JP2001242487A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the scale of a circuit, without having to perform the adding and the changing of a manufacturing process in the peripheral driving of a liquid crystal display device. SOLUTION: An SWpa, which is a P-ch TFT and an SWpb being a P-ch TFT are connected respectively to a signal line S1, and a signal line S2 and source electrodes of the SWpa, SWpb are connected to a common video bus P1 having a positive polarity. At this time, contact holes 221 in a P-ch source electrode 220 are constituted, so as to be shared with SWpa, SWpb.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, a flat display device represented by a liquid crystal display device has been used as a display device of various devices because of its low power consumption in addition to being thin and lightweight. Among them, an active matrix type liquid crystal display device (hereinafter referred to as a TFT-LCD) provided with a pixel switching element composed of a thin film transistor (TFT) for each display pixel arranged in a matrix has a clear image quality and is equivalent to a CRT. Since it has higher display performance than that, it is used in a field where a high definition display image is required.

In recent years, in particular, a thin film transistor type liquid crystal display device having a built-in drive circuit has been developed in order to increase the effective screen area on a transparent insulating substrate having the same area and reduce the manufacturing cost. This is because a display pixel is formed by a scanning line driving circuit that supplies a scanning signal to a pixel switching element via a scanning line, and a signal line driving circuit that supplies a video signal to a pixel switching element via a signal line. It is formed integrally on a transparent insulating substrate. Among them, a sample-and-hold (S / H) type drive in which sampling is controlled by a timing control circuit including a shift register and the like, and a video signal supplied via a signal line is held in a signal line capacitor and then written in a pixel capacitor. Development of a TFT-LCD with a built-in circuit is underway.

FIG. 11 is a circuit diagram of a TFT-LCD with a built-in general S / H type driving circuit. This TFT-L
The CD 100 includes a display unit 110 configured as a light transmission type liquid crystal panel, a scanning line driving circuit 120, and a signal line driving circuit 130, and is integrally formed on a transparent insulating substrate (array substrate) (not shown). ing.

The display unit 110 includes a plurality of signal lines 11.
One and a plurality of scanning lines 112 intersecting with the scanning lines 112 are arranged in a matrix, and a thin film transistor 113 serving as a pixel switching element is arranged near an intersection of the two lines. The thin film transistor 113 has a source electrode connected to the signal line 111 and a drain electrode connected to the pixel electrode 114.
It is connected to the. A liquid crystal layer 116 is sandwiched between the pixel electrode 114 and the counter electrode 115 to form a liquid crystal capacitance Clc. Further, the storage capacitor unit 11 is connected in parallel with the liquid crystal layer 116.
7 are connected to form an auxiliary capacitance Cs. Signal line 1
The video signal written through 11 is held by the liquid crystal capacitance Clc and the auxiliary capacitance Cs for a predetermined period. The counter electrode 115 is connected to a not-shown counter electrode driving circuit, and is given a predetermined common potential (Vcom).

The scanning line driving circuit 120 includes a plurality of sets of shift registers (S / R) 121 and a scanning line driving buffer 12.
2 and a vertical synchronizing signal (IN2) and a vertical clock signal (C) supplied from an external drive circuit (not shown).
LK2), and sequentially outputs a scanning signal to each scanning line 112.

The signal line driving circuit 130 includes a plurality of shift registers (S / R) 131, a sampling switch driving buffer 132, a video bus 133, and a sampling switch 134. Each sampling switch 134 is connected to the signal line 111, respectively.
The shift register 131 includes a horizontal synchronization signal (IN1) and a horizontal clock signal (C) supplied from the external driving circuit.
LK1), the sampling switch 134 is controlled via the sampling switch driving buffer 132 and the sampling switch control line 135, and the video signals (Video1, 2,...) Supplied from the external driving circuit are controlled.
N) is sampled on the signal line 111 at a predetermined timing.

Reference numeral 140 denotes a frame portion which is an area (an area where the scanning line driving circuit 120 and the signal line driving circuit 130 are arranged) excluding the display section 110 from the surface area of the transparent insulating substrate.

The TFT-LCD 1 configured as described above
00, the driving circuit (120, 130) is connected to the display unit 110.
It can be manufactured in the same manufacturing process as that described above, and can be integrally formed on a transparent insulating substrate such as an inexpensive glass substrate. Therefore, the driving circuit is manufactured at a lower cost compared to a TFT-LCD mounted with a TAB method. It becomes possible.

[0010]

By the way, in the TFT-LCD 100 as shown in FIG.
0, 130) on the same transparent insulating substrate as the display unit 110, the area of the frame unit 140 tends to be larger than that in the case where the drive circuit is mounted by the TAB method.
On the other hand, in the market, if the display screen size is the same,
There is a demand for a more compact overall size, and in order to reduce the area of the frame portion 140, it is necessary to reduce the circuit scale of a thin film transistor included in the driving circuit. However, in recent years, the size of the liquid crystal display device has been increasing, and the size of the transparent insulating substrate has been increasing.Moreover, since many panels are manufactured from one transparent insulating substrate,
Transparent insulating substrates are increasing in size. In such a large-sized transparent insulating substrate, shrinkage (expansion / shrinkage) of the substrate, processing variations in the transparent insulating substrate become large, and an alignment accuracy of an exposure machine accompanying the enlargement of the transparent insulating substrate is 1 μm.
m or more, it is considered extremely difficult to reduce the size of the drive circuit even further.

An object of the present invention is to provide a liquid crystal display device capable of reducing the circuit scale without adding or changing a manufacturing process.

[0012]

In order to achieve the above object, the invention according to claim 1 comprises a plurality of signal lines and a plurality of scanning lines intersecting each other, and arranged near each intersection of the signal lines and the scanning lines. A switching element, an array substrate including a pixel electrode connected to the switching element, a counter substrate including a counter electrode facing the pixel electrode, and a liquid crystal layer held between the array substrate and the counter substrate. A liquid crystal display panel, a signal line driving circuit for supplying a video signal to the signal line, a scanning line driving circuit for supplying a scanning signal to the scanning line, and a circuit for driving the signal line driving circuit and the scanning line driving circuit. In a liquid crystal display device having an external drive circuit, the signal line drive circuit, a positive video bus group transmitting a positive video signal, a negative video bus group transmitting a negative video signal, each A plurality of positive polarity switches connected to one of the positive video bus groups via connection wiring, and a plurality of negative polarity switches each connected to one of the negative video bus groups via connection wiring A switch and a switch pair including the adjacent positive polarity switch and the adjacent negative polarity switch are connected to the common signal line, and the positive polarity switch includes a P-type thin film transistor, and the negative polarity switch includes an N-type thin film transistor. And
The positive electrode switch connected to the (2N-1) th (N: natural number) signal line and the source electrode of the positive switch connected to the (2N) th signal line are connected to the positive electrode via a common contact hole. It is characterized by being connected to one of the sex video bus groups.

According to a second aspect of the present invention, in the first aspect, the signal line driving circuit is connected to a negative switch connected to a (2N) th signal line and to a (2N + 1) th signal line. The source electrode of the negative switch is connected to one of the negative video bus groups through a common contact hole.

According to a third aspect of the present invention, there are provided a plurality of signal lines and a plurality of scanning lines which intersect each other, a switching element arranged near each intersection of the signal line and the scanning line, and a pixel connected to the switching element. An array substrate including electrodes, a counter substrate including a counter electrode facing the pixel electrode, a liquid crystal display panel having a liquid crystal layer held between the array substrate and the counter substrate, and supplying a video signal to the signal line. A liquid crystal display device comprising a signal line driving circuit, a scanning line driving circuit for supplying a scanning signal to the scanning line, and an external driving circuit for driving the signal line driving circuit and the scanning line driving circuit. The signal line driving circuit includes a positive video bus group transmitting a positive video signal, a negative video bus group transmitting a negative video signal, and each of the positive video buses via a connection line. A plurality of positive switches connected to one of the plurality, a plurality of negative switches each connected to one of the negative video bus group via a connection wiring, the adjacent positive switch and the negative A switch pair including a negative switch is connected to the common signal line, the positive switch is a P-type thin film transistor, the negative switch is an N-type thin film transistor, and the signal line driving circuit is (2N− 1) The first (N: natural number)
And the source electrode of the negative switch connected to the (2N) th signal line is connected to one of the negative video bus groups via a common contact hole. It is characterized by being performed.

According to a fourth aspect of the present invention, in the third aspect, the source electrode of the positive polarity switch connected to the (2N) th signal line and the positive electrode switch connected to the (2N + 1) th signal line are provided. Are connected to one of the positive video bus groups via a common contact hole.

According to the first to fourth aspects of the present invention, compared with the conventional structure in which the contact holes in the source region of the N-type thin film transistor and the source region of the P-type thin film transistor are individually formed, even if the pixel pitch is narrower, the parallel arrangement is possible. Can be arranged. For this reason, even in the case where the P-type thin film transistor and the N-type thin film transistor must be alternately arranged in the conventional structure, if the pixel pitch is within a range where the P-type thin film transistor and the N-type thin film transistor can be arranged in parallel, the conventional structure is used. The circuit scale can be reduced as compared with the structure.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the liquid crystal display device according to the present invention will be described.

[First Embodiment] FIG. 1 is a circuit configuration diagram of a TFT-LCD according to a first embodiment, particularly a circuit configuration diagram of a signal line driving circuit 230. However, in this embodiment, a liquid crystal panel of eight-phase four-division driving is described as an example, and therefore, the circuit configuration is different from that of the signal line driving circuit 130 in FIG. The configuration of the other parts is the same as that of FIG. 11, and the same parts are denoted by the same reference numerals.

In FIG. 1, 32 blocks are arranged in parallel on a transparent insulating substrate (not shown), with 24 signal lines S1 to S24 as one block (1 in FIG. 1).
Only the blocks are shown). These signal lines are driven by a signal line driving circuit 230 integrated on the same substrate.

The signal line drive circuit 230 is a clocked inverter type shift register 150 (of 32 stages in FIG. 1) driven by a horizontal synchronization signal IN1, horizontal clock signals XCLK1 and XCLK2 supplied from an external drive circuit (not shown). And video buses P1 to P12 to which positive polarity video signals are supplied, video buses N1 to N12 to which negative polarity video signals are supplied, and the output of the shift register 150, Buses P1 to P
12, Pch sampling switches SWpa, SWpb, SWpc, SWpxd,... For transmitting video signals supplied to the respective N1 to N12 to the signal lines S1 to S24.
SWpx, Nch sampling switches SWna, S
Wnx, SWnc, SWnd... SWnx.

The display screen of the liquid crystal panel of this embodiment is vertically divided into four parts. And in one area,
The above-mentioned 24 signal lines S1 to S24 (1 block) are arranged in 32 blocks in parallel.

The output of the shift register 150 is distributed to timing signal lines TS1 to TS4 corresponding to 24 signal lines S1 to S24 via a signal switching circuit 160. The timing signal lines TS1 to TS4 are connected to the sampling switches SWna to SWnx, SWpa to SWna, respectively.
SWpx is connected to the gate electrode of the MOS transistor.

The signal switching circuit 160 is supplied with a polarity inversion signal Vpol from an external drive circuit (not shown), and switches the polarity of the video signal output to each signal line for each frame for polarity inversion driving. Can be As a result, a video signal of a positive polarity and a video signal of a negative polarity are alternately output to adjacent signal lines for each frame.

FIG. 2 shows the signal lines S1, S2, S2 of FIG.
3 is an enlarged configuration diagram of a sampling switch connected to S24. FIG.

Sampling switches SWpa, SWpb
Is connected to the positive video bus P1, and the sampling switches SWpw and SWpx are connected to the positive video bus P12.
It is connected to the. These sampling switches are
It is an analog switch composed of a PchTFT. The sampling switches SWna and SWnb are connected to the video bus N1 having a negative polarity, and are connected to the sampling switch SWn.
w and SWnx are connected to a video bus N12 of negative polarity. These sampling switches are NchTFT
Analog switch.

Pch and Nch analog switches are arranged in parallel on the signal lines S1, S2... S23 and S24.
0 is commonly connected to enable polarity inversion driving.

In this embodiment, it is assumed that the V-line inversion drive is performed. When the (2N-1) -th (N: natural number) signal lines S1, S3,.
(2N) -th signal lines S2, S4... S24 have a negative polarity, and when signal lines S1, S3... S23 have a negative polarity, signal lines S2, S4. . This polarity is inverted every frame to provide an image without flicker.

This pair of analog switches must be configured with a width within one dot pitch. Signal line S1
Is connected to SWp, which is a PchTFT, and to the signal line S2, SWpb, which is a PchTFT.
The source electrodes of Wpa and SWpb are connected to a common positive video bus P1. At this time, the contact hole 221 in the Pch source electrode 220 is SWp
a, SWpb.

According to this, the width of the pair of analog switches can be shortened.
Analog switches can be arranged without increasing the frame size to the dot size of the μm pitch.

FIG. 3 is an explanatory diagram showing an arrangement of video signals supplied to each video bus. Video bus P1, P2
.. P12, N1, N2... The video signal supplied to N12 is inverted in polarity every frame by the polarity inversion signal Vpol. When the V-line inversion driving is performed, the video bus P1 having the positive polarity is connected to the signal line S1 in the odd-numbered frame.
And supplies the video signal to the signal line S2 in the even frame. The video bus N1 of negative polarity is
In odd frames, a video signal is supplied to the signal line S2, and in even frames, a video signal is supplied to the signal line S1. Here, it is needless to say that the V-line inversion driving can be similarly performed even if the correspondence between the signal lines in the odd-numbered frames and the even-numbered frames is switched.

Second Embodiment In a second embodiment, an example will be described in which the arrangement of the sampling switches Pch and Nch in the TFT-LCD (FIG. 1) of the first embodiment is interchanged. That is, in the second embodiment, a description will be given of a TFT-LCD in which sampling switches are arranged in parallel and a contact hole in an Nch source electrode is shared. However, description of the circuit configuration of the TFT-LCD is omitted.

FIG. 4 shows signal lines S1 and S1 in the second embodiment.
FIG. 3 is an enlarged configuration diagram of a sampling switch connected to S2, S23, and S24, and portions that are the same as in FIG. 2 are given the same reference numerals.

Sampling switches SWpa, SWpb
Is connected to the positive video bus P1, and the sampling switches SWpw and SWpx are connected to the positive video bus P12.
It is connected to the. These sampling switches are
It is an analog switch composed of a PchTFT. Also,
The sampling switches SWna and SWnb are connected to the video bus N1 of negative polarity, and are connected to the sampling switch SWn.
w and SWnx are connected to a video bus N12 of negative polarity. These sampling switches are NchTFT
Analog switch.

Pch and Nch analog switches are arranged in parallel on the signal lines S1, S2... S23 and S24.
0 is commonly connected to enable polarity inversion driving.

In this embodiment, the description will be made assuming that the V-line inversion drive is performed.
When S1,..., S23 have a positive polarity, the (2N) th signal line S2, S4,..., S24 has a negative polarity, and when the signal lines S1, S3,. Line S2
S4 ... S24 have a positive polarity. This polarity is inverted every frame to provide an image without flicker.

The analog switches of this pair must have a width within one dot pitch. Signal line S1
Is connected to SWna, which is an Nch TFT, and SWnb, which is an Nch TFT, is connected to the signal line S2.
The source electrodes of Wna and SWnb are connected to a common negative video bus N1. At this time, the source electrode 32
0, SWna, SW
nb.

According to this, the width of the pair of analog switches can be shortened.
Analog switches can be arranged without increasing the frame size to the dot size of the μm pitch.

The video buses P1, P2... P1
The video signals supplied to 2, N1, N2,... N12 are the same as in FIG.

[Third Embodiment] In a third embodiment, a description will be given of a TFT-LCD in which sampling switches having the structure of the first embodiment are arranged in parallel, and the contact holes in the source electrodes of Pch and Nch are shared.

FIG. 5 shows a TFT-LC according to the third embodiment.
FIG. 3D is a circuit configuration diagram of the signal line driving circuit 330, in particular, FIG. Also in this embodiment, a description will be given of an example of an eight-phase four-split drive liquid crystal panel. Further, the arrangement of the sampling switch and the signal line driving circuit 230 in FIG.
Although the connections of the timing signal lines and the video bus are different, the configuration of the other parts is the same as that of FIG. 1, and the same parts are denoted by the same reference numerals.

In FIG. 5, 32 blocks are arranged in parallel on a transparent insulating substrate (not shown), with 24 signal lines S1 to S24 as one block (1 in FIG. 5).
Only the blocks are shown). These signal lines are driven by a signal line driving circuit 330 integrated on the same substrate.

The signal line driving circuit 330 is a clocked inverter type shift register 150 driven by a horizontal synchronizing signal IN1 and horizontal clock signals XCLK1 and XCLK2 supplied from an external driving circuit (not shown). ), Video buses P1 to P13 to which positive polarity video signals are supplied, video buses N1 to N12 to which negative polarity video signals are supplied, and an output of the shift register 150, Buses P1 to P
13, Pch sampling switches SWpa, SWpb, SWpc, SWpd... S for transmitting video signals supplied to the respective N1 to N12 to the signal lines S1 to S24.
Wpw, SWpx, Nch sampling switch SW
na, SWnb, SWnc, SWnd... SWnw,
SWnx.

In the configuration of this embodiment, the source electrode of the sampling switch SWpa is independently connected to the positive video bus P1, so that the number of the positive video bus is one more than that of the negative video bus. Configuration.

The display screen of the liquid crystal panel of this embodiment is also divided into four parts. In the area of one division, 32 signal lines S1 to S24 (one block) described above are arranged in parallel in 32 blocks.

The output of the shift register 150 is distributed via the signal switching circuit 260 to timing signal lines TS1 to TS4 corresponding to the 24 signal lines S1 to S24. The timing signal lines TS1 to TS4 are connected to the sampling switches SWna to SWnx, SWpa to SWna, respectively.
SWpx is connected to the gate electrode of the MOS transistor.

The signal switching circuit 260 is supplied with a polarity inversion signal Vpol from an external drive circuit (not shown), and switches the polarity of the video signal output to each signal line for each frame for polarity inversion driving. Can be As a result, a video signal of a positive polarity and a video signal of a negative polarity are alternately output to adjacent signal lines for each frame.

FIG. 6 shows the signal lines S1, S2, S3,
It is an enlarged block diagram of the sampling switch connected to S4.

The sampling switch SWpa is connected to the video bus P1 of positive polarity, and the sampling switch SWpa
pb and SWpc are connected to the video bus P2 of positive polarity. These sampling switches are PchTFT
Analog switch. The sampling switches SWna and SWnb are connected to a negative video bus N1, and the sampling switches SWnc and SWnd are connected to a negative video bus N2. These sampling switches are analog switches composed of Nch TFTs.

Pc is connected to the signal lines S1, S2, S3 and S4.
The analog switches of h and Nch are arranged in parallel as a pair, and the respective drain electrodes 410 are connected in common, thereby enabling the polarity inversion drive.

In this embodiment, the description will be made assuming that the V-line inversion drive is performed. In other words, the (2N-1) th signal line S
When 1, S3 (... S23) have a positive polarity, the (2N) -th signal line S2, S4 (... S24) has a negative polarity,
When the signal lines S1 and S3 (... S23) have a negative polarity,
The signal lines S2 and S4 (... S24) have a positive polarity. This polarity is inverted every frame to provide an image without flicker.

The analog switches of this pair must have a width within one dot pitch. Signal line S1
Is a Pch TFT SWpa, and a signal line S2 is P
SWpb which is a chTFT, and Pc is connected to the signal line S3.
SWpc, which is an hTFT, is connected to each other. The source electrodes of SWpb and SWpc are connected to a common positive video bus P2. Further, the signal line S1 is connected to an SWch which is an NchTFT, and the signal line S2 is connected to an SWnb which is an NchTFT. The source electrodes of SWna and SWnb are connected to a common negative video bus N1. And
Contact hole 4 in Pch source electrode 420
Reference numeral 21 is shared by SWpb and SWpc. The contact hole 4 in the Nch source electrode 430
Reference numeral 31 is shared by SWna and SWnb and SWnc and SWnd.

According to this, the width of the pair of analog switches can be shortened.
The analog switches can be arranged without increasing the frame size up to the dot size of the μm pitch.

FIG. 7 is an explanatory diagram showing an arrangement of video signals supplied to each video bus. Video bus P1, P2
.. The video signals supplied to P13, N1, N2,... N12 are inverted for each frame by the polarity inversion signal Vpol. When the V line inversion driving is performed, the video bus P2 of the positive polarity is connected to the signal line S3 in the odd-numbered frame.
And supplies the video signal to the signal line S2 in the even frame. The video bus P1 of positive polarity supplies a video signal to the signal line S1 only in odd frames, and the video bus P13 of positive polarity supplies a video signal to the signal line S24 only of odd frames. On the other hand, the video bus N1 of the negative polarity supplies a video signal to the signal line S2 in an odd frame, and supplies a video signal to the signal line S1 in an even frame. Here, it is needless to say that the V-line inversion driving can be similarly performed even if the correspondence between the signal lines in the odd-numbered frames and the even-numbered frames is switched.

Fourth Embodiment In a fourth embodiment, an example will be described in which the arrangement of the sampling switches Pch and Nch in the TFT-LCD (FIG. 5) of the third embodiment is interchanged.

FIG. 8 shows a TFT-LC according to the fourth embodiment.
FIG. 3D is a circuit configuration diagram of the signal line driving circuit 430, in particular, FIG. Also in this embodiment, a description will be given of an example of an eight-phase four-split drive liquid crystal panel. In addition, the signal line driving circuit 330 in FIG.
Although the connections of the timing signal lines and the video bus are different, the configuration of the other parts is the same as that of FIG. 5, and the same parts are denoted by the same reference numerals.

In FIG. 8, on a transparent insulating substrate (not shown), 32 blocks are arranged in parallel with 24 signal lines S1 to S24 as one block (1 block in FIG. 8).
Only the blocks are shown). These signal lines are driven by a signal line driving circuit 430 integrated on the same substrate.

The signal line drive circuit 430 is a clocked inverter type shift register 150 (in FIG. 8, of 32 stages) driven by a horizontal synchronization signal IN1, horizontal clock signals XCLK1 and XCLK2 supplied from an external drive circuit (not shown). ), Video buses P1 to P12 to which positive polarity video signals are supplied, video buses N1 to N13 to which negative polarity video signals are supplied, and the output of the shift register 150, Buses P1 to P
12, Pch sampling switches SWpa, SWpb, SWpc, SWpd... S for transmitting video signals supplied to the respective N1 to N13 to the signal lines S1 to S24.
Wpw, SWpx, Nch sampling switch SW
na, SWnb, SWnc, SWnd... SWnw,
SWnx.

In the configuration of this embodiment, since the source electrode of the sampling switch SWnx is connected to the negative video bus N13 by itself, the negative video bus is one more than the positive video bus. Configuration.

The display screen of the liquid crystal panel of this embodiment is also divided into four parts. In the area of one division, 32 signal lines S1 to S24 (one block) described above are arranged in parallel in 32 blocks.

The output of the shift register 150 is distributed to timing signal lines TS1 to TS4 corresponding to 24 signal lines S1 to S24 via a signal switching circuit 360. The timing signal lines TS1 to TS4 are connected to the sampling switches SWna to SWnx and SWpa to SWna, respectively.
SWpx is connected to the gate electrode of the MOS transistor.

The signal switching circuit 360 is supplied with a polarity inversion signal Vpol from an external driving circuit (not shown), and switches the polarity of the video signal output to each signal line for each frame for polarity inversion driving. Can be As a result, a video signal of a positive polarity and a video signal of a negative polarity are alternately output to adjacent signal lines for each frame.

FIG. 9 shows the signal lines S1, S2, S3,
It is an enlarged block diagram of the sampling switch connected to S4.

The sampling switch SWna is connected to the negative video bus N1.
nb and SWnc are connected to the negative video bus N2. These sampling switches are NchTFT
Analog switch. The sampling switches SWpa and SWpb are connected to a video bus P1 of positive polarity, and the sampling switches SWpc and SWpd are connected to a video bus P2 of positive polarity. These sampling switches are analog switches composed of PchTFTs.

The signal lines S1, S2, S3, and S4 have Pc
The analog switches of h and Nch are arranged in parallel as a pair, and the respective drain electrodes 510 are connected in common, thereby enabling the polarity inversion drive.

In this embodiment, the description will be made assuming that the V-line inversion drive is performed.
When 1, S3 (... S23) have a positive polarity, the (2N) -th signal line S2, S4 (... S24) has a negative polarity,
When the signal lines S1 and S3 (... S23) have a negative polarity,
The signal lines S2 and S4 (... S24) have a positive polarity. This polarity is inverted every frame to provide an image without flicker.

This pair of analog switches must be configured with a width within one dot pitch. Signal line S1
Is an Nch TFT SWna, and the signal line S2 is N
SWnb, which is a chTFT, and Nc is connected to the signal line S3.
SWncs, which are hTFTs, are connected to each other. The source electrodes of SWnb and SWnc are connected to a common negative video bus N2. Also, the signal line S
1 is connected to SWpa which is a PchTFT, and the signal line S2 is connected to SWpb which is a PchTFT. The source electrodes of SWpa and SWpb are connected to a common positive video bus P1. Further, the contact hole 521 in the Nch source electrode 520 is
SWnb and SWnc are common. The contact hole 531 in the Pch source electrode 530 is
SWpa and SWpb are common to SWpc and SWpd.

According to this, the width of the pair of analog switches can be shortened.
Analog switches can be arranged without increasing the frame size to the dot size of the μm pitch.

FIG. 10 is an explanatory diagram showing an arrangement of video signals supplied to each video bus. Video bus P1, P2
.., P12, N1, N2,..., N13 are inverted in polarity for each frame by a polarity inversion signal Vpol. When the V line inversion drive is performed,
The video bus P1 of the positive polarity is connected to the signal line S in the odd frame.
1 and the video signal is supplied to the signal line S2 in the even frame. On the other hand, the negative polarity video bus N2
Supplies a video signal to the signal line S3 in an odd frame,
In the even frame, a video signal is supplied to the signal line S2. Similarly, the video bus N1 of the negative polarity supplies the video signal to the signal line S1 only in the even frame, and the video bus N13 of the negative polarity supplies the video signal to S24 only in the odd frame. Here, it is needless to say that the V-line inversion driving can be similarly performed even if the correspondence relationship between the signal lines in the odd-numbered frames and the even-numbered frames is switched.

In the first to fourth embodiments, the contact hole on the drain side of the transmission gate may be shared.

The drain-side contact hole and the source-side contact hole of the transmission gate may be shared. In this case, the width can be further reduced as compared with the transmission gate having the conventional structure.

[0071]

As described above, in the liquid crystal display device according to the present invention, the drain region or the source region of the N-type thin film transistor and the drain region or the source region of the P-type thin film transistor which have the same electric potential are connected. Since the holes are shared, the elements can be arranged in parallel even at a narrower pixel pitch than in the case where the elements are configured by a CMOS circuit including a thin film transistor having a conventional structure. According to this, the circuit scale can be reduced as long as the pixel pitch is within the range in which the elements can be arranged in parallel. In particular, in the case of a liquid crystal display device with a built-in S / H drive circuit, a simple With this configuration, the area of the frame can be reduced.

Further, since the thin film transistor can be formed on the transparent insulating substrate by the same manufacturing process as that of the related art, the L length of the thin film transistor can be shortened or the manufacturing process can be added or changed as in the method of reducing the contact size. No longer needed
There is no decrease in productivity or increase in cost.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a TFT-LCD according to a first embodiment.

FIG. 2 is an enlarged configuration diagram of a sampling switch shown in FIG. 1;

FIG. 3 is an explanatory diagram showing an arrangement of video signals supplied to each video bus of FIG. 2;

FIG. 4 is an enlarged configuration diagram of a sampling switch according to a second embodiment.

FIG. 5 is a circuit configuration diagram of a TFT-LCD according to a third embodiment.

FIG. 6 is an enlarged configuration diagram of the sampling switch shown in FIG. 5;

FIG. 7 is an explanatory diagram showing an arrangement of video signals supplied to each video bus of FIG. 6;

FIG. 8 is a circuit configuration diagram of a TFT-LCD according to a fourth embodiment.

FIG. 9 is an enlarged configuration diagram of the sampling switch shown in FIG. 8;

FIG. 10 is an explanatory diagram showing an arrangement of video signals supplied to each video bus of FIG. 9;

FIG. 11 shows a TFT-L having a built-in general S / H drive circuit.
FIG. 3 is a circuit configuration diagram of a CD.

[Explanation of symbols]

110: display unit, 111: signal line, 112: scanning line 113: thin film transistor, 114: pixel electrode, 115
... counter electrode 120 ... scanning line driving circuit, 130 ... signal line driving circuit, 1
40 ... Frame

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H092 GA29 GA59 JA24 JB22 JB31 JB61 NA25 PA06 2H093 NA16 NA31 NC09 NC11 NC16 NC27 NC34 ND42 ND52 NE07 5C094 AA43 AA44 AA45 BA03 BA43 CA19 DA09 EA05 EB02 HA08 5F110 AA04 DD03 NN72 NN78

Claims (4)

[Claims] 1. An array substrate including a plurality of signal lines and a plurality of scanning lines crossing each other, a switch element disposed near each intersection of the signal line and the scanning line, and a pixel electrode connected to the switch element. A counter substrate including a counter electrode facing the pixel electrode, a liquid crystal display panel having a liquid crystal layer held between the array substrate and the counter substrate, and a signal line driving circuit for supplying a video signal to the signal line A liquid crystal display device comprising: a scanning line driving circuit for supplying a scanning signal to the scanning line; and an external driving circuit for driving the signal line driving circuit and the scanning line driving circuit. A positive video bus group for transmitting a positive video signal, a negative video bus group for transmitting a negative video signal, each of which is connected to one of the positive video bus groups via a connection wiring. Sa A plurality of positive polarity switches, a plurality of negative polarity switches each connected to one of the negative polarity video bus groups via a connection wiring, and a switch including the adjacent positive polarity switch and the negative polarity switch The pair is connected to the common signal line, the positive switch is a P-type thin film transistor, and the negative switch is an N-type thin film transistor, and is connected to the (2N-1) th (N: natural number) signal line. And the source electrode of the positive switch connected to the (2N) th signal line is connected to one of the positive video bus groups via a common contact hole. Liquid crystal display device. 2. The liquid crystal display device according to claim 1, wherein a source electrode of the negative polarity switch connected to the (2N) th signal line and a source electrode of the negative polarity switch connected to the (2N + 1) th signal line are common. The liquid crystal display device is connected to one of the negative video bus groups through the contact hole. 3. An array substrate including a plurality of signal lines and a plurality of scanning lines that intersect each other, a switching element disposed near each intersection of the signal line and the scanning line, and a pixel electrode connected to the switching element. A counter substrate including a counter electrode facing the pixel electrode, a liquid crystal display panel having a liquid crystal layer held between the array substrate and the counter substrate, and a signal line driving circuit for supplying a video signal to the signal line A liquid crystal display device comprising: a scanning line driving circuit for supplying a scanning signal to the scanning line; and an external driving circuit for driving the signal line driving circuit and the scanning line driving circuit. A positive video bus group for transmitting a positive video signal, a negative video bus group for transmitting a negative video signal, each of which is connected to one of the positive video bus groups via a connection wiring. Sa A plurality of positive polarity switches, a plurality of negative polarity switches each connected to one of the negative polarity video bus groups via a connection wiring, and a switch including the adjacent positive polarity switch and the negative polarity switch The pair is connected to the common signal line, the positive switch is a P-type thin film transistor, and the negative switch is an N-type thin film transistor, and is connected to the (2N-1) th (N: natural number) signal line. And the source electrode of the negative switch connected to the (2N) th signal line is connected to one of the negative video bus groups via a common contact hole. Liquid crystal display device. 4. The liquid crystal display device according to claim 3, wherein a source electrode of the positive polarity switch connected to the (2N) th signal line and a source electrode of the positive polarity switch connected to the (2N + 1) th signal line are common. The liquid crystal display device is connected to one of the positive video bus groups through the contact hole.