JP4621454B2 - Display device drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To turn a switching element ON for a sufficient period of time with respect to both of a video display and a black display in a driving circuit of a display apparatus in which the black display is inserted in a certain period in addition to the video display within one frame period. <P>SOLUTION: The driving circuit includes: a shift register 38 for an video signal; a shift register 39 for a black display signal; a plurality of buffers 40 disposed in the output stage of the respective shift registers for video signals, each buffer outputting an enable signal to a scan line to turn on a switching element over one horizontal scanning period according to a control pulse for the video signal or the black display signal after phase shift; and further, supply lines OE1, OE2 of an enable signal for the video signal and a supply line OEK of an enable signal for the black display signal. Two supply lines OE1, OE2 for video signals are alternately connected to the input terminal OEK of each buffer 40, and the supply line OEK for black display signals is connected to the input terminal OEK of each buffer 40. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to a drive circuit for a display device in which video display is performed within one frame period and black display is inserted for a certain period.

  A display device typified by a liquid crystal display device is thin, lightweight, and has low power consumption, and is therefore used as a display for various devices. In particular, an active matrix liquid crystal display device in which a transistor is arranged for each pixel is becoming widespread as a display for a notebook personal computer or a portable information terminal.

  In recent years, a polysilicon TFT (p-Si TFT) having a higher electron mobility than a thin film transistor (hereinafter referred to as TFT) made of amorphous silicon used in a conventional liquid crystal display device is manufactured at a relatively low temperature process. The forming technology has been established, and the transistor used in the liquid crystal display device can be downsized. As a result, a pixel portion having a transistor and a pixel electrode at each intersection of a plurality of scanning lines and a plurality of signal lines and a driving circuit for driving each transistor are integrally formed on a transparent substrate by the same manufacturing process. I was able to do that.

  In parallel with this, the development of the drive circuit of the liquid crystal display device is also progressing. In recent years, for the purpose of improving the visibility of moving images, the black level voltage for a certain period is written simultaneously to a plurality of pixel electrodes for each frame. A drive circuit has been developed in which afterimage is eliminated by black display and blurring of the image is prevented (see, for example, Patent Document 1).

  A conventional scanning line driving circuit will be described below with reference to the drawings.

  FIG. 10 is a block diagram showing a configuration of a conventional scanning line driving circuit. The scanning line driving circuit includes a plurality of video signal shift registers 38 that output the phase of the control pulse for the video signal by shifting each shift register, and the phase of the control pulse for the black display signal by each shift register. A plurality of black display signal shift registers 39 that are shifted and output, and provided at the output stage of each video signal shift register, scan the enable signal according to the control pulse for the video signal or black display signal after the phase shift. It comprises a plurality of buffers 41 that output to a line.

  The output terminal of each video signal shift register 38 is connected to the input terminal of the next-stage video signal shift register and the input terminal SIN of each buffer 41. The output terminal of each black display signal shift register 39 is connected to the input terminal of the next black display signal shift register and the input terminal KIN of each buffer 41. The output terminal BOUT of each buffer 41 is connected to each scan. Connected to the line. A supply line OE1 that supplies one enable signal is connected to the input terminal OE of each buffer 41. Each buffer 41 outputs OE (Output Enable) that is an enable signal in accordance with a control pulse that is output from the video signal shift register 38 or a control pulse that is output from the black display signal shift register 39.

  In the drive circuit shown in FIG. 6, as an example, four video signal shifts are performed with respect to one black display signal shift register 39 so that black display signals can be simultaneously written to four scanning lines. A block 42 having a register 38 and four buffers 41 as a unit is electrically connected in a vertical stage. In addition, the same code | symbol is attached | subjected to the same thing in the figure.

  FIG. 11 is a circuit diagram showing a configuration of a buffer in a conventional scanning line driving circuit. Here, a case where only a pMOS transistor is used is shown.

The buffer circuit is connected to an input terminal SIN of the buffer, a control electrode to which a video signal control pulse is input, an input electrode to which a first power supply voltage VDD is supplied, a first s transistor T1s having an output electrode, A control electrode connected to the input terminal KIN to which a control pulse for a black display signal is input, an input electrode to which a first power supply voltage VDD is supplied, a first k transistor T1k having an output electrode, and a second power supply voltage VSS are supplied A first inverter circuit having a second transistor T2 having a control electrode, an input electrode, and an output electrode, and a control electrode connected to each output electrode of the first s transistor T1s, the first k transistor T1k, and the second transistor T2 A third transistor T3 having an input electrode and an output electrode to which the first power supply voltage VDD is supplied; Connected to the terminal SIN, connected to the control electrode to which the control pulse for the video signal is input, the input electrode to which the second power supply voltage VSS is supplied, the fourth s transistor T4s having the output electrode, and the input terminal KIN of the buffer, A second inverter circuit having a fourth k transistor T4k having a control electrode to which a control pulse for black display signal is input, an input electrode to which the second power supply voltage VSS is supplied, and an output electrode, and a first s transistor T1s and a first k A fifth transistor T5 having a control electrode connected to the respective output electrodes of the transistor T1k and the second transistor T2, an input electrode supplied with the first power supply voltage VDD, and an output electrode connected to the output terminal BOUT of the buffer; Output electrodes of the fourth s transistor T4s, the fourth k transistor T4k, and the third transistor T3 And an output circuit having a sixth transistor T6 having an input electrode, an output electrode connected to the output terminal BOUT of the buffer continues a control electrode, the enable signal OE1 is input.

  The buffer circuit further includes a seventh transistor T7 connected between the output of the second inverter circuit and the control electrode of the sixth transistor T6. The seventh transistor T7 is arranged to reduce the voltage applied to the third transistor T3.

  FIG. 12 is a timing chart showing an example of the operation of the conventional liquid crystal display device. One frame period P1 shown in the figure is composed of a video signal period P2 in which a video signal voltage is applied to the pixel electrode 36 and a black display signal insertion period P3 in which a black display signal voltage is applied to the pixel electrode 36.

  FIG. 6A shows the scanning timing for each scanning line 31 (G1 to G16 in the figure). In each of the video signal period P2 and the black display signal insertion period P3, all the scanning lines 31 are sequentially scanned. Here, the writing of the black display signal is performed simultaneously for four rows in order to reduce the width of one horizontal scanning period P4 by adding the black display signal writing scan. That is, in the figure, as the video signal write scan, the first scan line G1 to the fourth scan line G4 are sequentially scanned, and then the black display signal write scan is performed from the 13th scan line G13 to the 16th scan line. The four rows up to the scanning line G16 are simultaneously scanned at once, and this operation is repeated over one frame.

  FIG. 4B shows a change in voltage applied to a certain pixel electrode 36 corresponding to the first scanning line G <b> 1 through the signal line 32. Here, a relatively low voltage is applied during the video signal period P2, and a relatively high voltage is applied during the black display signal insertion period P3. Further, in the driving method of the liquid crystal display device shown here, the applied voltage changes so that the voltage polarity of the signal to be written is inverted for each dot in each of the video signal period P2 and the black display signal insertion period P3. It is a dot inversion drive type.

  FIG. 13 is a timing chart for explaining the operation of the buffer circuit in the conventional scanning line driving circuit. In the figure, the period during which the OE signal is low is set shorter than the period during which Sin or Kin, which is the output signal of each shift register, is low. First, the operation of the circuit when supplying the output signal Sin (2) of the video signal shift register to the buffer connected to the scanning line G2 will be described with reference to the circuit diagram of FIG.

  When the output signal Sin (2) of the low level video signal shift register is input to the input terminal SIN of the buffer circuit at time t1, the first s transistor T1s and the second transistor T2 constituting the first inverter circuit are Both are turned on, and the potential n1 (2) of the node n1 becomes high level. At this time, the third transistor T3 and the fourth s transistor T4s constituting the second inverter circuit are turned off and on, respectively, so that the low level is applied to the node n2 and the node n3 via the fourth s transistor T4s. The As the node n2 and the node n3 become low level, the gate-source voltage of the fourth s transistor T4s gradually decreases, so that the fourth s transistor T4s gradually changes from on to off. Therefore, the change of the node n2 and the node n3 to the low level is slow, and finally the node n2 and the node n3 are in the low level and in the floating state. As a result, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the output signal BOUT (2) of the buffer circuit becomes the high level because the enable signal OE1 is supplied through the sixth transistor T6.

  When the OE signal becomes low level at time t2, the potential n3 (2) of the node n3 becomes lower than the low level. This is because there is a parasitic capacitance between the gate and the source of the sixth transistor T6 or between the gate and the drain. Therefore, when the gate, that is, the node n3 is in a floating state, the potential variation between the drain and the source of the sixth transistor T6 is accompanied. This is because the potential of the node n3 varies. In this manner, a phenomenon in which the potential of a node in a floating state varies under the influence of potential variation in a connection destination transistor is referred to as a bootstrap, and the node at this time is referred to as a bootstrap node. As a result, the output signal BOUT (2) of the buffer circuit is at the low level because the OE signal is supplied through the sixth transistor T6.

  At time t3, when the output signal Sin (2) and the OE signal of the video signal shift register become high level, the potential n1 (2) of the node n1 becomes low level, and the potential n3 (2) of the node n3 becomes high level. Therefore, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off. As a result, the output signal BOUT (2) of the buffer circuit is at the high level because the first power supply voltage VDD is supplied through the fifth transistor T5.

  Next, the operation of the circuit when the output signals Kin (13) to (16) of the black display signal shift register are collectively supplied to the buffers connected to the four rows of scanning lines G13 to G16 will be described. Here, since the output signals Kin (13) to (16) of the black display signal shift register are all the same signal, the operation when the output signal Kin (13) is supplied to the buffer connected to the scanning line G13. The following description will be given with reference to the circuit diagram of FIG. 11 and FIG.

  At time t4, when the output signal Kin (13) of the low-level black display signal shift register is input to the input terminal KIN of the buffer circuit, the first k transistor T1k and the second transistor T2 constituting the first inverter circuit. Are both turned on, and the potential n1 (13) of the node n1 becomes a high level. Then, the third transistor T3 and the fourth k transistor T4k constituting the second inverter circuit are turned off and on, respectively, so that the node n2 and the node n3 are in a floating state, and n3 (13) is at a low level. . As a result, the output signal BOUT (13) of the buffer circuit becomes high level because the enable signal OE1 is supplied via the sixth transistor T6.

  When the OE signal becomes low level at time t5, the potential n3 (13) of the node n3 becomes lower than the low level. This is because there is a parasitic capacitance between the gate and the source of the sixth transistor T6 or between the gate and the drain. Therefore, when the gate, that is, the node n3 is in a floating state, the potential variation between the drain and the source of the sixth transistor T6 is accompanied. This is because the potential of the node n3 varies. In this manner, a phenomenon in which the potential of a node in a floating state varies under the influence of potential variation in a connection destination transistor is referred to as a bootstrap, and the node at this time is referred to as a bootstrap node. As a result, the output signal BOUT (13) of the buffer circuit becomes low level because the low level OE signal is supplied from the sixth transistor T6.

  At time t6, when the output signal Kin (13) of the black display signal shift register and the OE signal become high level, the potential of the node n1 becomes low level, and the potentials of the nodes n2 and n3 become high level. The fifth transistor T5 is turned on and the sixth transistor T6 is turned off. As a result, the output signal BOUT (13) of the buffer circuit is at the high level because the first power supply voltage is supplied through the fifth transistor T5.

After time t6, the output signals Sin (2) and Kin (13) of each shift register are both at the high level. At this time, the potentials of n1 (2) and n1 (13) are at the low level, and n3 (2) Since the potentials of n3 (13) are both kept at a high level, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off. As a result, the first power supply voltage is supplied to the output signals BOUT (2) and BOUT (13) through the T5 transistor regardless of the OE signal, and thus becomes the high level.
Japanese Patent Laid-Open No. 2003-140619

  In the conventional scanning line driving circuit for inserting a black display signal for a certain period within one frame period as shown in FIG. 10, there is only one supply line OE1 for supplying an OE signal, and each buffer has one buffer. It is connected to the supply line OE1. Therefore, as shown in the timing chart of FIG. 13, the enable signal OE1 must be set to a low level once during each horizontal scanning period. That is, when attention is paid to the potential n3 (2) of the node n3 at the time of the video signal or the potential n3 (13) of the node n3 at the time of the black display signal, the potential is sufficiently low during the period a in which OE1 is high. Next OE1 is set to low level.

  When the period a is short, the potential n3 (2) of the node n3 or the potential n3 (13) of the node n3 is not sufficiently low level, and OE1 becomes low level. However, since the T6 transistor is not sufficiently turned on, OE1 Is not supplied to the output terminal BOUT.

  If the period a is sufficiently long, the period b in which OE1 is at a low level is shortened, and the switching element cannot be turned on for a sufficient period. For this reason, particularly when the load on the scanning line is large, such as a large LCD, there arises a problem that the shortage of writing of the video signal and the black display signal to the pixel electrode increases.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device driving circuit capable of turning on switching elements for a sufficient period of time for both video display and black display. There is.

According to a first aspect of the present invention, there is provided a driving circuit for a display device, wherein a video signal or a black display signal supplied through a signal line to a pixel electrode provided at each intersection of a plurality of scanning lines and a plurality of signal lines. This is a drive circuit for a display device that drives a scanning line to control on / off of a switching element provided for each pixel electrode in order to control the writing of the image signal, and it takes two horizontal scanning periods for video signals. A plurality of video signal shift registers that shift and output the phase of the control pulse by each shift register, and the phase of the control pulse over two horizontal scanning periods for the black display signal are shifted by each shift register and output. a plurality of shift registers for the black display signal, provided at an output stage of the shift register for each video signal, is phase shifted by the shift register for the video signal and the black display signal Together with the control pulses of the video signal and the black display signal has a plurality of buffers are respectively input, and inputs the enable signal for the two video signals alternately, one for each buffer, the black display signal In response to the control pulse for the video signal or the black display signal after the phase shift, each buffer outputs the above-mentioned enable signal over the latter one horizontal scanning period of the two horizontal scanning periods for the control pulse. An enable signal capable of turning on the switching element is output .

 In the present invention, the operation of the transistors in the buffer is sufficiently stabilized in one horizontal scanning period of the first half of the control pulse over two horizontal scanning periods output from the video or black display signal shift register. After that, the switching element can be turned on for a sufficient period by outputting an enable signal that can turn on the switching element from the buffer to the scanning line over one horizontal scanning period in the latter half.

 In the present invention, two enable signals for video signals and one enable signal for black display signals are provided, and each buffer uses video signal enable signals alternately one by one. Each switching element corresponding to a plurality of scanning lines for signals is sequentially turned on for a sufficient period, and subsequently, corresponding to a plurality of scanning lines at an arbitrary position for black display signals by an enable signal for black display signals. A plurality of switching elements can be turned on for a sufficient period of time.

  According to a third aspect of the present invention, each buffer includes a control electrode to which a video signal control pulse is input, an input electrode to which a first power supply voltage is supplied, and an output electrode. 1s transistor, control electrode to which a control pulse for black display signal is input, input electrode to which a first power supply voltage is supplied, first k transistor having an output electrode, control electrode to which a second power supply voltage is supplied, and an input electrode An inverter circuit having a second transistor with an output electrode, a first s transistor, a first k transistor, a control electrode connected to each output electrode of the second transistor, an input electrode to which a first power supply voltage is supplied, and a buffer A fifth transistor having an output electrode connected to the output terminal, a control electrode to which a video signal control pulse is input, and an enable signal for the video signal Input electrode, a 6s transistor having an output electrode connected to the output terminal of the buffer, a control electrode to which a control pulse for black display signal is input, and an input electrode to which an enable signal for black display signal is input And an output circuit having a sixth k transistor having an output electrode connected to the output terminal of the buffer.

 In the present invention, in each buffer, the first s transistor and the second transistor constituting the inverter circuit are turned on, the fifth transistor constituting the output circuit is turned off, and the sixth s transistor is turned off according to the control pulse for the video signal. By turning it on, it becomes possible to output an enable signal for a video signal that can turn on the switching element provided for each pixel electrode to the scanning line. Further, according to the control pulse for the black display signal, the first k transistor and the second transistor constituting the inverter circuit are turned on, the fifth transistor constituting the output circuit is turned off, and the sixth k transistor is turned on for each pixel electrode. An enable signal for a black display signal that can turn on the provided switching element can be output to the scanning line.

  In addition to displaying video within the frame period of the present invention, in the display device drive circuit in which black display is inserted for a certain period, both the video display and black display can be turned on for a sufficient period of time. As a result, the video signal and the black display signal can be written to the pixel electrode for a sufficient period, and a good image free from unevenness due to insufficient writing can be realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a cross-sectional view illustrating an example of a configuration of a liquid crystal panel included in the liquid crystal display device according to the first embodiment. As shown in the figure, in the liquid crystal panel, the counter substrate 101 and the array substrate 102 are arranged to face each other via a spacer (not shown), and the liquid crystal layer 4 is disposed in the gap between the counter substrate 101 and the array substrate 102. Has been placed.

    In the counter substrate 101, the transparent electrode 2 and the alignment film 3 are sequentially laminated on the lower surface of the glass substrate 1. In the array substrate 102, the transparent electrode 6 and the alignment film 5 are sequentially laminated on the upper surface of the glass substrate 7. In addition, in order to perform color display, between the glass substrate 1 and the transparent electrode 2 constituting the counter substrate 101, color filters (not shown) for red, blue, and green that are the three primary colors of light. Is arranged. A retardation film 8 for compensating for the retardation of the liquid crystal layer 4 is disposed on the upper surface of the counter substrate 101. Similarly, a retardation film 9 is disposed on the lower surface of the array substrate 102. Further, a polarizing plate 10 is disposed on the upper surface of the retardation film 8, and a polarizing plate 11 is disposed on the lower surface of the retardation film 9. Liquid crystal molecules 20 are injected into the liquid crystal layer 4 between the alignment film 3 on the counter substrate 101 side and the alignment film 5 on the array substrate 102 side. It is assumed that the liquid crystal layer 4 in the present embodiment uses an optical compensated birefringence mode (hereinafter referred to as OCB mode).

  FIG. 2 is a cross-sectional view schematically showing the alignment state of the liquid crystal molecules 20. The liquid crystal molecules 20 have a splay alignment as shown in FIG. The alignment state of the liquid crystal molecules 20 is changed from the splay alignment to the bend alignment as shown in FIG. 5B by applying a predetermined voltage to the liquid crystal display element 100. The image display is performed in this bend orientation state.

  Since the liquid crystal display element 100 is a normally white mode display element, white display is performed when a relatively low voltage is applied, and black display is performed when a relatively high voltage is applied. I have to. Therefore, when a black display signal is written, a relatively high voltage is applied to the pixel electrode, so that the bend alignment can be maintained. At this time, since the afterimage is eliminated by the black display, it is possible to prevent the image from being blurred.

  FIG. 3 is a block diagram showing a configuration of the present liquid crystal display device. As shown in the figure, the liquid crystal display device includes a display area 37 for displaying an image, a scanning line driving circuit 34 for supplying a scanning line voltage, and a signal line driving circuit 35 for supplying a signal line voltage.

  The display area 37 includes a pixel electrode 36 and a switching element 33 at each intersection of a plurality of scanning lines 31 extending from the scanning line driving circuit 34 and a plurality of signal lines 32 extending from the signal line driving circuit 35. Are arranged in a matrix.

  The scanning line driving circuit 34 applies a control pulse sent from the vertical shift register to the scanning line 31 via a buffer. At this time, the scanning line driving circuit 34 drives the scanning line 31 that controls on / off of the switching element 33 that controls writing of the video signal or the black display signal.

  The signal line drive circuit 35 supplies the video signal and the black display signal corresponding to each pixel electrode 36 to the switching element 33 via the signal line 32. Here, for example, a thin film transistor (TFT) is used as the switching element 33. The gate terminal of the TFT is connected to the scanning line 31, the source terminal is connected to the signal line 32, and the drain terminal is connected to the pixel electrode 36. The scanning line driving circuit 34 is integrally formed on the transparent substrate by the same manufacturing process as the pixel portion having TFTs.

  FIG. 4 is a block diagram showing a configuration of the scanning line driving circuit 34. The scanning line driving circuit includes a plurality of video signal shift registers 38 that output the phase of the control pulse for the video signal by shifting each shift register, and the phase of the control pulse for the black display signal by each shift register. A plurality of black display signal shift registers 39 that are shifted and output are provided at the output stage of each video signal shift register, and each buffer is provided in accordance with the control pulse for the video signal or black display signal after the phase shift. And a plurality of buffers 40 that output enable signals capable of turning on the switching elements over one horizontal scanning period to the scanning lines.

  The output terminal of each video signal shift register 38 is connected to the input terminal of the video signal shift register in the next stage and the input terminal SIN of the buffer 40. The output of each black display signal shift register 39 is connected to the next stage. The input of the black display signal shift register and the input terminal KIN of the buffer 40 are connected to each other, and the output terminal BOUT of each buffer is connected to each scanning line. The W / L ratio (ratio of wiring width and wiring length) of the transistors constituting each buffer 40 is set to be larger than the W / L ratio of the transistors constituting each shift register. The scanning line having a large load capacity can be sufficiently driven. Each buffer 40 alternately outputs video signal enable signals OE1 and OE2 one by one in accordance with a control pulse output from the video signal shift register 38, and is an output from the black display signal shift register 39. According to the control pulse, an enable signal OEK for black display signal is output.

  In this scanning line driving circuit, four video signal shifts are performed with respect to one black display signal shift register 39 so that the four scanning lines for black display signals can be simultaneously written. A block 42 having a register 38 and four buffers 40 as a unit is electrically connected in a vertical stage. In addition, the same code | symbol is attached | subjected to the same thing in the figure.

  In the first embodiment, supply lines OE1 and OE2 that supply enable signals for video signals, and OEK that is a supply line that supplies enable signals for black display signals are provided, and two input terminals OES of each buffer 40 are provided. The video signal supply lines OE1 and OE2 are alternately connected one by one, and the black display signal supply line OEK is connected to the input terminal OEK of each buffer 40.

  FIG. 5 is a buffer circuit diagram of the scanning line driving circuit according to the first embodiment. Here, the case where the present scanning line driving circuit is configured by only a pMOS transistor in order to shorten the manufacturing process and realize cost reduction is shown.

  In the figure, each buffer circuit is connected to an input terminal SIN of the buffer, and has a control electrode to which a video signal control pulse is input, an input electrode to which a first power supply voltage VDD is supplied, and a first s provided with an output electrode. A transistor T1s, a control electrode connected to an input terminal KIN of the buffer, to which a control pulse for a black display signal is input, an input electrode to which a first power supply voltage VDD is supplied, and a first k transistor T1k having a second output, and a second An inverter circuit having a second transistor T2 having a control electrode, an input electrode, and an output electrode to which the power supply voltage VSS is supplied, and each output electrode of the first s transistor T1s, the first k transistor T1k, and the second transistor T2. Connected to the control electrode, the input electrode to which the first power supply voltage VDD is supplied, and the output terminal BOUT of the buffer A fifth transistor T5 having a force electrode; a control electrode to which a control pulse for video signal is input; an input electrode to which an enable signal for video signal is input connected to the input terminal OES of the buffer; and an output terminal BOUT of the buffer A sixth s-transistor T6s having an output electrode connected to the control electrode; a control electrode to which a control pulse for black display signal is input; an input electrode to which an enable signal for black display signal is input connected to the input terminal OEK of the buffer And an output circuit having a sixth k transistor T6k having an output electrode connected to the output terminal BOUT of the buffer.

  Further, each buffer circuit includes a seventh s transistor T7s connected between the input electrode connected to the buffer input terminal SIN to which a video signal control pulse is input and the control electrode of the sixth s transistor T6s. A black display signal control pulse connected to the input terminal KIN and a seventh k transistor T7k connected between the control electrode of the sixth k transistor T6k.

  The difference between the buffer circuit in the first embodiment and the buffer circuit in the conventional scanning line driving circuit shown in FIG. 11 is that OES, T6s, T7s are used for video signals, and OEK, T6k, T7k are used for black display signals. As described above, the OE signal and the T6 and T7 transistors are independently arranged. Accordingly, in each buffer, the first s transistor T1s and the second transistor T2 constituting the inverter circuit are turned on, the fifth transistor T5 constituting the output circuit is turned off, and the sixth s transistor T6s is turned on according to the control pulse for the video signal. By turning on, the video signal enable signal OE1 or OE2 that can turn on the switching element provided for each pixel electrode can be output to the scanning line. Further, according to the control pulse for the black display signal, the first k transistor and the second transistor constituting the inverter circuit inside the buffer are turned on, the fifth transistor constituting the output circuit inside the buffer is turned off, and the sixth k transistor is turned on. As a result, the enable signal OEK for the black display signal that can turn on the switching element provided for each pixel electrode can be output to the scanning line.

  FIG. 6 is a timing chart for explaining the operation of the buffer circuit in the scanning line driving circuit according to the first embodiment. In the figure, the period during which the output signal Sin of the video signal shift register, which is a control pulse for video signals, and the output signal Kin of the black display signal shift register, which is a control pulse for black display signals, is at a low level is 2. Over the horizontal scanning period, the period during which the OE signal, which is an enable signal that can turn on the switching element, is at a low level is one horizontal scanning period in the latter half of the two horizontal scanning periods. Accordingly, the output signal of each shift register is shifted by a half clock (here, one horizontal scanning period) and input to the buffer circuit. Hereinafter, the operation of the circuit when the output signal Sin (2) of the video signal shift register is supplied to the buffer connected to the scanning line G2 will be described with reference to the circuit diagram of FIG.

  When the output signal Sin (2) of the low-level video signal shift register is input to the input terminal SIN of the buffer circuit at time t1, both the first s transistor T1s and the second transistor T2 constituting the inverter circuit The node n1 is turned on and the potential n1 (2) of the node n1 is at a high level. At this time, the potential n3s (2) of the node n3s is in a floating state and at a low level. As a result, the sixth s transistor T6s is turned on, and the output signal BOUT (2) of the buffer circuit is at the high level because the OE2 signal from the sixth s transistor T6s is supplied.

  When the OE2 signal becomes low level at time t2, the potential n3s (2) of the node n3s becomes lower than the low level. This is because there is a parasitic capacitance between the gate and the source of the sixth s transistor T6s or between the gate and the drain. Therefore, when the node n3s is in a floating state, the potential fluctuation (bootstrap) between the drain and the source of the sixth s transistor T6s occurs. This is because the potential n3s (2) of the bootstrap node n3s varies accordingly. As a result, the output signal BOUT (2) of the buffer circuit becomes the low level because the OE2 signal is supplied via the sixth s transistor T6s.

  At time t3, when the output signal Sin (2) and the OE2 signal of the video signal shift register become high level, the potential n1 (2) of the node n1 is low level, and the potential n3s (2) of the node n3s is high level. Therefore, the fifth transistor T5 is turned on and the sixth s transistor T6s is turned off. As a result, the output signal BOUT (2) of the buffer circuit is at the high level because the first power supply voltage VDD is supplied through the fifth transistor T5.

  Next, the operation of the circuit when the output signals Kin (13) to (16) of the black display signal shift register are collectively supplied to the buffers connected to the four rows of scanning lines G13 to G16 will be described. Here, since the output signals Kin (13) to (16) of the black display signal shift register are all the same signal, the operation when the output signal Kin (13) is supplied to the buffer connected to the scanning line G5. This will be described with reference to the circuit diagram of FIG.

  When the output signal Kin (13) of the low-level black display signal shift register is input to the input terminal KIN of the buffer circuit at time t4, the first k transistor T1k and the second transistor T2 constituting the inverter circuit are Both are turned on, and the potential n1 (13) of the node n1 becomes high level. At this time, the node n3k is in a floating state and at a low level. As a result, the sixth k transistor T6k is turned on, and the output signal BOUT (13) of the buffer becomes the high level because the OEK signal is supplied through the sixth k transistor T6k.

  When the OEK signal becomes low level at time t5, the potential n3k (13) of the node n3k becomes lower than the low level. This is because there is a parasitic capacitance between the gate and the source of the sixth k transistor T6k or between the gate and the drain. Therefore, if the node n3k is in a floating state, the potential fluctuation (bootstrap) between the drain and the source of the sixth k transistor T6k. This is because the potential n3k (13) of the bootstrap node n3k varies accordingly. As a result, the output signal BOUT (13) of the buffer circuit is at the low level because the OEK signal is supplied through the sixth k transistor T6k.

  At time t6, when the output signal Kin (13) of the black display signal shift register and the OEK of the OE signal become high level, the potential n1 (13) of the node n1 becomes low level, and the potential n3k (13) of the node n3k. Becomes high level, the fifth transistor T5 is turned on and the sixth k transistor T6k is turned off. As a result, the output signal BOUT (13) of the buffer circuit becomes the high level because the first power supply voltage VDD is supplied through the fifth transistor T5.

  After time t6, the output signals Sin (2) and Kin (13) of the shift registers are both at a high level. At this time, the potential n1 (2) of the node n1 and the potential n1 (13) of the node n1. Since the potential n3s (2) of the node n3s and the potential n3k (13) of the node n3k are both kept at the high level, the fifth transistor T5 is turned on and the sixth k transistor T6k is turned off. The output signals BOUT (2) and BOUT (13) of the buffer circuit are at a high level because the first power supply voltage VDD is supplied through the T5 transistor regardless of the OE signal.

  In the buffer circuit in the conventional scanning line driving circuit shown in FIG. 11, when both SIN and KIN become low level, both the transistors T1 and T2 are turned on, so that the potential of the node n1 is completely high. I ca n’t go up. Therefore, as an example of a change in transistor characteristics caused by the contamination of impurities, which often occurs in manufacturing, when the characteristics of the third transistor T3 shift in the depletion direction, the operation of T3 becomes unstable, and the node n2 As a result, the potential of n3 rises. As a result, the bootstrap does not function well, and the low level cannot be completely written to the scanning line.

  The buffer circuit according to the first embodiment is the same as the buffer circuit of the conventional scanning line driving circuit shown in FIG. 11, except that the input to the seventh transistor T7 is directly given from the input terminal SIN or KIN of the buffer. The configuration is such that T3, the fourth s transistor T4s, and the fourth k transistor T4k, which have supplied the power supply voltage via, are removed. As a result, low level and high level writing to the node n3 is performed directly from the respective input terminals SIN and KIN. When the input signals to SIN and KIN become low level, the node n1 does not fully rise to high level, but at this time there is no high level leak path to the nodes n3k and n3s, so the nodes n3k and n3s Is more stable. As a result, even if the characteristics of the third transistor T3 as described above are shifted in the depletion direction, this buffer circuit has an advantage that it is not easily affected by fluctuations in transistor characteristics.

  Therefore, according to the first embodiment, since at least one horizontal scanning period is secured for the OE signal for both the video signal and the black display signal during the low level, the video signal for the black display signal Similarly, the buffer output signal BOUT can be set to a low level for one horizontal scanning period, and the switching element to which the buffer output signal BOUT is supplied can be turned on for a sufficient period. Further, an OEK that is a supply line for supplying an enable signal for a black display signal is provided independently for the supply lines OE1 and OE2 that supply an enable signal for a video signal, and two input terminals OES of each buffer 40 are provided. The video signal supply lines OE1 and OE2 are alternately connected one by one, and the black display signal supply line OEK is connected to the input terminal OEK of each buffer 40. By alternately using the enable signals OE1 and OE2 for the video signal one after another, the switching elements corresponding to the four scanning lines G1 to G4 for the video signal are sequentially turned on for a sufficient period, and subsequently for the black display signal. In response to the enable signal, the switching elements corresponding to the four scanning lines G13 to G16 for the black display signal are turned on for a sufficient period of time in four rows. Theft is possible. As a result, it is possible to realize a good image display without unevenness due to insufficient writing.

  In the first embodiment described above, a case has been described in which the switching elements corresponding to the four scanning lines G13 to G16 are turned on all at once for the black display signal. However, the present invention is not limited to this. Absent. Since a plurality of scanning lines for black display signals can be selected at arbitrary positions, for example, the four scanning lines G5 to G8 located immediately below the scanning lines G1 to G4 may be selected.

[Second Embodiment]
Hereinafter, a second embodiment of the present invention will be described. Note that the configuration of the liquid crystal display element and the alignment state of the liquid crystal molecules included in the liquid crystal display element are exactly the same as those of the first embodiment shown in FIGS. Here again, the scanning line driving circuit described below is integrally formed on the electrode substrate by the same manufacturing process as that of the pixel portion having the TFT as a switching element.

  FIG. 7 is a block diagram showing a configuration of a scanning line driving circuit according to the second embodiment. This scanning line driving circuit includes a plurality of video signal shift registers 38 having a function equivalent to each block constituting the conventional scanning line driving circuit shown in FIG. 10, a plurality of black display signal shift registers 39, and And a plurality of buffers 41. The output of each video signal shift register 38 is connected to the input of the video signal shift register of the next stage and the input terminal SIN of the buffer 41, and the output of each black display signal shift register 39 is the black display of the next stage. The input of the signal shift register and the input terminal KIN of the buffer 41 are connected to each other, and the output terminal BOUT of each buffer is connected to each scanning line. The output terminal BOUT of each buffer 41 is connected to each scanning line. Each buffer 41 outputs an enable signal OE1 or OE2 in accordance with a control pulse output from the video signal shift register 38 or a control pulse output from the black display signal shift register 39.

 Similarly, four video signal shifts are made to one black display signal shift register 39 so that signals for black display signals can be simultaneously written to four scanning lines. A block 42 having a register 38 and four buffers 41 as a unit is electrically connected in a vertical stage. In the figure, the same components are denoted by the same reference numerals, and the buffer 41 in the second embodiment has the same circuit configuration as the buffer in the conventional scanning line driving circuit shown in FIG. Yes.

 In the first embodiment, the video signal enable signals OE1 and OE2 and the black display signal enable signal OEK are provided. In the second embodiment, the video signal and black display signal are used. Without distinction, three enable signals OE1, OE2, and OE3 are provided, and in each block 42, two enable signals OE1, OE2, and OE3 are alternately supplied to the input terminal OE of each buffer 41 one by one. Connection is made (explanation regarding the OE signal in the second embodiment will be described later).

  FIG. 8 is a timing chart for explaining the operation of the buffer in the scanning line driving circuit according to the second embodiment. As in the first embodiment, the output signal of the video signal shift register, which is a control pulse for video signals, and the output signal of the black display signal shift register, which is a control pulse for black display signals, are at a low level. This period is over two horizontal scanning periods, and the period during which the OE signal, which is an enable signal capable of turning on the switching element, is at a low level is set to one horizontal scanning period. Accordingly, the output signal of each shift register is shifted by a half clock (here, one horizontal scanning period) and input to the buffer circuit.

  Here, the operation of the circuit when supplying the output signal Sin (2) of the video signal shift register to the buffer connected to the scanning line G2 will be described with reference to the circuit diagram of FIG. In this case, the OE2 signal is used from the three enable signals OE1, OE2, and OE3.

  When the output signal Sin (2) of the low level video signal shift register is input to the input terminal SIN of the buffer circuit at time t1, the first s transistor T1s and the second transistor T2 constituting the first inverter circuit are Both are turned on, and the potential n1 (2) of the node n1 becomes high level. At this time, the third transistor T3 and the fourth s transistor T4s constituting the second inverter circuit are turned off and on, respectively, so that the node n2 and the node n3 are in a floating state, and the potential n3 (2) of the node n3. The gate / drain voltage of T7, which is a pMOS transistor, is not kept constant and gradually becomes low level. As a result, since the sixth transistor T6 is turned on, the output signal BOUT (2) of the buffer is supplied with the OE2 signal from the sixth transistor T6 and becomes high level.

  When the OE2 signal becomes low level at time t2, the potential n3 (2) of the node n3 becomes lower than the low level. This is because there is a parasitic capacitance between the gate and the source of the sixth transistor T6 or between the gate and the drain. Therefore, if the node n3 is in a floating state, the potential fluctuation (bootstrap) between the drain and the source of the sixth transistor T6. This is because the potential n3 (2) of the bootstrap node n3 varies accordingly. As a result, the output signal BOUT (2) of the buffer is at the low level because the OE2 signal is supplied through the sixth transistor T6 that is kept on.

  At time t3, when the output signal Sin (2) of the video signal shift register and the OE2 of the OE signal become high level, the potential n1 (2) of the node n1 becomes low level, and the potential n3 (2) of the node n3 becomes low. Since it becomes high level, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off. As a result, the buffer output signal BOUT (2) is at the high level because the first power supply voltage VDD is supplied via the fifth transistor T5.

  Next, the operation of the circuit when supplying the output signals Kin (9) to (12) of the black display signal shift register to the buffers connected to the four rows of scanning lines G9 to G12 will be described. Here, since the output signals Kin (9) to (12) of the black display signal shift register are all the same signal, the operation when the output signal Kin (9) is supplied to the buffer connected to the scanning line G9. Will be described with reference to the circuit diagram of FIG.

  At time t4, when the output signal Kin (9) of the low-level black display signal shift register is input to the input terminal SIN of the buffer circuit, the first k transistor T1k and the second transistor T2 constituting the first inverter circuit. Are both turned on, and the potential n1 (9) of the node n1 becomes a high level. At this time, the third transistor T3 and the fourth k transistor T4k constituting the second inverter circuit are in an off state and an on state, respectively, so that the node n2 and the node n3 are in a floating state, and n3 (9) is at a low level. Become. As a result, since the sixth transistor T6 is turned on, the output signal BOUT (9) of the buffer is supplied with the OE2 signal via the sixth transistor T6 and becomes high level.

  When the OE2 signal becomes low level at time t5, the potential n3 (9) of the node n3 becomes lower than the low level. This is because there is a parasitic capacitance between the gate and the source of the sixth transistor T6 or between the gate and the drain. Therefore, if the node n3 is in a floating state, the potential fluctuation (bootstrap) between the drain and the source of the sixth transistor T6. This is because the potential n3 (9) of the bootstrap node n3 varies accordingly. As a result, the output signal BOUT (9) of the buffer becomes the low level because the OE2 signal is supplied through the sixth transistor T6 that is kept on.

  At time t6, when the output signal Kin (9) of the black display signal shift register and the OE2 of the OE signal become high level, n1 (9) becomes low level and n3 (9) becomes high level. The fifth transistor T5 is turned on and the sixth transistor T6 is turned off. As a result, the buffer output signal BOUT (2) is at the high level because the first power supply voltage VDD is supplied via the fifth transistor T5.

  After time t6, the output signals Sin (2) and Kin (9) of each shift register are both at the high level. At this time, n1 (2) and n1 (9) are at the low level, and n3 (2 ) And n3 (9) both maintain a high level state, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off. As a result, BOUT (2) and BOUT (9) are set to the high level because the power supply voltage is supplied through the respective fifth transistors T5 regardless of the OE signal.

  Next, in the scanning line driving circuit according to the second embodiment, three OE signals supplied to the buffer circuit will be described with reference to the matrix in FIG. 9 and the timing chart in FIG.

  FIG. 9 is a matrix diagram for explaining the OE signal connected to each scanning line in the scanning line driving circuit according to the second embodiment. In the figure, the vertical rows represent scanning lines, the horizontal columns represent time axes, and the numbers in the matrix represent the numbers of OE signals connected corresponding to the respective scanning lines. In the second embodiment, the matrix is continuous for the black display signal after sequentially scanning the scanning lines G1 to G4 for the video signal as in the first embodiment. Thus, the scanning lines G5 to G8 are not collectively scanned, but the scanning lines G9 to G12 (or G21 to G24) must be collectively scanned. This is because the OE signals are not arranged independently such as OE1 and OE2 for video and OEK for black display, but the three OE signals have no distinction for video signal and black display signal. Because they are shared and used.

  Therefore, according to the timing chart of FIG. 8, in order to perform the scanning for the black display signal collectively for four rows, it is necessary to simultaneously set any two OE signals to the low level among the three OE signals. is there. That is, after the OE1 and OE2 are alternately used for video from t1 to t5 and the scanning lines G1 to G4 are sequentially scanned, the scanning for the black display signal is started at t4. Since it is just after using OE2 to scan G4, the OE2 signal remains low. In this case, a combination that alternately uses OE2 and OE3 corresponding to the scanning lines G5 to G8 and a combination that alternately uses OE1 and OE2 corresponding to the scanning lines G13 to G16 cannot be used because they include OE2. (Black line in the matrix) Therefore, here, OE3 and OE1 corresponding to the scanning lines G9 to G12 are used alternately.

  Accordingly, also in the scanning line driving circuit according to the second embodiment, when any two of the three OE signals are used under the above-described conditions, the period during which the OE signal is at a low level is at least. One horizontal scanning period is secured, and BOUT for the video signal and the black display signal can be set to a low level for one horizontal scanning period, and for the video signal and the black display signal with respect to the scanning line. The switching elements can be turned on for a sufficient period of time. As a result, it is possible to realize a good image display without unevenness due to insufficient writing.

[Other forms]
In the drive circuit of the liquid crystal display device in the first and second embodiments described above, a buffer circuit of a scanning line drive circuit constituted only by a pMOS transistor will be described in order to shorten the manufacturing process and realize cost reduction. However, the present invention is not limited to this, and it may be a buffer circuit of a scanning line driving circuit composed of only nMOS transistors. Further, as long as the buffer circuit has a function of inserting an enable signal for a video signal and an enable signal for a black display signal independently, it may be a buffer circuit that constitutes a scanning line driving circuit using a CMOS transistor. . Even in such a case, the same effects as those of the above embodiments can be obtained.

  In the liquid crystal display element of the liquid crystal display device according to the first and second embodiments described above, the case where image display is performed using the OCB mode has been described, but the present invention is not limited to this. For example, an image may be displayed using a TN (Twisted Nematic) mode, an IPS (In-Plane Switching) mode, or an MVA (Multi-domain Vertical Alignment) mode. Even in such a case, the same effects as those of the above embodiments can be obtained.

  In the liquid crystal display elements of the liquid crystal display devices in the first and second embodiments described above, the black display signals are inserted in a lump in four rows, but the present invention is not limited to this. If the interval between the black display signal writing scanning period and the video signal writing scanning period is substantially equal over one frame as shown in FIG. 12, it may be two rows or eight rows at once. Even in such a case, the same effects as those of the above embodiments can be obtained.

It is sectional drawing which shows an example of a structure of the liquid crystal display element with which the liquid crystal display device which concerns on 1st Embodiment is provided. It is sectional drawing which shows typically the orientation state of the liquid crystal molecule which the liquid crystal display element with which the liquid crystal display device which concerns on 1st Embodiment is provided has. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to a first embodiment. 1 is a block diagram illustrating a configuration of a scanning line driving circuit in a liquid crystal display device according to a first embodiment. FIG. FIG. 3 is a buffer circuit diagram in the scanning line driving circuit according to the first embodiment. 6 is a timing chart for explaining the operation of the buffer circuit in the scanning line driving circuit according to the first embodiment. It is a block diagram which shows the structure of the scanning-line drive circuit which concerns on 2nd Embodiment. 10 is a timing chart for explaining the operation of the buffer in the scanning line driving circuit according to the second embodiment. It is a matrix figure explaining the OE signal connected corresponding to each scanning line in the scanning line drive circuit concerning a 2nd embodiment. It is a block diagram which shows the structure of the conventional scanning line drive circuit. It is a circuit diagram which shows the structure of the buffer in the conventional scanning line drive circuit. It is a timing chart which shows an example of operation | movement of the conventional liquid crystal display device. It is a timing chart explaining operation | movement of the buffer in the conventional scanning line drive circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Transparent electrode 3 ... Alignment film 4 ... Liquid crystal layer 5 ... Alignment film 6 ... Transparent electrode 7 ... Glass substrate 8 ... Phase difference film 9 ... Phase difference film 10 ... Polarizing plate 11 ... Polarizing plate 20 ... Liquid crystal molecule 31 ... Scanning line 32 ... Signal line 33 ... Switching element 34 ... Scanning line drive circuit 35 ... Signal line drive circuit 36 ... Pixel electrode 37 ... Display area 38 ... Video signal shift register 39 ... Black display signal shift register 40 ... book Buffer 41 included in the scanning line driving circuit ... Buffer 42 included in the conventional scanning line driving circuit ... Blocks 100 constituting each shift register and buffer ... Liquid crystal display element 101 ... Counter substrate 102 ... Array substrate

Claims (2)

Provided for each pixel electrode to control writing of a video signal or a black display signal supplied through the signal line with respect to the pixel electrode provided at each intersection of the plurality of scanning lines and the plurality of signal lines. A driving circuit of a display device that performs on / off control of a switching element by driving a scanning line,
A plurality of video signal shift registers for shifting the phase of the control pulse over two horizontal scanning periods for video signals by each shift register; and
A plurality of black display signal shift registers for shifting and outputting the phase of control pulses for two horizontal scanning periods for black display signals by each shift register;
A plurality of buffers provided at an output stage of each video signal shift register, to which control pulses for video signals and black display signals, phase-shifted by the video signal and black display signal shift registers, are respectively input ; Have
The two video signal enable signals are alternately input to each buffer one by one, and the black display signal enable signal is input. Each buffer controls the video signal after the phase shift or the black display signal. According to a pulse, a driving circuit for a display device, wherein an enable signal capable of turning on the switching element is output for one horizontal scanning period in the latter half of two horizontal scanning periods for the control pulse . Each buffer has a control electrode to which a video signal control pulse is input, an input electrode to which a first power supply voltage is supplied, a first s transistor having an output electrode, and a control to which a black display signal control pulse is input. An inverter circuit having an electrode, an input electrode to which a first power supply voltage is supplied, a first k transistor having an output electrode, a control electrode to which a second power supply voltage is supplied, an input electrode, and a second transistor having an output electrode;
A fifth transistor having a control electrode connected to each output electrode of the first s transistor, the first k transistor, and the second transistor, an input electrode supplied with the first power supply voltage, and an output electrode connected to the output terminal of the buffer A control electrode for receiving a video signal control pulse; an input electrode for receiving a video signal enable signal; a sixth s transistor having an output electrode connected to an output terminal of the buffer; a control for a black display signal An output circuit having a 6k transistor having a control electrode to which a pulse is input, an input electrode to which an enable signal for a black display signal is input, and an output electrode connected to the output terminal of the buffer;
The display circuit drive circuit according to claim 1, further comprising:

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