JP2001230431A - Photoelectric conversion device - Google Patents

Photoelectric conversion device

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Publication number
JP2001230431A
JP2001230431A JP2000034896A JP2000034896A JP2001230431A JP 2001230431 A JP2001230431 A JP 2001230431A JP 2000034896 A JP2000034896 A JP 2000034896A JP 2000034896 A JP2000034896 A JP 2000034896A JP 2001230431 A JP2001230431 A JP 2001230431A
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JP
Japan
Prior art keywords
layer
photoelectric conversion
conversion device
cell
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000034896A
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Japanese (ja)
Other versions
JP4064592B2 (en
Inventor
Tadashi Hisamatsu
正 久松
Kazuyo Nakamura
一世 中村
Yuji Komatsu
雄爾 小松
Masabumi Shimizu
正文 清水
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Sharp Corp
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Sharp Corp
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Priority to JP2000034896A priority Critical patent/JP4064592B2/en
Priority to US09/779,827 priority patent/US6504091B2/en
Priority to TW090103072A priority patent/TW480738B/en
Priority to DE10106491A priority patent/DE10106491B4/en
Publication of JP2001230431A publication Critical patent/JP2001230431A/en
Application granted granted Critical
Publication of JP4064592B2 publication Critical patent/JP4064592B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H01L31/1852Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising a growth substrate not being an AIIIBV compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264Inorganic materials
    • H01L31/0304Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L31/03046Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds including ternary or quaternary compounds, e.g. GaAlAs, InGaAs, InGaAsP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0687Multiple junction or tandem solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H01L31/1844Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/544Solar cells from Group III-V materials
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Sustainable Energy (AREA)
  • Sustainable Development (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric conversion device which optimizes the combination of the materials of a top cell and a bottom cell and realizes higher photoelectric conversion efficiency. SOLUTION: A photoelectric conversion device is provided with first and second p-n junctions. First p-n junction is formed in a semiconductor 4 shown by (Al1-yGay)1-xInxP and second p-n junction is formed in a semiconductor 2 which is substantially displayed by Ga1-z InzAs.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、光エネルギーを電
気エネルギーに変換するための光電変換装置に関し、特
に宇宙空間での使用において太陽光エネルギーを電気エ
ネルギーに変換する光電変換効率を向上させたIII−
V族系化合物半導体を用いた光電変換装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device for converting light energy into electric energy, and more particularly, to a photoelectric conversion device having improved photoelectric conversion efficiency for converting sunlight energy into electric energy when used in outer space. −
The present invention relates to a photoelectric conversion device using a group V compound semiconductor.

【0002】[0002]

【従来の技術】近年、人工衛星等の宇宙機の電源に使用
される宇宙用太陽電池セルとして、GaAsなどのII
I−V族系化合物半導体を主材料に用いた多接合型の太
陽電池セルを使用する例が増加している。これらの電池
セルは、従来から宇宙用太陽電池として広く用いられて
いるシリコン太陽電池セルに比べて高い光電変換効率が
期待できる。このため、シリコンセルでは対応できなか
った小型衛星や大電力衛星などへの用途に適している。
2. Description of the Related Art In recent years, as a solar cell for space used for a power source of a spacecraft such as an artificial satellite, II, such as GaAs, has been used.
Examples of using multi-junction solar cells using an IV group compound semiconductor as a main material are increasing. These battery cells can be expected to have higher photoelectric conversion efficiency than silicon solar battery cells that have been widely used as space solar cells. For this reason, it is suitable for use in small satellites, high power satellites, and the like, which cannot be handled by silicon cells.

【0003】多接合型太陽電池セルとして現在最も用い
られている電池セルは、例えば、米国特許5,223,043号
および5,405,453号に開示されている。これらの電池セ
ルの基本的な構造を図20に示す。この従来の多接合型
(2接合型)セルの主材料には、太陽光入射側の表面に
形成される第1の電池セル(以下、「トップセル」と記
す)104にGa1-xInxPが、また、トップセルの下
に形成される第2の電池セル(以下、「ボトムセル」と
記す)102にGaAsが用いられ、両者はトンネル接
合103で接続されている。基板101には、GaAs
またはGe単結晶ウエハが用いられている。トップセル
のGa1-xInxPの組成比は、ボトムセルのGaAsと
格子定数が一致することを目的に、x=0.49程度と
している。この場合、トップセルおよびボトムセル材料
の格子定数は、基板であるGeの格子定数にもほぼ等し
くなり、比較的容易にGe基板上にエピタキシャル成長
できるように意図されている。このとき、トップセルの
禁制帯幅(バンドギャップ)Egは約1.9eVであ
り、またボトムセルのバンドギャップEgは約1.4e
Vである。この従来の多接合型電池セルは、宇宙空間で
の太陽光スペクトルを模した光源を用いた特性試験によ
り、実験室レベルで約26%、工業製品レベルで約22
%の光電変換効率を達成している。さらに、近年では、
上記トップセルおよびボトムセルに加えて、Ge基板に
もpn接合を形成した3接合型電池セルも開発されてい
る。
[0003] Battery cells currently most used as multi-junction solar cells are disclosed in, for example, US Patent Nos. 5,223,043 and 5,405,453. FIG. 20 shows the basic structure of these battery cells. The main material of this conventional multi-junction (two-junction) cell includes Ga 1-x In as a first battery cell (hereinafter referred to as “top cell”) 104 formed on the surface on the sunlight incident side. x P is also a second battery cell which is formed below the top cell (hereinafter, referred to as "bottom cell") 102 GaAs is used, both of which are connected by a tunnel junction 103. The substrate 101 has GaAs
Alternatively, a Ge single crystal wafer is used. The composition ratio of Ga 1-x In x P in the top cell is set to about x = 0.49 for the purpose of matching the lattice constant with GaAs in the bottom cell. In this case, the lattice constant of the material of the top cell and the material of the bottom cell is substantially equal to the lattice constant of Ge as the substrate, and is intended to be able to epitaxially grow on the Ge substrate relatively easily. At this time, the forbidden band width (band gap) Eg of the top cell is about 1.9 eV, and the band gap Eg of the bottom cell is about 1.4 eV.
V. The characteristics of this conventional multi-junction battery cell are about 26% at the laboratory level and about 22% at the industrial product level by a characteristic test using a light source simulating the solar spectrum in space.
% Of photoelectric conversion efficiency. Furthermore, in recent years,
In addition to the top cell and the bottom cell, a three-junction battery cell in which a pn junction is also formed on a Ge substrate has been developed.

【0004】[0004]

【発明が解決しようとする課題】しかし、近年の宇宙開
発の飛躍的な進歩に対応してゆくためには、上記の光電
変換効率では不充分であり、さらに高い変換効率が望ま
れている。上記した従来の多接合型電池セルは、歴史的
にはGe基板上に形成したGaAs太陽電池セルの発展
型として開発された経緯があり、その結果として上記の
構造が定められてきた。しかし、太陽光エネルギーを最
大限利用するという観点からあらためて上記のGa1-x
InxPとGaAsとの組合せを考えた場合、この組合
せは、下記するように、最適な組合せということができ
ない。
However, in order to cope with the dramatic progress of space development in recent years, the above-mentioned photoelectric conversion efficiency is insufficient, and a higher conversion efficiency is desired. The above-described conventional multi-junction battery cell has been historically developed as an advanced type of a GaAs solar cell formed on a Ge substrate, and as a result, the above-described structure has been determined. However, from the viewpoint of maximizing the use of solar energy, the above Ga 1-x
When considering the combination of In x P and GaAs, this combination cannot be said to be the optimal combination as described below.

【0005】2つのpn接合からなる太陽電池セルの理
論的な光電変換効率が、例えば、IEEE Transaction on
Electron Devices,ED-34,p257に記載の論文にとり上
げられている。この論文には、トップセルおよびボトム
セルの材料のバンドギャップと入射光スペクトルとのマ
ッチングから、光電変換効率の期待値とトップセルおよ
びボトムセルのバンドギャップの範囲との関係が示され
ている。実際に電池セルを製作する場合には、通常、単
にバンドギャップだけが問題とされるのではなく、高品
質のエピタキシャル成長層を得るために、トップセルと
ボトムセルとの間、およびボトムセルと基板との間の格
子整合を図る。図21は、各種半導体材料の格子定数と
バンドギャップの関係を示した図である。上記の論文に
基づいて、図21の中に、宇宙空間における太陽光スペ
クトル(AMO)に対して30%以上の変換効率が得られる
トップセルのバンドギャップ範囲Uおよびボトムセルの
バンドギャップ範囲Lを示す。この図によれば、上記し
た従来の多接合型電池セルの材料の組合せ、すなわち、
Ga1-xInxPとGaAsとの組合せでは、光電変換効
率が30%に達しないことが分かる。
[0005] The theoretical photoelectric conversion efficiency of a solar cell comprising two pn junctions is, for example, IEEE Transaction on
Electron Devices, ED-34, p257. In this paper, the relationship between the expected value of the photoelectric conversion efficiency and the range of the band gap of the top cell and the bottom cell is shown by matching the band gap of the material of the top cell and the bottom cell with the incident light spectrum. When actually manufacturing a battery cell, usually, not only the band gap is a problem, but also the gap between the top cell and the bottom cell and between the bottom cell and the substrate in order to obtain a high-quality epitaxial growth layer. Lattice matching between them. FIG. 21 is a diagram showing a relationship between lattice constants and band gaps of various semiconductor materials. Based on the above-mentioned paper, FIG. 21 shows a band gap range U of the top cell and a band gap range L of the bottom cell which can obtain a conversion efficiency of 30% or more with respect to the solar spectrum (AMO) in outer space. . According to this figure, the combination of the materials of the conventional multi-junction battery cell described above, that is,
It can be seen that the photoelectric conversion efficiency does not reach 30% with the combination of Ga 1-x In x P and GaAs.

【0006】そこで、本発明は、トップセルおよびボト
ムセルの材料の組合せの最適化を図り、より高い光電変
換効率が実現可能な光電変換装置を提供することを目的
とする。
[0006] Therefore, an object of the present invention is to provide a photoelectric conversion device capable of realizing higher photoelectric conversion efficiency by optimizing a combination of materials of a top cell and a bottom cell.

【0007】[0007]

【課題を解決するための手段】本発明の請求項1の光電
変換装置は、第1および第2のpn接合を備える光電変
換装置であって、第1のpn接合は実質的に(Al1-y
Gay1-xInxPによって表示される半導体中に形成
され、第2のpn接合は実質的にGa1-zInzAsによ
って表示される半導体中に形成されている。
According to a first aspect of the present invention, there is provided a photoelectric conversion device including first and second pn junctions, wherein the first pn junction is substantially (Al 1) -y
Ga y ) 1-x In x P is formed in the semiconductor represented by P, and the second pn junction is substantially formed in the semiconductor represented by Ga 1-z In z As.

【0008】変換効率30%以上の高変換効率を実現す
るためには、少なくとも次の条件を満たすことが重要で
あると言われてきた。 (a)トップセルを構成する材料(以下、「トップセル
材料」と記す)およびボトムセルを構成する材料(以
下、「ボトムセル材料」と記す)のバンドギャップエネ
ルギの組合せの最適化を図る。 (b)トップセル材料とボトムセル材料との間の格子整
合を図る。 (c)ボトムセル材料と基板材料との間の格子整合を図
る。 (d)成長層材料と基板材料との熱膨張係数の整合を図
る。
It has been said that it is important to satisfy at least the following conditions in order to achieve a high conversion efficiency of 30% or more. (A) The combination of the band gap energies of the material forming the top cell (hereinafter referred to as “top cell material”) and the material forming the bottom cell (hereinafter referred to as “bottom cell material”) is optimized. (B) Lattice matching between the top cell material and the bottom cell material. (C) To achieve lattice matching between the bottom cell material and the substrate material. (D) Match the thermal expansion coefficients of the growth layer material and the substrate material.

【0009】しかしながら、これらの条件をすべて満た
し、かつ経済的に製造可能な半導体材料の組合せを見出
すことは至難の業である。本発明者らは、上記の各条件
について広範な調査を行った。その結果、(a)トップ
セル材料およびボトムセル材料のバンドギャップエネル
ギの組合せの最適化、および(b)トップセル材料とボ
トムセル材料との間の格子整合を図る、の2条件は、変
換効率30%以上の実現に不可欠であることをあらため
て確認した。
However, it is extremely difficult to find a combination of semiconductor materials that satisfies all of these conditions and can be manufactured economically. The present inventors have conducted extensive research on each of the above conditions. As a result, two conditions of (a) optimizing the combination of the band gap energies of the top cell material and the bottom cell material, and (b) achieving lattice matching between the top cell material and the bottom cell material are that the conversion efficiency is 30%. It was confirmed again that it is indispensable for realizing the above.

【0010】しかし、「ボトムセル材料と基板材料との
間の格子整合は重視する必要がなく、格子不整合の程度
が4%程度以内であれば、結晶成長技術を工夫すること
により結晶性の良い層を形成できる」(以後、(c)の
条件を緩和したこの条件を(c’)と記す)見通しを得
ることができた。
However, it is not necessary to emphasize the lattice matching between the bottom cell material and the substrate material. If the degree of lattice mismatch is within about 4%, good crystallinity can be obtained by devising a crystal growth technique. A layer can be formed ”(hereinafter, the condition obtained by relaxing the condition (c) is referred to as (c ′)).

【0011】また、「成長層材料と基板材料との間の熱
膨張係数の整合に関しても、過大な重視は不要であり、
成長層の熱膨張係数が基板の熱膨張係数に比べて同等以
下であれば、熱膨張係数の相違に起因する成長層へのク
ラック伝播等は抑制可能である」(以後、(d)の条件
を緩和したこの条件を(d’)と記す)見通しを得るこ
とができた。
[0011] Further, regarding the matching of the thermal expansion coefficient between the growth layer material and the substrate material, too much emphasis is not required.
If the thermal expansion coefficient of the growth layer is equal to or less than the thermal expansion coefficient of the substrate, crack propagation to the growth layer due to the difference in the thermal expansion coefficient can be suppressed. ”(Hereinafter, condition (d)) This condition, which was relaxed, is referred to as (d ')).

【0012】上記の調査において、条件(a)、
(b)、(c’)および(d’)を満足する材料とし
て、トップセルには(Al1-yGay1-xInxPによっ
て表示される半導体が、また、ボトムセルにはGa1-z
InzAsによって表示される半導体を用いることが有
効であるとの確信を得ることができた。これら(Al
1-yGay 1-xInxP、およびGa1-zInzAsを見出
すことができたのは、上記の条件(c’)および
(d’)の方針が大きく寄与している。上記請求項1の
構成の採用により、上記の条件(a)、(b)、
(c’)および(d’)の全てを満足することができ
る。この結果、変換効率30%以上の光電変換装置を実
現することが可能となる。なお、化学組成の表示におい
て、元素B,C,Pからなる物質B1- xxPでは、原子
Cは、化学式CPの結晶格子においてCが占めるサイト
のうちx(≦1.0)だけを占有し、残りの1−xのサ
イトを原子Bが占めている。また、物質(A1-yy
1-xxPでは、上記のB1-xxPにおいてB原子が占有
しているサイトのうち、さらにy(≦1.0)だけをを
B原子が占め、残りの1−yをA原子が占める。本発明
が対象とするIII−V族化合物半導体では、InP、
InAs、GaAs、GaP等は、通常、閃亜鉛鉱(Zi
nc blende)型結晶構造をしている。この閃亜鉛鉱型結晶
構造は、Ge、Si等のIV族半導体が有するダイヤモ
ンド型結晶構造と類似している。
In the above investigation, the conditions (a),
Materials satisfying (b), (c ′) and (d ′)
The top cell contains (Al1-yGay)1-xInxBy P
And the bottom cell is Ga1-z
InzUse of semiconductor indicated by As
I was convinced that it was effective. These (Al
1-yGay) 1-xInxP and Ga1-zInzFind As
The above conditions (c ′) and
The policy of (d ') greatly contributes. Claim 1
By adopting the configuration, the above conditions (a), (b),
(C ') and (d') can all be satisfied
You. As a result, a photoelectric conversion device having a conversion efficiency of 30% or more is realized.
It is possible to manifest. In addition, in the indication of chemical composition
And substance B consisting of elements B, C, and P1- xCxIn P, the atom
C is a site occupied by C in the crystal lattice of the chemical formula CP
Occupies only x (≦ 1.0) and the remaining 1−x
The atom B occupies the site. The substance (A1-yBy)
1-xCxIn P, B above1-xCxB atom occupied by P
Of the sites that do, only y (≦ 1.0)
B atom occupies, and A atom occupies the remaining 1-y. The present invention
In the group III-V compound semiconductors targeted by InP, InP,
InAs, GaAs, GaP, etc. are usually zincblende (Zi
nc blende) type crystal structure. This sphalerite type crystal
The structure is the same as that of the diamond
It is similar to a land-type crystal structure.

【0013】請求項2の光電変換装置では、請求項1の
変換装置において、半導体Ga1-zInzAsおよび(A
1-yGay1-xInxPの組成比zならびにxおよびy
は、それぞれ、0.11<z<0.29、x=-0.346z2+1.08z+
0.484、および131z3-66.0z2+9.17z+0.309<y<28.0z
3-24.4z2+5.82z+0.325の範囲内にある。
According to a second aspect of the present invention, there is provided the photoelectric conversion device according to the first aspect, wherein the semiconductors Ga 1 -z In z As and (A
l 1-y G ay ) 1-x In x P composition ratio z and x and y
Are respectively 0.11 <z <0.29, x = −0.346z 2 + 1.08z +
0.484, and 131z 3 -66.0z 2 + 9.17z + 0.309 <y <28.0z
3 -24.4z 2 + 5.82z + 0.325.

【0014】この構成により、具体的にトップセル材料
およびボトムセル材料のバンドギャップエネルギの最適
化を図ることができる。本発明者らは、(Al1-y
y1- xInxPおよびGa1-zInzAsの最適な組成
を得ることを目的に、これらの半導体について格子定数
およびバンドギャップエネルギの計算を行った。図1
は、光電変換効率34%以上が得られるトップセル材料
およびボトムセル材料のバンドギャップエネルギの範囲
Aを示す図である。図1において、トップセル材料のバ
ンドギャップエネルギを横軸に、ボトムセル材料のバン
ドギャップエネルギを縦軸にとっている。この図におい
て、変換効率34%以上が期待される領域Aは1つの閉
曲線で囲まれた領域として表示されている。図1には、
ボトムセル材料を固定してトップセル材料を混晶として
構成した場合のボトムセルバンドギャップとトップセル
バンドギャップとの関係が横軸に平行な線分として示さ
れている。トップセルは混晶なので、混晶が成立する範
囲内でバンドギャップにも範囲が生じ、線分として表示
される。各線分の右側にはボトムセルとして定めた半導
体材料とその上に形成される混晶の2成分の半導体材料
が示されている。そこに記載されるボトムセルには、G
eの格子定数との格子不整のパーセントが示されてい
る。例えばGa.29In.71P−Al.30In.70P on
Ga.77In.23As(1.62%>Ge)は、トップセ
ルがGa.29In.71P−Al.30In.70Pで構成される
混晶によって構成され、ボトムセルがGa.77In.23
sであることを示す。また、このボトムセルGa.77
.23Asの格子定数がGeに比べて1.62%大きい
ことを意味する。この変換効率34%以上の領域Aに対
応するトップセルおよびボトムセルをそれぞれ構成する
(Al1-yGay1-xInxPおよびGa1-zInzAsの
組成範囲は、次の範囲である。 z:ボトムセル材料のGa1-zInzAsの組成比zは、
0.11<z<0.29の範囲内とする。 x、y:トップセル材料の(Al1-yGay1-xInx
の組成比x、yは、zが上記の範囲内にあることを前提
として、それぞれ、x=-0.346z2+1.08z+0.484、およ
び131z3-66.0z2+9.17z+0.309<y<28.0z3-24.4z2+
5.82z+0.325の範囲内とする。xの範囲は、ボトムセル
材料のGa1-zInzAsの組成比zに応じて図2に示す
とおりである。また、yの範囲は、ボトムセル材料のG
1-zInzAsの組成比zに応じて図3に示すとおりと
なる。
With this configuration, it is possible to specifically optimize the band gap energy of the top cell material and the bottom cell material. The present inventors have proposed (Al 1-y G
in a y) 1- x In x P and Ga 1-z In z As the purpose of obtaining an optimum composition, was calculated lattice constant and band gap energy for these semiconductors. FIG.
FIG. 4 is a diagram showing a band gap energy range A of a top cell material and a bottom cell material that can obtain a photoelectric conversion efficiency of 34% or more. In FIG. 1, the horizontal axis represents the band gap energy of the top cell material, and the vertical axis represents the band gap energy of the bottom cell material. In this figure, a region A where a conversion efficiency of 34% or more is expected is displayed as a region surrounded by one closed curve. In FIG.
The relationship between the bottom cell band gap and the top cell band gap when the bottom cell material is fixed and the top cell material is formed as a mixed crystal is shown as a line segment parallel to the horizontal axis. Since the top cell is a mixed crystal, a band gap also occurs within the range where the mixed crystal is established, and is displayed as a line segment. On the right side of each line segment, a two-component semiconductor material of a semiconductor material defined as a bottom cell and a mixed crystal formed thereon is shown. The bottom cell described there is G
The percentage of lattice mismatch with the lattice constant of e is shown. For example Ga .29 In .71 P-Al .30 In .70 P on
Ga .77 In .23 As (1.62% > Ge) , the top cell is formed by a mixed crystal composed of Ga .29 In .71 P-Al .30 In .70 P, the bottom cell is Ga .77 In .23 A
s. The bottom cell Ga.77I
This means that the lattice constant of n.23 As is 1.62% larger than that of Ge. The composition range of (Al 1-y Ga y ) 1-x In x P and Ga 1-z In z As constituting the top cell and the bottom cell respectively corresponding to the region A having the conversion efficiency of 34% or more is as follows. It is. z: The composition ratio z of Ga 1-z In z As of the bottom cell material is
0.11 <z <0.29. x, y: (Al 1- y Ga y) of the top cell material 1-x In x P
The composition ratios x and y of x are -0.346z 2 + 1.08z + 0.484 and 131z 3 -66.0z 2 + 9.17z + 0.309 <y <, respectively, assuming that z is within the above range. 28.0z 3 -24.4z 2 +
It should be within the range of 5.82z + 0.325. The range of x is as shown in FIG. 2 according to the composition ratio z of Ga 1-z In z As of the bottom cell material. The range of y is G of the bottom cell material.
It becomes as shown in FIG. 3 according to the composition ratio z of a 1-z In z As.

【0015】トップセル材料およびボトムセル材料の組
成比x、yおよびzが上記の範囲内にあれば、変換効率
34%以上を達成することが期待できる。さらに、x、
yおよびzが上記の範囲内にあれば、基板をGeとした
とき、Geとの格子不整を2%以内に収めることができ
る。また、熱膨張係数については、Ge:5.5×10-6/
K、Ga1-zInzAs:5.8×10-6/K、および(Al
1-yGay1-xInxP:4.8×10-6/Kのように、3者は
互いに近接しているので、成長層にクラックが発生した
り、成長層にクラックが伝播したりする問題は生じな
い。
If the composition ratios x, y and z of the top cell material and the bottom cell material are within the above ranges, it is expected that a conversion efficiency of 34% or more will be achieved. Further, x,
When y and z are within the above ranges, when the substrate is Ge, lattice mismatch with Ge can be kept within 2%. Regarding the coefficient of thermal expansion, Ge: 5.5 × 10 −6 /
K, Ga 1 -z In z As: 5.8 × 10 −6 / K, and (Al
1-y Ga y) 1- x In x P: as 4.8 × 10 -6 / K, since the three parties are close to each other, cracks may occur in the grown layer, cracks propagate in the growth layer No problem.

【0016】本発明においては、太陽電池セルを構成す
る半導体材料について、基板と格子整合をとるという条
件を緩和することにより、新しい材料を見出した点に大
きな特徴を有する。すなわちトップセルについては、混
晶の概念を拠り所にして新しい半導体を創製した。すな
わち、結晶構造は同じものであるが、その結晶を構成す
る元素を変え、またそれら元素の組成比を変えて新しい
半導体を創製した。一般に、化合物半導体では、結晶構
造が同じで異なった材料を混合することにより、その混
合割合に応じて格子定数、バンドギャップエネルギ等に
中間的な物性を有する混晶が得られることはよく知られ
ている。このような混晶は、LED(Light Emitting D
iode)やレーザダイオード等のデバイスで実用化されて
いる。この場合、混合する異種材料の量は、単なる不純
物ドーピングの程度ではなく、結晶格子定数やバンドギ
ャップの変化が生じるほどの組成変化を伴う。したがっ
て、混晶の概念を拠り所にして創製した上記の半導体G
1-zInzAsおよび(Al1-yGay1-xInxPは、
新しい半導体ということができる。
The present invention has a great feature in that a new material has been found for the semiconductor material constituting the solar cell by relaxing the condition of lattice matching with the substrate. That is, for the top cell, a new semiconductor was created based on the concept of mixed crystals. That is, although the crystal structure is the same, a new semiconductor was created by changing the elements constituting the crystal and changing the composition ratio of these elements. In general, it is well known that, in a compound semiconductor, mixed materials having the same crystal structure and different properties can be obtained by mixing different materials having the same physical properties such as lattice constant and band gap energy according to the mixing ratio. ing. Such a mixed crystal is formed by an LED (Light Emitting D
It has been put to practical use in devices such as iode) and laser diodes. In this case, the amount of the different materials to be mixed is not merely a degree of impurity doping but is accompanied by a composition change such that a change in crystal lattice constant or band gap occurs. Therefore, the above-described semiconductor G created based on the concept of mixed crystals
a 1-z In z As and (Al 1-y Ga y) 1-x In x P is
It can be called a new semiconductor.

【0017】ここで、上記の本発明の基にある考え方が
従来の技術である、上記の米国特許発明等と相違する点
について詳しく説明する。 (1)米国特許5,223,043号との相違について 上記の米国特許発明には、2接合型電池セルの材料とし
て、次の3種類の組合せが開示されている。 (A)トップセルGaxIn1-xP(0<x<0.5)とボト
ムセルGaAsとの組合せ (B)トップセルGaxIn1-xP(x=0.51±0.05)と
ボトムセルGaAsとの組合せ (C)トップセルGaxIn1-xP(0<x<0.5)とボト
ムセルGax+0.5In0.5- xAs(0<x<0.5)との組合
せ 上記の組合せのうち、(A)および(B)は、前述の通
り、成長層をGe基板と格子整合させることを前提に組
合せがなされている。これに対して、本発明の成長層
は、上記(c’)に示すように、Ge基板と格子整合を
とる必要がない。さらに、本発明の光電変換装置のトッ
プセルを構成する材料は、上記米国特許発明の光電変換
装置のトップセルの材料と相違する。すなわち、本発明
の光電変換装置の典型的なトップセルの材料である、A
0.15Ga0.15In0.7Pは、15%のAlを含んでお
り、上記の米国特許発明の(A)、(B)および(C)
のいずれとも相違している。すなわち、本発明では、図
1に示すように、トップセルにAlを含んだ(Al1-y
Gay1-xInxPを用いることにより、トップセルと
ボトムセルとのバンドギャップを適当な値にして、高変
換効率を達成することが可能となる。この高変換効率の
達成のためには、トップセルの構成材料としてAlを一
定以上含む半導体材料を用いることが必須である。 (2)米国特許5405453号との相違について 上記の米国特許発明には、2接合型電池セルの材料とし
て、次の2種類の組合せが開示されている。 (D)トップセル(Ga,In)P(典型例として、G
0.49In0.51P)とボトムセルGaAsとの組合せ (E)トップセル(Al,In)P(典型例として、A
0.55In0.45P)とボトムセルGaAsとの組合せ 上記の(D)および(E)は、ともにGe基板と格子整
合することを前提にした組合せであり、本発明とは基本
的な電池セルの設計方針が異なる。また、トップセルお
よびボトムセルの両方とも構成材料が本発明の構成材料
と相違する。 (3)その他 その他に開示されたもの(Technical Digest of the In
ternational PVSEC-11, Sapporo, Hokkaido, Japan, 19
99, p593-594)には、次の組合せが開示されている。 (F)トップセルIn0.49Ga0.51PとボトムセルIn
0.01Ga0.99Pとの組合せ この(F)の組合せは、従来のボトムセルの材料である
GaAsと基板Geとの間のわずかな格子不整を是正す
るために、GaAsに1%のInを含ませてIn0.01
0.99Pとして、Ge基板に格子整合するようにしたも
のである。したがって、上記(F)の組合せも本発明の
電池セルと基本的な設計方針が相違する。さらに、トッ
プセルおよびボトムセルの両方とも、本発明とは電池セ
ルを構成する材料が相違する。
Here, the point that the concept based on the above-mentioned present invention differs from the above-mentioned US patent invention and the like, which is a conventional technique, will be described in detail. (1) Difference from U.S. Pat. No. 5,223,043 The above-mentioned U.S. Pat. No. 5,223,043 discloses the following three types of combinations as materials for a two-junction battery cell. (A) Combination of top cell Ga x In 1-x P (0 <x <0.5) and bottom cell GaAs (B) Combination of top cell Ga x In 1-x P (x = 0.51 ± 0.05) and bottom cell GaAs (C) top cell Ga x in 1-x P ( 0 <x <0.5) and bottom cell Ga x + 0.5 in 0.5- x as of a combination described above in combination with (0 <x <0.5), (a) and (B) is, as described above, combined on the premise that the growth layer is lattice-matched with the Ge substrate. On the other hand, the growth layer of the present invention does not need to be lattice-matched with the Ge substrate as shown in the above (c ′). Further, the material constituting the top cell of the photoelectric conversion device of the present invention is different from the material of the top cell of the photoelectric conversion device of the above-mentioned US patent invention. That is, A, which is a typical material of the top cell of the photoelectric conversion device of the present invention,
l 0.15 Ga 0.15 In 0.7 P contains 15% Al, and the above-mentioned US patent inventions (A), (B) and (C)
Is different from any of the above. That is, in the present invention, as shown in FIG. 1, the top cell contained Al (Al 1-y
By using Ga y ) 1-x In x P, the band gap between the top cell and the bottom cell can be set to an appropriate value, and high conversion efficiency can be achieved. In order to achieve this high conversion efficiency, it is essential to use a semiconductor material containing Al in a certain amount or more as a constituent material of the top cell. (2) Difference from U.S. Pat. No. 5,545,453 In the U.S. patent invention described above, the following two combinations are disclosed as materials for a two-junction battery cell. (D) Top cell (Ga, In) P (typically, G
a 0.49 In 0.51 P) and combination of bottom cell GaAs (E) Top cell (Al, In) P (typically A
l 0.55 In 0.45 P) Combination with Bottom Cell GaAs The above (D) and (E) are combinations based on the premise that they are lattice-matched with a Ge substrate. Different policies. The constituent materials of both the top cell and the bottom cell are different from the constituent materials of the present invention. (3) Others Others (Technical Digest of the In
ternational PVSEC-11, Sapporo, Hokkaido, Japan, 19
99, p593-594) disclose the following combinations. (F) Top cell In 0.49 Ga 0.51 P and bottom cell In
Combination with 0.01 Ga 0.99 P This combination of (F) is performed by adding 1% In to GaAs in order to correct a slight lattice mismatch between GaAs, which is a material of the conventional bottom cell, and the substrate Ge. In 0.01 G
a 0.99 P is lattice matched to the Ge substrate. Therefore, the combination of the above (F) also has a different basic design principle from the battery cell of the present invention. Further, both the top cell and the bottom cell are different from the present invention in the material constituting the battery cell.

【0018】本発明は上記の(A)〜(F)の従来技術
と比較して、基板と格子整合をとる必要がなく、トップ
セルに(Al1-yGay1-xInxPなる新しい材料を用
い、トップセルおよびボトムセルともに構成材料の組成
比の範囲を設定している。
The present invention does not require lattice matching with the substrate as compared with the prior arts (A) to (F) described above, and (Al 1 -y G ay ) 1 -x In x P Using a new material, the range of the composition ratio of the constituent materials is set for both the top cell and the bottom cell.

【0019】請求項3の光電変換装置では、請求項1ま
たは2の変換装置において、(Al 1-yGay1-xInx
PおよびGa1-zInzAsはトンネル接合部で接合され
ている。
According to the third aspect of the present invention, there is provided a photoelectric conversion device according to the first aspect.
Or 2 conversion devices, (Al 1-yGay)1-xInx
P and Ga1-zInzAs is joined at the tunnel junction
ing.

【0020】トンネル接合部は、トップセルとボトムセ
ルとを電気的に接続するために高濃度にドープされたp
++接合を含む。この構成により、トップセルにおいて
エネルギの高い状態の入射光を部分的に電気エネルギに
変換し、ボトムセルにおいてトップセルでエネルギ変換
された分だけ減少した光エネルギから部分的に電気エネ
ルギに変換するタンデム変換を行うことができる。しか
も、トンネル接合のために変換された後の電気エネルギ
の損失はほとんど生じない。このため、上記光電変換装
置により高い変換効率で電気エネルギを利用することが
可能となる。
The tunnel junction is highly doped p-type to electrically connect the top cell and the bottom cell.
+ n + junction included. According to this configuration, tandem conversion in which incident light having a high energy state is partially converted into electric energy in the top cell, and light energy reduced by an amount converted in the top cell in the bottom cell is partially converted into electric energy. It can be performed. Moreover, there is almost no loss of electric energy after being converted due to the tunnel junction. For this reason, it is possible to use electric energy with high conversion efficiency by the photoelectric conversion device.

【0021】請求項4の光電変換装置では、請求項1〜
3のいずれかの変換装置において、基板の上に形成され
た第1および第2のpn接合を含む成長層とその基板と
の間にバッファ層を有し、そのバッファ層の熱膨張係数
がバッファ層の直上の成長層の熱膨張係数と同等以上で
ある。
According to the photoelectric conversion device of the fourth aspect, the first to fourth aspects are as follows.
3. The conversion device according to claim 3, further comprising a buffer layer between the growth layer including the first and second pn junctions formed on the substrate and the substrate, wherein the coefficient of thermal expansion of the buffer layer is It is equal to or higher than the thermal expansion coefficient of the growth layer immediately above the layer.

【0022】この構成により、MOCVD(Metal Organ
ic Chemical Vapor Deposition)法による成長層形成時
の高温から室温にまで降下する際の温度変化に対して、
バッファ層にのみクラックを封じ込めておくことができ
る。このため、成長層でのクラック発生や成長層へのク
ラック伝播を抑制することができる。
With this configuration, MOCVD (Metal Organ
ic Chemical Vapor Deposition)
Cracks can be contained only in the buffer layer. For this reason, crack generation in the growth layer and crack propagation to the growth layer can be suppressed.

【0023】請求項5の光電変換装置では、請求項4の
変換装置において、基板の熱膨張係数が、そのバッファ
層の直上の成長層の熱膨張係数より小さい。
According to a fifth aspect of the present invention, the thermal expansion coefficient of the substrate is smaller than that of the growth layer immediately above the buffer layer.

【0024】この構成により、バッファ層によるいっそ
う強いクラック抑制効果を期待することができる。この
バッファ層材料の格子定数は、成長層および基板の格子
定数と近接していることが良い。さらに、請求項6のバ
ッファ層のように、請求項4または5の変換装置におい
て、その格子定数が、バッファ層の直上の成長層の格子
定数と整合していることが望ましい。上記バッファ層材
料は、具体的には、例えば、請求項7のバッファ層のよ
うに、実質的にGaAs1-wSbw(0.29<w<0.33)から
構成されていることが望ましい。上記の組成比wは、G
1-zInzAsの組成比z(0.11<z<0.29)の値に対応
して、格子整合をとるか、またはわずかの格子不整範囲
内になるように0.29<w<0.33の範囲内で適宜選択するこ
とができる。
According to this configuration, a stronger crack suppressing effect by the buffer layer can be expected. The lattice constant of the buffer layer material is preferably close to the lattice constants of the growth layer and the substrate. Furthermore, as in the buffer layer of the sixth aspect, in the conversion device of the fourth or fifth aspect, it is desirable that the lattice constant of the conversion apparatus matches the lattice constant of the growth layer immediately above the buffer layer. The buffer layer material, specifically, for example, as a buffer layer according to claim 7, it is preferably composed substantially of GaAs 1-w Sb w (0.29 <w <0.33). The above composition ratio w is G
According to the value of the composition ratio z of a 1-z In z As (0.11 <z <0.29), lattice matching is performed, or within a range of 0.29 <w <0.33 so as to be within a slight lattice mismatch range. Can be selected as appropriate.

【0025】請求項8の光電変換装置では、請求項1〜
7のいずれかの変換装置において、第1および第2のp
n接合を含む成長層が、GaAs単結晶基板、Ge単結
晶基板およびSi単結晶基板のうちのいずれか1つの上
に形成されている。
In the photoelectric conversion device according to the eighth aspect, the first to fourth aspects are as follows.
7 wherein the first and second p
A growth layer including an n-junction is formed on any one of a GaAs single crystal substrate, a Ge single crystal substrate, and a Si single crystal substrate.

【0026】この構成により、結晶性の良い成長層を形
成し、変換効率の高い光電変換装置を簡便に提供するこ
とが可能となる。また、基板にGe単結晶を用いること
により、基板との格子不整を2%以下に抑制することが
できる。このため、エピタキシャル成長した高品質の成
長層を得ることができるばかりか、将来的にはGeにも
pn接合を形成することにより、一層高い変換効率を得
ることが可能となる。
With this configuration, a growth layer having good crystallinity can be formed, and a photoelectric conversion device with high conversion efficiency can be easily provided. Further, by using a Ge single crystal for the substrate, lattice irregularity with the substrate can be suppressed to 2% or less. For this reason, not only can a high-quality epitaxially grown layer be obtained, but also a higher conversion efficiency can be obtained by forming a pn junction in Ge in the future.

【0027】請求項9の光電変換装置では、請求項1〜
7のいずれかの変換装置において、基板の上に形成され
た第1および第2のpn接合を含む成長層が、Si単結
晶基板上に設けられたSi1-xGex混晶層の上に形成さ
れている。
According to the photoelectric conversion device of the ninth aspect, the first to the fifth aspects are as follows.
7, the growth layer including the first and second pn junctions formed on the substrate may be formed on the Si 1-x Ge x mixed crystal layer provided on the Si single crystal substrate. Is formed.

【0028】上記構成により、格子不整の程度を抑制す
ることができ、結晶性に優れた成長層を形成することが
可能となる。また、安価な基板を用いて変換効率の高い
光電変換装置を得ることができる。
With the above configuration, the degree of lattice irregularity can be suppressed, and a grown layer having excellent crystallinity can be formed. Further, a photoelectric conversion device with high conversion efficiency can be obtained using an inexpensive substrate.

【0029】請求項10の光電変換装置では、請求項1
〜9のいずれかの変換装置において、第1および第2の
pn接合を含む成長層が形成されている基板の上層部
に、さらにpn接合が形成されている。
[0029] According to the photoelectric conversion device of the tenth aspect, in the first aspect,
In any one of the converters of (1) to (9), a pn junction is further formed in an upper layer portion of the substrate on which the growth layers including the first and second pn junctions are formed.

【0030】この構成により、光の有効利用をさらに図
ることができ、光電変換効率をさらに向上させることが
可能となる。
According to this configuration, the light can be more effectively used, and the photoelectric conversion efficiency can be further improved.

【0031】[0031]

【発明の実施の形態】次に、図面を用いて本発明の実施
の形態について説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

【0032】(実施の形態1)本発明の実施の形態1に
おける光電変換装置の基本構成の断面図を図4に示す。
同図に光の入射方向10を示すが、以後の説明におい
て、各層の光の入射方向側を各層の「表面」または「上
層」と、また対する側を「裏面」と記す。図4の基本構
造において、基板1の上にボトムセル2、トンネル接合
3およびトップセル4が、順次積層されている。この積
層には、有機金属を用いた気相成長法(MOCVD法:Metal
Organics Chemical Vapor Deposition)や分子線エピタ
キシー法(MBE法:Molecular Beam Epitaxy)が使用され
る。基板1にはGe単結晶を用いることが望ましいが、
低価格化を図る観点からは、Si、または、Si基板上
にGeまたはSi1-xGex のような混晶をエピタキシ
ャル成長させた「エピ基板」であってもよい。また、こ
れらの基板内にもpn接合を設けて3接合の構造とした
り、直上のボトムセル材料とヘテロ接合を形成すること
により電位障壁を形成する構造としてもよい。
(Embodiment 1) FIG. 4 is a sectional view showing the basic structure of a photoelectric conversion device according to Embodiment 1 of the present invention.
The light incident direction 10 is shown in the figure. In the following description, the light incident direction side of each layer is referred to as “front surface” or “upper layer” of each layer, and the opposite side is referred to as “back surface”. In the basic structure of FIG. 4, a bottom cell 2, a tunnel junction 3, and a top cell 4 are sequentially stacked on a substrate 1. For this lamination, a vapor phase growth method using organic metal (MOCVD method: Metal
Organics Chemical Vapor Deposition) and molecular beam epitaxy (MBE: Molecular Beam Epitaxy) are used. Although it is desirable to use a Ge single crystal for the substrate 1,
From the viewpoint of cost reduction, Si, or may be a mixed crystal such as Ge or Si 1-x Ge x epitaxially grown on Si substrate "epitaxial substrate." Also, a pn junction may be provided in these substrates to form a three-junction structure, or a structure in which a potential barrier is formed by forming a hetero junction with the bottom cell material immediately above.

【0033】ボトムセル2は少なくともGa1-zInz
s(0.11<z<0.29)なる組成の材料からなるp層とn層
の接合、すなわちpn接合を含む。このpn接合をはさ
んで、例えば、表面側に公知の窓層や、裏面側に公知の
裏面電界層等を設けることによりボトムセルのキャリア
収集効率を高める工夫を有してもよい。また、基板1か
らの基板構成元素や不純物の拡散を防止するためのバッ
ファ層を有してもよい。
The bottom cell 2 has at least Ga 1 -z In z A
It includes a junction between a p-layer and an n-layer made of a material having a composition of s (0.11 <z <0.29), that is, a pn junction. The pn junction may be sandwiched, for example, to provide a well-known window layer on the front side or a well-known back surface electric field layer on the back side to improve the carrier collection efficiency of the bottom cell. Further, a buffer layer for preventing the diffusion of the constituent elements and impurities from the substrate 1 may be provided.

【0034】トンネル接合3はトップセルとボトムセル
とを電気的に接続するための高濃度ドープのpn接合で
あり、少なくとも一対のp+層とn+層とを含む。このp
+層とn+層とをはさんで、この高濃度ドープ層からの不
純物拡散を抑制するためのもう一対の層を挿入する等の
公知の工夫を有してもよい。また、トンネル接合の材料
は、Ga1-zInzAsまたは(Al1-yGay1-xInx
Pであってもよいし、他の組成の半導体材料であっても
よい。
The tunnel junction 3 is a heavily doped pn junction for electrically connecting the top cell and the bottom cell, and includes at least a pair of p + and n + layers. This p
A well-known device such as insertion of another pair of layers for suppressing impurity diffusion from the highly doped layer may be provided between the + layer and the n + layer. The material of the tunnel junction is Ga 1 -z In z As or (Al 1 -yG ay ) 1 -x In x
It may be P or a semiconductor material having another composition.

【0035】トップセル4は、少なくとも(Al1-y
y1-xInxPなる組成の材料からなるp層とn層の
接合を含む。ただし、xおよびyは、ボトムセルにおけ
るInの組成比z(0.11<z<0.29)との間に、それぞ
れ、x=-0.346z2+1.08z+0.484、および131z3-66.0
2+9.17z+0.309<y<28.0z3-24.4z2+5.82z+0.325の
関係を有している。トップセル4においては、このpn
接合をはさんで、例えば、表面側に公知の窓層や、裏面
側に公知の裏面電界層等を設けることにより、トップセ
ルのキャリア収集効率を高める工夫を有してもよいこと
は言うまでもない。
The top cell 4 has at least (Al 1 -y G
a y ) A junction of a p-layer and an n-layer made of a material having a composition of 1-x In x P is included. Here, x and y are between x = −0.346z 2 + 1.08z + 0.484 and 131z 3 −66.0, respectively, between the In composition ratio z (0.11 <z <0.29) in the bottom cell.
z 2 + 9.17z + 0.309 <have a relationship of y <28.0z 3 -24.4z 2 + 5.82z + 0.325. In the top cell 4, this pn
It goes without saying that, for example, a known window layer on the front surface side or a known back surface electric field layer or the like on the back surface may be provided to improve the carrier collection efficiency of the top cell with the junction interposed therebetween. .

【0036】図5は、上記図4の基本構成を基にして作
製した光電変換装置の具体例を示す断面図である。この
図5では、ボトムセル2が、n型窓層21と、n型Ga
1-zInzAs層22と、p型Ga1-zInzAs層23
と、p+型裏面電界層24とから構成されている。ま
た、トップセル4は、n型窓層42と、n型(Al1-y
Gay1-xInxP層43とp型(Al1-yGay1-x
xP層44と、p+層型裏面電界層45とから構成され
ている。また、反射防止膜81,82およびn型キャッ
プ41aが表面側に形成され、さらに電気エネルギを取
り出す表面電極83および裏面電極84が設けられてい
る。
FIG. 5 is a sectional view showing a specific example of a photoelectric conversion device manufactured based on the basic configuration of FIG. In FIG. 5, the bottom cell 2 includes an n-type window layer 21 and an n-type Ga
1-z In z As layer 22 and p-type Ga 1-z In z As layer 23
And a p + type back surface electric field layer 24. The top cell 4 includes an n-type window layer 42 and an n-type (Al 1-y
Ga y ) 1-x In x P layer 43 and p-type (Al 1-y Ga y ) 1-x I
An n x P layer 44 and ap + -type back surface electric field layer 45 are provided. Further, antireflection films 81 and 82 and an n-type cap 41a are formed on the front surface side, and a front electrode 83 and a back electrode 84 for extracting electric energy are provided.

【0037】次に、上記図5の光電変換装置の製造方法
を図6〜図9により説明する。本製造方法においては、
成膜処理等はすべてMOCVD装置を使って連続して行
われる。III族材料としては、例えばトリメチルガリ
ウム、トリメチルアルミニウム、トリメチルインジウム
などの有機金属が水素をキャリアガスとして成長装置に
供給される。V族材料には、例えばアルシン(As
3)、ホスフィン(PH3)、スチビン(SbH3)など
のガスが使われる。p型不純物またはn型不純物のドー
パントとしては、例えばp型化にはジエチルジンク、ま
たn型化には、例えばモノシラン(SiH4)、ジシラン
(Si26)、セレン化水素(H2Se)などが使われ
る。これらの材料ガスを、例えば700℃に加熱された
基板上に供給することにより熱分解させ、所望の化合物
半導体材料の膜をエピタキシャル成長させることができ
る。これら成長層の組成は導入するガスの組成により、
また、膜厚はガスの導入時間によりコントロールするこ
とができる。図6は成長層が形成されるp型Ge基板1
の断面図である。まず、図7に示すように、上記p型G
e基板1の上にMOCVD法でボトムセル2を形成す
る。ボトムセル2は、上から順にn型窓層21、n型G
1-zInzAs層22、p型Ga1-zInzAs層23、
およびp+型裏面電界層24から構成されている。n型
窓層21およびp+型裏面電界層24の材料は、2つの
Ga1-zInzAs層22,23と格子整合する材料から
ボトムセルの変換効率を考慮して適宜選択することがで
きる。したがって、例えば、n型窓層21としてn型
(Al1-yGay1-xInxP層を、またp+型裏面電界
層24としてp+型Ga1-zInzAs層24を選択する
ことができる。次に、図8に示すように、ボトムセル2
上にトンネル接合3を形成する。トンネル接合3は、p
+型(Al1-yGay)1-xInxP31およびn+型(Al1-y
Gay)1- xInxP32から構成される。次に、図9に示
すように、トップセル4を形成する。このトップセル4
は、上から順にn型キャップ層41、n型窓層42、n
型(Al1-yGay)1-xInxP層43およびp型(Al1-y
Gay)1-xInx32層44およびp+型裏面電界層45
から構成される。n型窓層42の上にn型キャップ層4
1が設けられるのは、n電極のオーミック接触を高める
ためである。n型窓層42およびp+型裏面電界層45
の材料として(Al1-yGay)1-xInx31層と格子整合
する材料からトップセルの変換効率を考慮して適宜選択
することができる。したがって、例えば、n型窓層42
として、よりIn組成を低くしたn型(Al1-yGay)
1-xInxP層を、また、p+型裏面電界層45としてp+
型(Al1 -yGay)1-xInxP層を用いる。n型キャップ
層41としては、例えばn+型Ga1-zInzAs層を用
いることができる。その後、n型キャップ層41が選択
的にエッチングにより除去されn型キャップ41aが形
成される。また、トップセル41の表面に、例えば2層
の反射防止膜81,82が、さらに最表面と裏面とに金
属電極膜83,84が真空蒸着法やスパッタリング法に
より形成され、図5に示した光電変換装置が完成する。
Next, a method of manufacturing the photoelectric conversion device shown in FIG. 5 will be described with reference to FIGS. In the present manufacturing method,
All the film forming processes and the like are continuously performed using a MOCVD apparatus. As the group III material, for example, an organic metal such as trimethylgallium, trimethylaluminum, and trimethylindium is supplied to the growth apparatus using hydrogen as a carrier gas. Group V materials include, for example, arsine (As
Gases such as H 3 ), phosphine (PH 3 ), and stibine (SbH 3 ) are used. As the dopant of the p-type impurity or the n-type impurity, for example, diethyl zinc is used for p-type conversion, and monosilane (SiH 4 ), disilane is used for n-type impurity.
(Si 2 H 6 ), hydrogen selenide (H 2 Se) and the like are used. By supplying these material gases onto a substrate heated to, for example, 700 ° C., they are thermally decomposed, and a film of a desired compound semiconductor material can be epitaxially grown. The composition of these growth layers depends on the composition of the gas to be introduced.
Further, the film thickness can be controlled by the gas introduction time. FIG. 6 shows a p-type Ge substrate 1 on which a growth layer is formed.
FIG. First, as shown in FIG.
The bottom cell 2 is formed on the e-substrate 1 by MOCVD. The bottom cell 2 includes an n-type window layer 21 and an n-type G
a 1 -z In z As layer 22, p-type Ga 1 -z In z As layer 23,
And a p + type back surface electric field layer 24. The materials of the n-type window layer 21 and the p + -type backside electric field layer 24 can be appropriately selected from materials that lattice-match with the two Ga 1-z In z As layers 22 and 23 in consideration of the conversion efficiency of the bottom cell. . Thus, for example, n-type as the n-type window layer 21 (Al 1-y Ga y ) 1-x In x P layer and p + -type as a back surface field layer 24 p + -type Ga 1-z In z As layer 24 Can be selected. Next, as shown in FIG.
A tunnel junction 3 is formed thereon. Tunnel junction 3 has p
+ -Type (Al 1-y Ga y) 1-x In x P31 and the n + type (Al 1-y
Ga y ) 1- x In x P32. Next, as shown in FIG. 9, the top cell 4 is formed. This top cell 4
Are n-type cap layer 41, n-type window layer 42, n
Type (Al 1-y Ga y) 1-x In x P layer 43 and the p-type (Al 1-y
Ga y ) 1-x In x P 32 layer 44 and p + -type backside electric field layer 45
Consists of The n-type cap layer 4 is formed on the n-type window layer 42.
The reason why 1 is provided is to increase the ohmic contact of the n-electrode. n-type window layer 42 and p + -type backside electric field layer 45
Can be appropriately selected from materials that lattice-match with the (Al 1-y Ga y ) 1-x In x P 31 layer in consideration of the conversion efficiency of the top cell. Therefore, for example, the n-type window layer 42
N-type (Al 1-y Ga y ) with a lower In composition
The 1-x In x P layer, a p + -type back surface field layer 45 p +
Type (Al 1 -y Ga y) 1 -x In x P layer is used. As the n-type cap layer 41, for example, an n + -type Ga 1-z In z As layer can be used. Thereafter, the n-type cap layer 41 is selectively removed by etching to form an n-type cap 41a. In addition, for example, two layers of antireflection films 81 and 82 are formed on the surface of the top cell 41, and metal electrode films 83 and 84 are formed on the outermost surface and the back surface by a vacuum evaporation method or a sputtering method, as shown in FIG. The photoelectric conversion device is completed.

【0038】(実施の形態2)図10は、本発明による
III-V族系化合物半導体の多接合型太陽電池セルの
もう一つの基本構造を示す断面図である。本実施の形態
では、基板1とボトムセル2との間に、バッファ層5が
設けられている。このバッファ層5は、その格子定数が
成長層および基板の格子定数に近く、かつその熱膨張係
数がバッファ層直上に形成される成長層、すなわちボト
ムセルの最下層の材料の熱膨張係数と同等かまたはそれ
より大きい材料によって構成される。このバッファ層5
は、結晶成長後の降温時に、基板1と成長層との間の熱
膨張係数の相違に起因して発生するクラックをバッファ
層内にのみ発生させ、成長層でのクラック発生および成
長層へのクラック伝播を防止することを意図する。この
ため、ボトムセル2、トンネル接合3、トップセル4に
はクラックの影響が及ばず、クラックから保護されてい
る。このバッファ層に関して、さらに望ましくは、この
バッファ層の直上に形成する成長層の材料の熱膨張係数
は、基板の熱膨張係数より大きいものとするのがよい。
具体的なバッファ層の材料としては、例えば、ボトムセ
ルの材料Ga 1-zInzAsの組成範囲0.11<z<0.29に対
応して、wを適宜選択したGa1-wAswSb(0.29<w<
0.33)とする。ボトムセル2、トンネル接合3およびト
ップセル4については、実施の形態1と同様である。
(Embodiment 2) FIG.
III-V compound semiconductor multi-junction solar cell
It is sectional drawing which shows another basic structure. This embodiment
Then, the buffer layer 5 is provided between the substrate 1 and the bottom cell 2.
Is provided. This buffer layer 5 has a lattice constant
Close to the lattice constant of the growth layer and substrate and its thermal expansion
The growth layer formed directly above the buffer layer,
The coefficient of thermal expansion of the material in the bottom layer of the
Composed of larger materials. This buffer layer 5
Is the heat between the substrate 1 and the growth layer when the temperature is lowered after the crystal growth.
Buffers cracks caused by differences in expansion coefficients
Cracks in the growth layer
It is intended to prevent crack propagation to long layers. this
Therefore, the bottom cell 2, the tunnel junction 3, and the top cell 4
Is unaffected by cracks and is protected from cracks.
You. With regard to this buffer layer, more desirably,
Thermal expansion coefficient of material of growth layer formed directly on buffer layer
Is preferably larger than the coefficient of thermal expansion of the substrate.
As a specific material of the buffer layer, for example, a bottom cell
Material Ga 1-zInzAs composition range 0.11 <z <0.29
Accordingly, Ga is appropriately selected as w.1-wAswSb (0.29 <w <
0.33). Bottom cell 2, tunnel junction 3 and
The cell 4 is the same as in the first embodiment.

【0039】上記図10に示した光電変換装置の基本構
造に基づく具体的な光電変換装置を図11に示す。多層
構造となっているボトムセル2およびトップセル4の内
容、反射防止膜81,82、電極83,84について
は、実施の形態1に示したものと同じである。
FIG. 11 shows a specific photoelectric conversion device based on the basic structure of the photoelectric conversion device shown in FIG. The contents of the bottom cell 2 and the top cell 4 having a multilayer structure, the antireflection films 81 and 82, and the electrodes 83 and 84 are the same as those described in the first embodiment.

【0040】なお、本発明は、トップセル、トンネル接
合およびボトムセルを含む多層成長層を基板上に形成し
て、高変換効率の光電変換装置を提供するという基本的
な材料選択に関わる発明である。したがって、バッファ
層とボトムセルとの間に別にトンネル接合を設けたり、
トップセルとトンネル接合との間またはトンネル接合と
ボトムセルとの間に、歪み緩和層等の別の層を挿入して
も本発明の範囲に含まれることは言うまでもない。ま
た、受光面側がp型であっても、n型であっても、材料
選択が本発明に該当するかぎり、同様に、本発明の範囲
内に含まれる。
The present invention relates to a basic material selection in which a multilayer growth layer including a top cell, a tunnel junction and a bottom cell is formed on a substrate to provide a photoelectric conversion device with high conversion efficiency. . Therefore, a tunnel junction is separately provided between the buffer layer and the bottom cell,
It goes without saying that inserting another layer such as a strain relaxation layer between the top cell and the tunnel junction or between the tunnel junction and the bottom cell is also included in the scope of the present invention. Further, whether the light receiving surface side is p-type or n-type is also included in the scope of the present invention as long as the material selection falls under the present invention.

【0041】上記本実施の形態のようにバッファ層を設
けることにより、成膜処理後の降温時に光電変換装置各
部の熱膨張の相違により発生する可能性のあるクラック
をバッファ層の中に閉じ込めておくことができる。この
ため、製造歩留りが向上し、製造コスト低減が可能とな
る。また、格子定数を調整することにより、直上の成長
層と格子整合をとることにより、結晶性に優れた成長層
を形成でき、光電変換効率の向上をもたらすことができ
る。
By providing the buffer layer as in the present embodiment, cracks which may be generated due to differences in thermal expansion of the respective parts of the photoelectric conversion device when the temperature is lowered after the film forming process are confined in the buffer layer. I can put it. Therefore, the production yield is improved, and the production cost can be reduced. In addition, by adjusting the lattice constant, the growth layer with excellent crystallinity can be formed by lattice matching with the growth layer immediately above, and the photoelectric conversion efficiency can be improved.

【0042】(実施の形態3)図12は実施の形態3に
おける光電変換装置の基本構成を示す断面図である。こ
の光電変換装置は、基板表層にもpn接合を形成し、さ
らにバッファ層5とボトムセル2との間にトンネル接合
9をさらに設けた構成を有する。図12に示す基本構成
に基づいて実際に構成した光電変換装置の具体例の断面
図を図13に示す。図13に示した光電変換装置の製造
方法について、図14〜図19を用いて説明する。図1
4はp型Ge基板1を示す。この上にセル構造を形成す
るのであるが、その間のエピタキシャル成長中にAsを
拡散させることによりp型Ge基板12の上部に薄いn
型層11を形成することができる。次に、図15に示す
ように、基板1上にMOCVD法によりバッファ層5を
形成する。このバッファ層の材料としては、例えば、n
型GaAs1-wSbw(0.29<w<0.33)をあげることがで
きる。次に、図16に示すように、トンネル接合部9を
新たに形成する。このトンネル接合部9としては、例え
ば、p+型Ga1-zInzAs91とn+型Ga 1-zInz
s92とから形成することができる。次に、図17に示
すように、ボトムセル2を形成する。ボトムセル2は、
上から順にn型窓層21と、n型Ga 1-zInzAs層2
2と、p型Ga1-zInzAs層23と、p+型裏面電界
層24からなる。n型窓層21およびp+型裏面電界層
24の材料は、Ga1-zInzAs層22,23と格子整
合する材料の中からボトムセルの変換効率を考慮して適
宜選択することができる。例えば、n型窓層21はn型
(Al1-yGay)1-xInxPとし、またp+型裏面電界層
24はp+型Ga1-zInzAsとすることができる。次
に、図18に示すように、トンネル接合3を形成する。
このトンネル接合3はp+型(Al1-yGay)1-xInx
層31およびn+型(Al1-yGay)1-xInxP層32か
らなる。次に、図19に示すように、トップセル4を形
成する。このトップセル4は、上から順に、n型窓層4
2と、n型(Al1-yGay)1-xInxP層43と、p型
(Al1-yGay)1-xInxP層44と、p+型裏面電界層
45とから構成される。さらに、本実施の形態では、n
電極のオーミック接触を高めるためにn型キャップ層4
1が設けられている。n型窓層42およびp+型裏面電
界層45の材料は、(Al1-yGay)1-xInxP層43,
44と格子整合する材料の中からトップセルの変換効率
を考慮して適宜選択することができる。n型窓層42と
しては、例えば、In組成を低くしたn型(Al1-yGa
y)1-xInxP層を、また、p+型裏面電界層45として
は、例えば、p+型(Al1-yGay)1-xInxP層を用い
ることができる。n型キャップ層41には、例えばn型
Ga1-zInzAsを用いることができる。その後、キャ
ップ層41が選択的にエッチングされて除去され、トッ
プセルの裏面に、例えば2層の反射防止膜81,82が
形成される。最後に、最表面と裏面とに金属電極膜8
3,84が、真空蒸着法やスパッタリング法により形成
され、図13に示す光電変換装置が完成される。
(Embodiment 3) FIG. 12 shows Embodiment 3 of the present invention.
FIG. 2 is a cross-sectional view illustrating a basic configuration of the photoelectric conversion device in FIG. This
The photoelectric conversion device of (1) also forms a pn junction on the surface of the substrate,
And a tunnel junction between the buffer layer 5 and the bottom cell 2
9 is further provided. Basic configuration shown in FIG.
Section of a specific example of a photoelectric conversion device actually configured based on
The figure is shown in FIG. Manufacturing of the photoelectric conversion device shown in FIG.
The method will be described with reference to FIGS. FIG.
Reference numeral 4 denotes a p-type Ge substrate 1. Form a cell structure on this
However, during the epitaxial growth during that, As
By diffusion, a thin n is formed on the p-type Ge substrate 12.
The mold layer 11 can be formed. Next, as shown in FIG.
As described above, the buffer layer 5 is formed on the substrate 1 by the MOCVD method.
Form. As a material of this buffer layer, for example, n
Type GaAs1-wSbw(0.29 <w <0.33)
Wear. Next, as shown in FIG.
Form a new one. As the tunnel junction 9, for example,
If p+Type Ga1-zInzAs91 and n+Type Ga 1-zInzA
s92. Next, FIG.
Thus, the bottom cell 2 is formed. The bottom cell 2
An n-type window layer 21 and an n-type Ga 1-zInzAs layer 2
2 and p-type Ga1-zInzAs layer 23 and p+Mold back surface electric field
Consists of layer 24. n-type window layer 21 and p+Mold back surface electric field layer
24 is made of Ga1-zInzAs layers 22, 23 and lattice alignment
Considering the conversion efficiency of the bottom cell
You can choose any. For example, the n-type window layer 21 is an n-type window layer.
(Al1-yGay)1-xInxP and p+Mold back surface electric field layer
24 is p+Type Ga1-zInzAs. Next
Next, as shown in FIG. 18, a tunnel junction 3 is formed.
This tunnel junction 3 is p+Mold (Al1-yGay)1-xInxP
Layers 31 and n+Mold (Al1-yGay)1-xInxP layer 32
Become. Next, as shown in FIG.
To achieve. The top cell 4 includes, in order from the top, an n-type window layer 4.
2 and n-type (Al1-yGay)1-xInxP layer 43 and p-type
(Al1-yGay)1-xInxP layer 44 and p+Mold back surface electric field layer
45. Further, in the present embodiment, n
N-type cap layer 4 to enhance ohmic contact of the electrode
1 is provided. n-type window layer 42 and p+Mold back side
The material of the boundary layer 45 is (Al1-yGay)1-xInxP layer 43,
Conversion efficiency of top cell from materials that lattice-match with 44
Can be appropriately selected in consideration of the above. n-type window layer 42
For example, for example, an n-type (Al1-yGa
y)1-xInxP layer and p+Mold back surface electric field layer 45
Is, for example, p+Mold (Al1-yGay)1-xInxUsing the P layer
Can be The n-type cap layer 41 includes, for example, an n-type
Ga1-zInzAs can be used. Then,
The top layer 41 is selectively etched and removed, and the top layer 41 is removed.
On the back surface of the capsule, for example, two layers of antireflection films 81 and 82 are provided.
It is formed. Finally, a metal electrode film 8 is formed on the top and bottom surfaces.
3,84 formed by vacuum deposition or sputtering
Thus, the photoelectric conversion device shown in FIG. 13 is completed.

【0043】上記の光電変換装置は、トップセルとボト
ムセルとのバンドギャップの組合わせが最高の光電変換
効率をもたらすことを目的に、これまでにない新しい半
導体材料を用いて形成されている。このため、従来のI
II−V族半導体を用いた光電変換装置の変換効率を大
きく超える変換効率を達成することが可能となる。
The above-mentioned photoelectric conversion device is formed using an unprecedented new semiconductor material for the purpose of providing the highest photoelectric conversion efficiency by the combination of the band gap of the top cell and the bottom cell. For this reason, the conventional I
It is possible to achieve a conversion efficiency that greatly exceeds the conversion efficiency of a photoelectric conversion device using a II-V group semiconductor.

【0044】上記において、本発明の実施の形態につい
て説明を行なったが、上記に開示された本発明の実施の
形態は、あくまで例示であって、本発明の範囲はこれら
発明の実施の形態に限定されない。本発明の範囲は、特
許請求の範囲の記載によって示され、さらに特許請求の
範囲の記載と均等の意味および範囲内でのすべての変更
を含む。
Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. Not limited. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.

【0045】[0045]

【発明の効果】本発明によるIII-V族系化合物を含
む半導体多接合型太陽電池セルは、理論上、変換効率が
34%以上となる構成を有し、工業製品レベルでも変換
効率27%以上の特性が得られる。このため、小型衛星
や大電力衛生用の発電設備に用いられ、通信関連の関連
産業分野の発展に寄与することが期待される。
The semiconductor multi-junction solar cell containing the group III-V compound according to the present invention has a structure in which the conversion efficiency is 34% or more in theory, and the conversion efficiency is 27% or more even at the industrial product level. Is obtained. Therefore, it is used for power generation equipment for small satellites and large power sanitation, and is expected to contribute to the development of communication-related related industrial fields.

【0046】上記において、本発明の実施の形態につい
て説明を行ったが、上記に開示された本発明の実施の形
態は、あくまで例示であって、本発明の範囲はこれら発
明の実施の形態に限定されない。本発明の範囲は、特許
請求の範囲の記載によって示され、さらに特許請求の範
囲の記載と均等の意味および範囲内でのすべての変更を
含む。
Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. Not limited. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明におけるトップセル(Al1-yGay
1-xInxPおよびおよびボトムセルGa1-zInzAsの
それぞれの最適組成範囲を示す図である。
FIG. 1 is a top cell (Al 1-y Ga y ) of the present invention.
Is a diagram illustrating the respective optimum composition range of 1-x In x P and and the bottom cell Ga 1-z In z As.

【図2】 トップセル(Al1-yGay1-xInxPのお
ける組成比xの範囲を、ボトムセルGa1-zInzAsの
組成比zに応じて示す図である。
FIG. 2 is a diagram showing a range of a composition ratio x in a top cell (Al 1-y Ga y ) 1-x In x P according to a composition ratio z of a bottom cell Ga 1-z In z As.

【図3】 トップセル(Al1-yGay1-xInxPのお
ける組成比yの範囲を、ボトムセルGa1-zInzAsの
組成比zに応じて示す図である。
FIG. 3 is a diagram showing a range of a composition ratio y in a top cell (Al 1-y Ga y ) 1-x In x P according to a composition ratio z of a bottom cell Ga 1-z In z As.

【図4】 実施の形態1におけるIII-V族系化合物
半導体の多接合型太陽電池セルの基本構造を示す断面図
である。
FIG. 4 is a cross-sectional view showing a basic structure of a group III-V compound semiconductor multi-junction solar cell according to the first embodiment.

【図5】 実施の形態1における具体的なIII-V族
系化合物半導体の多接合型太陽電池セルの断面図であ
る。
FIG. 5 is a cross-sectional view of a specific III-V compound semiconductor multi-junction solar cell according to the first embodiment.

【図6】 図5の多接合型太陽電池セルの基板の断面図
である。
6 is a cross-sectional view of the substrate of the multi-junction solar cell of FIG.

【図7】 図6に示す基板上にボトムセルを形成した段
階の断面図である。
FIG. 7 is a cross-sectional view at the stage when a bottom cell is formed on the substrate shown in FIG.

【図8】 図7の状態に対してトンネル接合部を形成し
た段階の断面図である。
8 is a cross-sectional view of a state where a tunnel junction is formed in the state of FIG. 7;

【図9】 図8の状態に対してトップセルを形成した段
階の断面図である。
FIG. 9 is a cross-sectional view of a state where a top cell is formed in the state of FIG. 8;

【図10】 実施の形態2におけるIII-V族系化合
物半導体の多接合型太陽電池セルの基本構造を示す断面
図である。
FIG. 10 is a cross-sectional view showing a basic structure of a group III-V compound semiconductor multi-junction solar cell in Embodiment 2.

【図11】 実施の形態2における具体的なIII-V
族系化合物半導体の多接合型太陽電池セルの断面図であ
る。
FIG. 11 is a specific III-V according to the second embodiment.
1 is a cross-sectional view of a multi-junction type solar cell made of a group III compound semiconductor.

【図12】 実施の形態3におけるIII-V族系化合
物半導体の多接合型太陽電池セルの基本構造を示す断面
図である。
12 is a cross-sectional view showing a basic structure of a group III-V compound semiconductor multi-junction solar cell in Embodiment 3. FIG.

【図13】 実施の形態3における具体的なIII-V
族系化合物半導体の多接合型太陽電池セルの断面図であ
る。
FIG. 13 is a specific III-V according to the third embodiment.
1 is a cross-sectional view of a multi-junction type solar cell made of a group III compound semiconductor.

【図14】 図13の多接合型太陽電池セルのp型基板
の上部にn型不純物を導入してpn接合を基板に形成し
た段階の断面図である。
14 is a cross-sectional view of a stage in which an n-type impurity is introduced into an upper portion of a p-type substrate of the multi-junction solar cell of FIG.

【図15】 図14の状態に対してバッファ層を形成し
た段階の断面図である。
FIG. 15 is a cross-sectional view of a state where a buffer layer is formed in the state of FIG. 14;

【図16】 図15の状態に対してトンネル接合を形成
した段階の断面図である。
16 is a cross-sectional view of a state where a tunnel junction is formed in the state of FIG.

【図17】 図16の状態に対してボトムセルを形成し
た段階の断面図である。
FIG. 17 is a cross-sectional view of a state where a bottom cell is formed in the state of FIG. 16;

【図18】 図17の状態に対してトンネル接合を形成
した段階の断面図である。
FIG. 18 is a cross-sectional view of a state where a tunnel junction is formed in the state of FIG. 17;

【図19】 図18の状態に対してトップセルを形成し
た段階の断面図である。
FIG. 19 is a cross-sectional view of a state where a top cell is formed in the state of FIG. 18;

【図20】 従来のIII-V族系化合物半導体の多接
合型太陽電池セルの基本構造を示す断面図である。
FIG. 20 is a cross-sectional view showing the basic structure of a conventional III-V compound semiconductor multi-junction solar cell.

【図21】 各種半導体の格子定数とバンドギャップエ
ネルギとの関係を示す図である。
FIG. 21 is a diagram showing a relationship between lattice constants and band gap energies of various semiconductors.

【符号の説明】[Explanation of symbols]

1 基板、2 ボトムセル、3 トンネル接合、4 ト
ップセル、5 バッファ層、81,82 反射防止膜、
83,84 電極金属、9 トンネル接合、11 n型
Ge層、12 p型Ge基板、21 n型窓層(n型
(Al1-yGay 1-xInxP層)、22 n型Ga1-z
InzAs層、23 p型Ga1-zInzAs層、24
+型裏面電界層(p+型Ga1-zInzAs層)、31
+型(Al1- yGay1-xInxP層、32 n+型(A
1-yGay1-xInxP層、41 n型キャップ層(n+
型Ga1-zInzAs層)、41a n型キャップ、42
n型窓層(In組成が低いn型(Al1-yGay1-x
xP層)、43 n型(Al1 -yGay1-xInx
層、44 p型(Al1-yGay1-xInxP層、45
+型裏面電界層(p+型(Al1-yGay1-xInx
層)、91 p+型Ga1-zIn zAs層、92 n+型G
1-zInzAs層、A 34%以上の変換効率の領域、
U 変換効率30%達成のためのトップセルのバンドギ
ャップ範囲、L 変換効率30%達成のためのボトムセ
ルのバンドギャップ範囲。
 1 substrate, 2 bottom cell, 3 tunnel junction, 4 ton
Cell, 5 buffer layer, 81, 82 anti-reflection film,
83,84 electrode metal, 9 tunnel junction, 11 n-type
Ge layer, 12 p-type Ge substrate, 21 n-type window layer (n-type
(Al1-yGay) 1-xInxP layer), 22 n-type Ga1-z
InzAs layer, 23 p-type Ga1-zInzAs layer, 24
p+Mold back surface electric field layer (p+Type Ga1-zInzAs layer), 31
p+Type (Al1- yGay)1-xInxP layer, 32 n+Type (A
l1-yGay)1-xInxP layer, 41 n-type cap layer (n+
Type Ga1-zInzAs layer), 41a n-type cap, 42
 n-type window layer (n-type (Al1-yGay)1-xI
nxP layer), 43 n-type (Al1 -yGay)1-xInxP
Layer, 44 p-type (Al1-yGay)1-xInxP layer, 45
p+Mold back surface electric field layer (p+Type (Al1-yGay)1-xInxP
Layer), 91 p+Type Ga1-zIn zAs layer, 92 n+Type G
a1-zInzAs layer, A region with a conversion efficiency of 34% or more,
U Top cell bandgear to achieve 30% conversion efficiency
Gap, L-conversion efficiency 30%
Band gap range.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小松 雄爾 大阪府大阪市阿倍野区長池町22番22号 シ ャープ株式会社内 (72)発明者 清水 正文 大阪府大阪市阿倍野区長池町22番22号 シ ャープ株式会社内 Fターム(参考) 5F051 AA08 BA02 CA14 DA03 DA17 DA19 DA20 GA04 HA03  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuji Komatsu 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Masafumi Shimizu 22-22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka F-term (for reference) 5F051 AA08 BA02 CA14 DA03 DA17 DA19 DA20 GA04 HA03

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 第1および第2のpn接合を備える光電
変換装置であって、第1のpn接合は実質的に(Al
1-yGay1-xInxPによって表示される半導体中に形
成され、第2のpn接合は実質的にGa1-zInzAsに
よって表示される半導体中に形成されている、光電変換
装置。
1. A photoelectric conversion device comprising first and second pn junctions, wherein the first pn junction is substantially (Al
1-y Ga y ) formed in the semiconductor represented by 1-x In x P, and the second pn junction is formed substantially in the semiconductor represented by Ga 1-z In z As; Photoelectric conversion device.
【請求項2】 前記半導体Ga1-zInzAsおよび(A
1-yGay1-xInxPの組成比zならびにxおよびy
は、それぞれ、0.11<z<0.29、x=-0.346z2+1.08z+
0.484、および131z3-66.0z2+9.17z+0.309<y<28.0z
3-24.4z2+5.82z+0.325の範囲内にある、請求項1に記
載の光電変換装置。
2. The semiconductor according to claim 1, wherein said Ga 1-z In z As and (A
l 1-y G ay ) 1-x In x P composition ratio z and x and y
Are respectively 0.11 <z <0.29, x = −0.346z 2 + 1.08z +
0.484, and 131z 3 -66.0z 2 + 9.17z + 0.309 <y <28.0z
3 -24.4Z in the range of 2 + 5.82z + 0.325, the photoelectric conversion device according to claim 1.
【請求項3】 前記(Al1-yGay1-xInxPおよび
Ga1-zInzAsはトンネル接合部で接合されている、
請求項1または2に記載の光電変換装置。
Wherein the (Al 1-y Ga y) 1-x In x P and Ga 1-z In z As are joined in the tunnel junction,
The photoelectric conversion device according to claim 1.
【請求項4】 基板の上に形成された前記第1および第
2のpn接合を含む成長層とその基板との間に、バッフ
ァ層を有し、そのバッファ層の熱膨張係数が、バッファ
層の直上の成長層の熱膨張係数と同等以上である、請求
項1〜3のいずれかに記載の光電変換装置。
4. A buffer layer between a growth layer including the first and second pn junctions formed on a substrate and the substrate, wherein the buffer layer has a thermal expansion coefficient of The photoelectric conversion device according to any one of claims 1 to 3, which has a thermal expansion coefficient equal to or higher than a thermal expansion coefficient of a growth layer immediately above the growth layer.
【請求項5】 前記基板の熱膨張係数が、前記バッファ
層の直上の成長層の熱膨張係数より小さい、請求項4に
記載の光電変換装置。
5. The photoelectric conversion device according to claim 4, wherein a thermal expansion coefficient of the substrate is smaller than a thermal expansion coefficient of a growth layer immediately above the buffer layer.
【請求項6】 前記バッファ層の格子定数が、そのバッ
ファ層の直上の成長層の格子定数と整合している、請求
項4または5に記載の光電変換装置。
6. The photoelectric conversion device according to claim 4, wherein a lattice constant of the buffer layer matches a lattice constant of a growth layer immediately above the buffer layer.
【請求項7】 前記バッファ層が実質的にGaAs1-w
Sbw(0.29<w<0.33)によって表示される材
料から構成されている、請求項4〜6に記載の光電変換
装置。
7. The method according to claim 7, wherein the buffer layer is substantially GaAs 1-w
Sb w (0.29 <w <0.33 ) are made of a material that is displayed by the photoelectric conversion device according to claim 4-6.
【請求項8】 前記第1および第2のpn接合を含む成
長層が、GaAs単結晶基板、Ge単結晶基板およびS
i単結晶基板のうちのいずれか1つの上に形成されてい
る、請求項1〜7のいずれかに記載の光電変換装置。
8. A growth layer including the first and second pn junctions comprises a GaAs single crystal substrate, a Ge single crystal substrate,
The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device is formed on any one of the i-single-crystal substrates.
【請求項9】 基板の上に形成された前記第1および第
2のpn接合を含む成長層が、Si単結晶基板上に形成
されたSi1-xGex混晶層の上に形成されている、請求
項1〜7のいずれかに記載の光電変換装置。
9. A growth layer including the first and second pn junctions formed on a substrate is formed on a Si 1-x Ge x mixed crystal layer formed on a Si single crystal substrate. The photoelectric conversion device according to claim 1, wherein:
【請求項10】 前記第1および第2のpn接合を含む
成長層が形成されている基板の上層部に、さらにpn接
合が形成されている、請求項1〜9のいずれかに記載の
光電変換装置。
10. The photoelectric conversion device according to claim 1, wherein a pn junction is further formed in an upper layer portion of the substrate on which the growth layers including the first and second pn junctions are formed. Conversion device.
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