JP2001230385A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the connection between a bit line and a plug in self alignment in the direction of a word line. SOLUTION: A word line WL which functions as the gate electrode of the selective MISFET of a DRAM is made on the main surface of a semiconductor substrate, and then, plugs (a connecting plug BP and a plug made in a pattern SNCT) to be connected with the source and drain regions of the MISFET are made in the insulating film covering the word line WL. Next, an insulating film to cover the plug is made, and a bit line pattern and a tungsten film in reverse pattern are made on the insulating film. Using the tungsten film as a mask, a part of the insulating film is etched to form a wiring groove 18a. Next, a photo resist film 35, which has an opening on the connecting plug BP and is made rectilinearly in the direction of the word line WL, is made, and using the photoresist film 35 and the tungsten films as masks, the remainder of the insulating film is etched to expose the connecting plug BP.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to a random access memory (D-ROM) which requires a memory holding operation suitable for high integration.
The present invention relates to a technology effective when applied to a RAM (Dynamic Random Access Memory).

[0002]

2. Description of the Related Art In general, a trench type and a stacked type are known as a basic structure of a DRAM. The trench type is
An information storage capacitor (hereinafter simply referred to as a capacitor) is formed inside a trench dug in a substrate. In a stacked type, a capacitor is formed by a transfer transistor (hereinafter referred to as a selected MISFET (Metal Insulator Semic
onductor Field Effect Transistor). In the stacked type, a CUB (Capacitor Under) in which a capacitor is further arranged below the bit line
Bit-line) type and COB (Capacitor Ov)
er Bit-line) type. 64M mass production started
In products after the bit, a stacked type and a COB type, which have excellent cell area reduction properties, are becoming mainstream.

The structure of a DRAM having a COB type memory cell is as follows. That is, CO
A memory cell of a DRAM having a B-type memory cell is arranged at the intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix on the main surface of a semiconductor substrate, and one selection MISFET and one And one capacitor connected in series. The selection MISFET is formed in an active region surrounded by an element isolation region, and is mainly composed of a gate oxide film, a gate electrode integrally formed with a word line, and a pair of semiconductor regions forming a source and a drain. . The bit line is arranged above the select MISFET, and two select MISs adjacent in the extending direction thereof
It is electrically connected to one of the source and drain shared by the FET. The capacitor is also selected MI
It is arranged above the SFET and is electrically connected to the other of the source and the drain. In order to compensate for the decrease in the amount of stored charge (Cs) of the capacitor due to the miniaturization of the memory cell,
The surface area of the lower electrode (storage electrode) of the capacitor arranged above the bit line is increased by processing it into a cylindrical shape, and a capacitor insulating film and an upper electrode (plate electrode) are formed on the lower electrode.

In such a structure of the COB type memory cell, the bit line and the source and drain of the select MISFET are connected by a plug made of a polycrystalline silicon film or the like. In general, since a plug for connecting a capacitor is formed simultaneously with a plug for connecting a bit line, at least one insulating film is provided between the plug and the bit line to insulate the bit line from the plug for connecting a capacitor. It is formed.
Therefore, the connection between the bit line and the plug is made via the bit line connection hole. In addition, a reduction in bit line capacitance is required from the viewpoint of improving the operation speed of the DRAM and an improvement in the detection sensitivity of stored charges, and further, from the viewpoint of realizing miniaturization, miniaturization of members such as bit lines is required. . In order to satisfy these demands, for example, as described in WO 98/28795,
There is known a technique in which a bit line is formed by a damascene method and a sidewall spacer made of a silicon nitride film is formed on an inner wall. As a result, the bit lines are made thinner, the distance between the bit lines is lengthened, the capacitance between the bit lines is reduced, and the speed of the DRAM and the sensitivity of detecting the storage capacitance are improved.

[0005]

When a bit line is connected to a connection plug through a bit line connection hole, it is necessary to form a bit line pattern and a bit line connection hole pattern using different masks. Usually, after forming an isolation region on the main surface of a semiconductor substrate, a word line that also functions as a gate electrode of a MISFET is formed, and then a connection plug is formed. Furthermore, when forming a bit line by a damascene method, after forming a groove of a bit line pattern, a bit line connection hole is formed, and a bit line connected to a connection plug is formed by a so-called dual damascene (Dual Damascene) method. . Here, lithography at the time of forming the connection plug is performed based on a word line pattern that is a gate electrode of the MISFET. However, since the connection plug for connecting the bit line and the connection plug for connecting the capacitor are generally formed in common, the next formed bit line pattern and bit line connection hole pattern are formed by photolithography based on the connection plug. Is not performed, and photolithography is performed based on the word line pattern as in the case of the connection plug. That is, the bit line pattern and the bit line connection hole pattern are aligned with three layers,
Pattern misalignment is likely to occur. Particularly, the misalignment between the bit line and the bit line connection hole does not cause much problem in the vertical direction of the word line because the bit line is formed extending in the vertical direction of the word line. In any direction, the size of the misalignment directly affects the connection area, and there is a high possibility that a problem will occur.

In the prior art, a sidewall spacer made of a silicon nitride film is formed on the inner side wall of a groove formed in a bit line pattern as a method of thinning a bit line. Is large, which causes an increase in capacitance between bit lines. An increase in the bit line capacity is not preferable because it lowers the storage capacity detection sensitivity and lowers the operation speed of the DRAM.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique capable of realizing an electrical connection between a bit line and a connection plug in a word line direction by self-alignment in a miniaturized DRAM memory cell. It is an object of the present invention to provide a technology capable of easily and highly reliably realizing the electrical connection of the above.

It is another object of the present invention to simplify a process for forming a connection portion between a bit line and a connection plug.

Another object of the present invention is to reduce the capacitance between bit lines.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. (1) A method for manufacturing a semiconductor integrated circuit device according to the present invention
(A) forming an isolation region on a main surface of a semiconductor substrate and arranging a plurality of active regions having long sides in a first direction; (b)
A first surface extending on a main surface of the semiconductor substrate in a second direction perpendicular to the first direction and functioning as a gate electrode of the MISFET;
Forming a wiring, (c) in an active region between the first wirings,
Forming a pair of semiconductor regions functioning as a source / drain of the MISFET; (d) a first covering the first wiring;
Forming an insulating film and forming a connection hole in the first insulating film on at least one of the semiconductor regions; (e) forming a connection member in the connection hole for electrically connecting to the semiconductor region; (F) depositing a second insulating film, a third insulating film, and a fourth insulating film having an etching selectivity with respect to the third insulating film on the connecting member, and depositing a first coating on the fourth insulating film; (G) patterning the first resist film extending in the first direction on the first film, and etching the first film in the presence of the first resist film; (h) etching the first film Etching the fourth insulating film using the third insulating film as a stopper in the presence of the coating, further etching the third insulating film, and forming a first groove extending in the first direction;
(I) patterning a second resist film having an opening extending in the second direction, etching the second insulating film in the presence of the second resist film and the first coating, and connecting the etched first coating; Forming a second groove on the member, (j)
A first embedding first and second trenches in the entire surface of the semiconductor substrate;
Forming a conductive film, (k) removing the first conductive film other than in the first and second grooves, and electrically connecting the first conductive film to the connecting member on one of the semiconductor regions in the first and second grooves; Forming a second wiring. (2) The method for manufacturing a semiconductor integrated circuit device according to the present invention includes:
(A) forming an isolation region on a main surface of a semiconductor substrate and arranging a plurality of active regions having long sides in a first direction; (b)
A first surface extending on a main surface of the semiconductor substrate in a second direction perpendicular to the first direction and functioning as a gate electrode of the MISFET;
Forming a wiring, (c) in an active region between the first wirings,
Forming a pair of semiconductor regions functioning as a source / drain of the MISFET; (d) a first covering the first wiring;
Forming an insulating film and forming a connection hole in the first insulating film on at least one of the semiconductor regions; (e) forming a connection member in the connection hole for electrically connecting to the semiconductor region; (F) depositing a second insulating film, a third insulating film, and a fourth insulating film having an etching selectivity with respect to the third insulating film on the connecting member, and depositing a first coating on the fourth insulating film; (G) patterning the first resist film extending in the first direction on the first film, and etching the first film in the presence of the first resist film; (h) etching the first film Etching the fourth insulating film using the third insulating film as a stopper in the presence of the coating, further etching the third insulating film, and forming a first groove extending in the first direction;
(I) Forming a second conductive film covering the inner surface of the first groove on the entire surface of the semiconductor substrate, performing anisotropic etching on the second conductive film, and forming a side wall made of the second conductive film on the inner wall of the first groove. A step of forming a wall, (j) a step of etching the second insulating film in the presence of the first film and the side wall to form a second groove reaching the connecting member, and (k) a first step of forming the first groove on the entire surface of the semiconductor substrate. And forming a first conductive film filling the second groove,
(L) removing the first conductive film other than in the first and second grooves;
Forming a second wiring in the first and second trenches, the second wiring being electrically connected to a connection member on one of the semiconductor regions. (3) The method of manufacturing a semiconductor integrated circuit device of the present invention
(2) The method for manufacturing a semiconductor integrated circuit device according to (2),
Before the etching of the second insulating film, the second resist film having the opening extending in the second direction is patterned, and the second resist film is formed in the presence of the second resist film, the first coating and the sidewall.
The second groove is formed by etching the insulating film. (4) The method of manufacturing a semiconductor integrated circuit device of the present invention
(A) forming an isolation region on a main surface of a semiconductor substrate and arranging a plurality of active regions having long sides in a first direction; (b)
A first surface extending on a main surface of the semiconductor substrate in a second direction perpendicular to the first direction and functioning as a gate electrode of the MISFET;
Forming a wiring, (c) in an active region between the first wirings,
Forming a pair of semiconductor regions functioning as a source / drain of the MISFET; (d) a first covering the first wiring;
Forming an insulating film and forming a connection hole in the first insulating film on at least one of the semiconductor regions; (e) forming a connection member in the connection hole for electrically connecting to the semiconductor region; (F) depositing a second insulating film on the connecting member;
Depositing a first coating on the second insulating film, (g) patterning the first resist film extending in the first direction on the first coating, and applying the first coating in the presence of the first resist film. (H) forming a second conductive film covering the inner surface of the patterned first film on the entire surface of the semiconductor substrate, and performing anisotropic etching on the second conductive film to form a second conductive film on the side wall of the first film; 2
Forming a sidewall made of a conductive film, (i)
Etching the second insulating film in the presence of the first film and the side wall to form a second groove reaching the connection member; (j) first embedding the second groove in the entire surface of the semiconductor substrate;
Forming a conductive film, (k) removing the first conductive film other than in the second groove, and forming a second wiring electrically connected to the connection member on one of the semiconductor regions in the second groove Performing the following steps. (5) The method of manufacturing a semiconductor integrated circuit device of the present invention
(4) The method for manufacturing a semiconductor integrated circuit device according to (4),
In the step of etching the first coating, the second insulating film, which is the base of the first coating, is excessively etched so that the bottom of the sidewall is formed deeper than the bottom of the first coating. (6) The method of manufacturing a semiconductor integrated circuit device of the present invention
(1) The method for manufacturing a semiconductor integrated circuit device according to any one of (1) to (5), wherein the first film and the first conductive film are made of the same material, and in the step of removing the first conductive film. , First
The first film or the first film and the side wall are removed together with the conductive film. (7) The method for manufacturing a semiconductor integrated circuit device of the present invention
(1) The method for manufacturing a semiconductor integrated circuit device according to any one of (1) to (6), wherein the first insulating film and the upper surface of the connection member have an etching selectivity with respect to the second insulating film. The fifth insulating film is formed, and in the step of forming the second groove, the fifth insulating film is etched after the etching of the second insulating film using the fifth insulating film as a stopper. (8) A semiconductor integrated circuit device according to the present invention includes a semiconductor substrate having an active region having a long side in a first direction formed by an isolation region formed on a main surface thereof, and a gate insulating film interposed on the active region. A gate electrode formed and extending in a second direction perpendicular to the first direction, a pair of semiconductor regions formed in active regions on both sides of the gate electrode, and a pair of first insulating films formed on the first insulating film covering the gate electrode; A connection plug connected to one of the semiconductor regions, a second insulation film on the first insulation film,
A semiconductor integrated circuit device having a groove formed in a second insulating film and extending in a first direction, and a bit line connected to a connection plug and formed in the groove, wherein the groove is a second insulating film. The first groove includes an upper first groove and a second groove below the first groove. A sidewall made of a conductor is formed on an inner wall of the first groove, and the width of the second groove is equal to the thickness of the sidewall. The width is smaller than the width of one groove, and the second groove is formed continuously in the first direction. (9) In the semiconductor integrated circuit device of the present invention, a semiconductor substrate in which an active region having a long side in the first direction is formed by an isolation region formed in a main surface thereof, and a gate insulating film on the active region A gate electrode formed and extending in a second direction perpendicular to the first direction, a pair of semiconductor regions formed in active regions on both sides of the gate electrode, and a pair of first insulating films formed on the first insulating film covering the gate electrode; A connection plug connected to one of the semiconductor regions, a second insulation film on the first insulation film,
A semiconductor integrated circuit device having a groove formed in a second insulating film and extending in a first direction, and a bit line connected to a connection plug and formed in the groove, wherein the groove is a second insulating film. The first groove includes an upper first groove and a second groove below the first groove. A sidewall made of a conductor is formed on an inner wall of the first groove, and the width of the second groove is equal to the thickness of the sidewall. The width is smaller than the width of one groove, the second groove is formed discontinuously in the first direction, and the second groove is formed only in a region connected to the connection plug. (10) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to (9), wherein the second groove is formed longer in the first direction than the diameter of the connection plug. (11) The semiconductor integrated circuit device according to the present invention includes (8) to (1)
0) The semiconductor integrated circuit device according to any one of the above items, wherein the second insulating film has an upper insulating film and a lower insulating film, wherein the first insulating film has a first groove formed therein, and the lower insulating film has Has a second groove, and a first intermediate insulating film having an etching rate different from that of the upper insulating film is formed between the upper insulating film and the lower insulating film. (12) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to (11), wherein the lower insulating film and the first insulating film have a different etching rate between the lower insulating film and the first insulating film. An intermediate insulating film is formed. (13) The semiconductor integrated circuit device according to the present invention includes (8) to (1)
2) The semiconductor integrated circuit device according to any one of 2), wherein the semiconductor substrate has a first MI that forms a memory cell.
SFET and a second MISFE that directly constitutes a peripheral circuit
T is formed, and the width of the bit line in the region connected to the source / drain region of the second MISFET is the first MISFET.
It is formed wider than the width of the bit line in the region connected to the source / drain region of the FET. (14) A semiconductor integrated circuit device according to the present invention includes a semiconductor substrate having an active region having a long side in a first direction formed by an isolation region formed on a main surface thereof, and a gate insulating film interposed on the active region. A gate electrode formed and extending in a second direction perpendicular to the first direction, a pair of semiconductor regions formed in active regions on both sides of the gate electrode, and a pair of first insulating films formed on the first insulating film covering the gate electrode; A connection plug connected to one of the semiconductor regions, a second insulation film on the first insulation film, a groove formed in the second insulation film and extending in the first direction,
A semiconductor integrated circuit device having a bit line connected to the connection plug and formed in the groove, wherein the groove comprises a first groove above the second insulating film and a second groove below the first groove; The second groove is formed discontinuously in the first direction, and the second groove is formed in a region connected to the connection plug so as to be longer in the first direction than the diameter of the connection plug. (15) A method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps. (A) forming a first semiconductor region, a second semiconductor region, and an isolation region separating the first and second semiconductor regions on a main surface of a semiconductor substrate; and (b) forming the first and second semiconductor regions. Forming a first insulating film on a main surface of the semiconductor substrate including an upper portion of the second semiconductor region; (c) forming a second insulating film on the first insulating film; (d) ) The second
Having a first and a second opening above the insulating film
(E) etching the second insulating film exposed at the bottoms of the first and second openings with the second insulating film so that the second insulating film has an etching rate with respect to the first film; Forming the first and second grooves by etching with a method larger than (f), forming a second film covering a part of the first and second grooves with the first and second grooves. Forming a step inside the groove and above the first film;
(G) removing the first insulating film exposed at the bottoms of the first and second grooves by a method in which an etching rate for the first insulating film is higher than an etching rate for the first and second films; Etching to form a third opening at the bottom of the first groove and forming a fourth opening at the bottom of the second groove; (h) removing the second film (I) the inside of the first and second grooves and the third
Forming a first conductor film on the second insulating film including the first insulating film and the inside of the fourth opening; and (j) forming the first conductive film on the first insulating film.
Forming a first wiring which is electrically connected to the first semiconductor region through the third opening inside the first groove by removing a part of the conductive film of Forming a second wiring electrically connected to the second semiconductor region through the fourth opening inside the second groove. (16) The method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps. (A) A first structure in which a gate insulating film, a gate electrode, and a pair of semiconductor regions are formed on a main surface of a semiconductor substrate.
And the second MISFET and the first and second M
Forming an isolation region separating the ISFET, (b)
Forming a first insulating film on a main surface of the semiconductor substrate including upper portions of the first and second MISFETs;
(C) forming a second insulating film on the first insulating film; and (d) forming a first film having first and second openings on the second insulating film. (E) removing the second insulating film exposed at the bottom of the first and second openings by etching the second insulating film at a rate higher than the etching rate of the first film. (F) forming a second film covering a part of the first and second grooves with the inside of the first and second grooves. (G) forming the first insulating film exposed at the bottom of the first and second trenches with the first insulating film at an etching rate of the first insulating film equal to the first insulating film; And etching by a method larger than the etching rate for the second film, The third opening is formed in part, forming a fourth opening in the bottom of the second groove, (h)
Removing the second film; (i) forming a first film on the second insulating film including the inside of the first and second grooves and the inside of the third and fourth openings; (J) removing a part of the first conductive film to form the first MISFET through the third opening inside the first groove by removing a part of the first conductive film; Forming a first wiring electrically connected to one of the pair of semiconductor regions, and forming the second wiring through the fourth opening in the second groove.
Forming a second wiring electrically connected to one of the pair of semiconductor regions of the ISFET; (17) A semiconductor integrated circuit device according to the present invention is formed on a main surface of a semiconductor substrate and has first and second Ms each having a source, a drain region, a gate insulating film, and a gate electrode.
An ISFET, a source / drain region of the first MISFET formed on the main surface of the semiconductor substrate, and the second
An isolation region separating the source and drain regions of the MISFET, a first insulating film formed on the first and second MISFETs, and a second insulating film formed on the first insulating film. An insulating film, first and second conductors formed inside the second insulating film, and first and second wirings formed on the second insulating film; The first wiring is electrically connected to one of a source and a drain of the first MISFET through the first conductor, and the second wiring is connected to the second MISFET through the second conductor. The first MISFET is electrically connected to one of a source and a drain of the second MISFET.
And the second conductor is not formed.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) FIG. 1A is a plan view showing an example of an entire semiconductor chip on which a DRAM according to a first embodiment is formed. As shown, the main surface of the semiconductor chip 1A made of single-crystal silicon has an X direction (long side direction of the semiconductor chip 1A; first direction) and a Y direction (short side direction of the semiconductor chip 1A; second direction). A number of memory arrays MARY are arranged along the matrix. A sense amplifier SA is arranged between memory arrays MARY adjacent to each other along the X direction. Semiconductor chip 1
A control circuit such as a word driver WD and a data line selection circuit, an input / output circuit, a bonding pad, and the like are arranged in the center of the main surface of A.

FIG. 1B shows a DRAM according to the first embodiment.
3 is an equivalent circuit diagram of FIG. As shown, the memory array (MARY) of the DRAM includes a plurality of word lines WL (WL0, WL1, WLn...) And a plurality of bit lines BL arranged in a matrix and a plurality of bit lines BL arranged at intersections thereof. It is composed of memory cells. One memory cell that stores one bit of information is composed of one capacitor C and one selection MISFET Qs connected in series to the capacitor C. One of the source and the drain of the selection MISFET Qs is electrically connected to the capacitor C, and the other is electrically connected to the bit line BL. Word line WL
Is connected to a word driver WD and a bit line B
One end of L is connected to the sense amplifier SA.

FIG. 2 is an enlarged plan view of a part of the memory array MARY of FIG. In this plan view and the following plan views, the shapes of the patterns constituting the members are shown,
It does not represent the actual shape of the member. That is, the illustrated pattern is drawn in a rectangle or a square, but in an actual member, the apex angle is formed to be round or obtuse. In the memory array MARY, an active region L1 is arranged, and word lines WL are formed in the Y direction (second direction), and bit lines BL are formed in the X direction (first direction). In a region where the word line WL and the active region L1 overlap, the word line W
L functions as a gate electrode of the selection MISFET Qs. A connection plug BP connected to the bit line BL is formed in a region of the active region L1 interposed between regions functioning as a gate electrode of the word line WL, that is, in a central portion of the active region L1. The connection plug BP has a shape elongated in the Y direction so as to extend over the active region L1 and the bit line BL.
The central portion of the active region L1 and the bit line are connected to a connection plug BP
Connected via Both end regions of the active region L1 are connected to the capacitor C via the capacitor electrode connection holes SNCT.

In this embodiment, the bit line BL and the active region L1 are formed in a straight line extending in the X direction. Since it is formed in such a linear shape, interference of exposure light in photolithography when processing the bit line BL and the active region L1 can be reduced, and the processing margin can be improved.

FIG. 3 is a partial cross-sectional view of the DRAM of the present embodiment, wherein (a), (b), (c) and (d)
2 is a cross section taken along line CC, a cross section taken along line AA, and DD
2 shows a line cross section and a line BB cross section. In FIG. 3A, the memory cell area of the DRAM is shown on the left, and the peripheral circuit area is shown on the right. In the present embodiment, a manufacturing technique based on a design rule of 0.18 μm will be exemplified.

On the main surface of the semiconductor substrate 1, a p-type well 2 in a memory cell region, a p-type well 3 in a peripheral circuit region and n
A shaped well 4 is formed. The semiconductor substrate 1 is made of, for example, p-type single crystal silicon having a resistivity of 10 Ω · cm. A threshold voltage adjusting layer 5 is formed on the main surface of the p-type well 2, and an n-type deep well 6 is formed so as to surround the p-type well 2. Note that a threshold voltage adjustment layer may be formed in each of the other wells.

An isolation region 7 is formed on the main surface of each well. The isolation region 7 is made of a silicon oxide film and is formed by filling in a shallow groove 8 formed on the main surface of the semiconductor substrate 1. The shallow groove 8 has a depth of, for example, 0.3 μm, and a thermally oxidized silicon oxide film may be formed on the inner wall.

The main surface of the p-type well 2 has a DRAM selection M
ISFET Qs is formed. Also, p-type well 3
And n-channel MISF on the main surface of n-type well 4 respectively.
ETQn and p-channel MISFETQp are formed.

The selection MISFET Qs includes a gate electrode 11 formed on the main surface of the p-type well 2 via a gate insulating film 10 and a semiconductor region formed on the main surface of the p-type well 2 on both sides of the gate electrode 11. And 12.

The gate insulating film 10 is made of, for example, a silicon oxide film having a thickness of 7 to 8 nm and formed by thermal oxidation.

The gate electrode 11 can be a laminated film of, for example, a polycrystalline silicon film having a thickness of 50 nm and a tungsten silicide (WSi ₂ ) film having a thickness of 100 nm. For example, phosphorus (P) is 3 × 1 in the polycrystalline silicon film.
About 0 ²⁰ atoms / cm ³ can be introduced. The silicide film is not limited to the tungsten silicide film, but may be a cobalt silicide (CoSi) film, a titanium silicide (Ti
Another silicide film such as a Si) film may be used. Also,
The gate electrode 11 includes, for example, a polycrystalline silicon film having a thickness of 70 nm, a titanium nitride film having a thickness of 50 nm, and a thickness of 100 n.
m can be formed as a stacked film of tungsten films. A tungsten nitride film can be used instead of the titanium nitride film.

The semiconductor region 12 is doped with an n-type impurity, for example, arsenic (As) or phosphorus.

A cap insulating film 13 made of a silicon nitride film is formed on the upper layer of the gate electrode 11 of the selected MISFET Qs, and the upper layer is covered with a silicon nitride film 14. The thickness of the cap insulating film 13 is, for example, 200 nm, and the thickness of the silicon nitride film 14 is, for example, 30 nm. The silicon nitride film 14 is also formed on the side wall of the gate electrode 11, and is used for a self-alignment process when forming a connection hole described later. The gate electrode 11 of the selection MISFET Qs functions as a word line WL of the DRAM, and a part of the word line WL is formed on the upper surface of the isolation region 7.

On the other hand, n-channel MISFET Qn and p-channel MISFET Qp are formed on the main surfaces of p-type well 3 and n-type well 4, respectively.
A gate electrode 11 formed through the gate electrode 11
And semiconductor regions 15 formed on the main surface of each well on both sides of the semiconductor device. Gate insulating film 10 and gate electrode 1
1 is the same as above. The semiconductor region 15 includes a low concentration impurity region 15a and a high concentration impurity region 15b, and forms a so-called LDD (Lightly Doped Drain) structure. The impurity introduced into the semiconductor region 15 is MISFE
An n-type or p-type impurity is introduced depending on the conductivity type of T.

A cap insulating film 13 made of a silicon nitride film is formed on the gate electrode 11 of the n-channel MISFET Qn and the p-channel MISFET Qp.
3 is covered with the silicon nitride film 14. The cap insulating film 13 and the silicon nitride film 14 are the same as described above.

Selection MISFET Qs, n-channel MIS
An insulating film 16 is buried in a gap between the gate electrode 11 of the FET Qn and the p-channel MISFET Qp. The insulating film 16 is, for example, SOG (Spin On Glass)
A silicon oxide film (hereinafter referred to as a TEOS oxide film) formed by a plasma CVD method using TEOS (tetraethoxysilane) as a source gas is a CMP (Chemical Mechanical) film.
al Polishing) to form a laminated film of a TEOS oxide film planarized.

On the insulating film 16, insulating films 17a, 17
b, 17c are formed. The insulating films 17a and 17c are made of, for example, a TEOS oxide film, and the wiring grooves 18b are made of, for example, a silicon nitride film. The wiring groove 18b functions as an etching stopper when etching the wiring groove in the insulating film 17c, as described later.

The insulating films 17b and 17c have wiring grooves 18a.
Is formed, and a wiring groove 18b is formed in the insulating film 17a. The bit lines BL and the first layer wiring 20 are formed inside the wiring grooves 18a and 18b. Bit line BL
Is connected to the connection plug 2 described later through the wiring groove 18b.
1 electrically.

The bit line BL and the first layer wiring 20 are simultaneously formed by using the CMP method as described later.
Although the bit line BL and the first layer wiring 20 are made of, for example, a tungsten film, other metals, for example, a copper film may be used.

The bit line BL is connected to the semiconductor region 12 shared by the pair of select MISFETs Qs via the connection plug 21.
Connected to. As shown in the plan view of FIG. 2, the connection plug 21 is formed to be long in the Y direction so as to overlap the pattern of the active region L1 and the pattern of the bit line BL.

A connection plug 2 connected to a capacitor is provided on the other semiconductor region 12 of the selected MISFET Qs.
2 are formed. The connection plugs 21 and 22 are polycrystalline silicon films into which n-type impurities such as phosphorus are introduced at about 2 × 10 ²⁰ atoms / cm ³ .

The n-channel MISFET Qn and the p-channel MISFET Qp formed in the peripheral circuit region
The first layer wiring 20 (bit line BL) is directly connected to the high concentration impurity region 15b. Also, the high concentration impurity region 1
On the surface of 5b, a silicide film of cobalt, titanium, tantalum, tungsten or the like can be formed.

The bit line BL and the first layer wiring 20 are covered with an interlayer insulating film 23. The interlayer insulating film 23 can be, for example, a TEOS oxide film.

In the memory cell region above the interlayer insulating film 23, an insulating film 24 made of a silicon nitride film is formed, and a capacitor C for storing information is formed. The insulating film 24 is formed on the lower electrode 2 of the capacitor C as described later.
7 is a thin film that functions as an etching stopper when forming 7.

The capacitor C has a lower electrode 27 connected to the connection plug 22 via the connection plug 25 and a capacitor insulating film 2 made of, for example, a silicon nitride film and a tantalum oxide.
8 and a plate electrode 29 made of, for example, titanium nitride. The connection plug 25 is formed in the capacitor electrode connection hole 26.

On the upper layer of the capacitor C, for example, TEOS
An insulating film 30 made of an oxide film is formed. Note that an insulating film may be formed on the interlayer insulating film 23 in the peripheral circuit region in the same layer as the capacitor C. With this insulating film,
It is possible to prevent the occurrence of a step between the memory cell region and the peripheral circuit region due to the elevation of the capacitor C, to allow a margin in the depth of focus of photolithography, to stabilize the process, and to achieve fine processing. Can respond.

A second layer wiring 31 is formed above the insulating film 30, and the second layer wiring 31 is connected to the upper electrode 29 or the first layer wiring 20 by a plug 32. The second layer wiring 31 can be, for example, a laminated film of a titanium nitride film, an aluminum film, and a titanium nitride film.
For example, a stacked film of a titanium film, a titanium nitride film, and a tungsten film can be used.

It should be noted that a third layer wiring or more wiring layers may be further provided on the second layer wiring 31 with an interlayer insulating film interposed therebetween, but the description is omitted.

Next, a method of manufacturing the DRAM of the first embodiment will be described with reference to the drawings. 4 to 19 are sectional views or plan views showing an example of the method of manufacturing the DRAM of the first embodiment in the order of steps. Unless otherwise indicated, the cross-sectional view shows a cross section taken along line CC of FIG. 2 and a cross section of a peripheral circuit portion.

First, as shown in FIG.
A p-type semiconductor substrate 1 having a resistivity of about 0 Ω · cm is prepared, and the main surface of the semiconductor substrate 1 has a depth of, for example, 0.3 μm.
The shallow groove 8 of m is formed. Thereafter, the semiconductor substrate 1 may be subjected to thermal oxidation to form a silicon oxide film. Further, a silicon oxide film is deposited and polished by the CMP method to leave the silicon oxide film only in the shallow groove 8, thereby forming the isolation region 7.

The pattern of the active region L1 surrounded by the isolation region 7 at this time is a linear planar pattern as shown in FIG. For this reason, in the processing of the shallow groove 8 by photolithography, it is possible to perform processing with high accuracy even near the processing limit of photolithography by eliminating factors that reduce processing accuracy such as interference of exposure light as much as possible.

Next, phosphorus ions are implanted using the photoresist as a mask to form a deep well 6, and then phosphorus ions are implanted using the photoresist as a mask to form an n-type well 4. Further, boron ions are implanted using the photoresist as a mask,
Form 3 Further, boron diboride (BF2) ions may be implanted into the entire surface of the semiconductor substrate 1.

Next, as shown in FIG. 4B, a gate insulating film 10 is formed by thermal oxidation in the active region where the p-type wells 2 and 3 and the n-type well 4 have been formed.
Is implanted into the memory cell region at an acceleration energy of 20 keV and a dose of about 3 × 10 ¹² / cm ² to form the threshold voltage adjusting layer 5 of the selected MISFET Qs. MIS selected by threshold voltage adjustment layer 5
The threshold voltage of the FET Qs can be adjusted to about 0.7V.

Next, a polycrystalline silicon film in which, for example, phosphorus as an impurity is introduced at a concentration of 3 × 10 ²⁰ / cm ³ is formed on the entire surface of the semiconductor substrate 1 to a thickness of 50 nm. A tungsten silicide film is deposited to a thickness. Further, a silicon nitride film is deposited to a thickness of, for example, 200 nm. Polycrystalline silicon film and silicon nitride film
For example, by CVD (Chemical Vapor Deposition) method,
The tungsten silicide film can be formed by a sputtering method. After that, the silicon nitride film, the tungsten silicide film, and the polycrystalline silicon film are patterned by using a photolithography technique and an etching technique to form a gate electrode 11 (word line WL) and a cap insulating film 13. At this time, the word line WL (cap insulating film 13)
The same is true for 4) is shown in FIG. The word lines WL are linearly patterned, which indicates that photolithography can be easily performed even at the processing limit.

Next, using the cap insulating film 13, the gate electrode 11, and the photoresist as a mask, the n-channel MISFET Q
Impurities such as arsenic (As) or phosphorus are ion-implanted into the region where n is to be formed to form the semiconductor region 12 and the low-concentration impurity region 15a of the n-channel MISFET Qn. Then, the p-channel MISFET Q in the peripheral circuit region
Impurities such as boron (B) are ion-implanted into a region where p is to be formed, thereby forming a low-concentration impurity region 15a of the p-channel MISFET Qp.

Next, as shown in FIG. 5A, a silicon nitride film 14 is deposited on the entire surface of the semiconductor substrate 1 to a thickness of, for example, 30 nm. The silicon nitride film 14 is anisotropically etched using the photoresist film formed only in the memory cell formation region as a mask so that the silicon nitride film 14 is left only on the semiconductor substrate 1 in the memory cell region and the peripheral circuit A sidewall spacer may be formed on the side wall of the gate electrode 11 in the region.

Next, a photoresist film is formed in the memory cell formation region and the region where the n-channel MISFET Qn is formed in the peripheral circuit region, and impurities such as boron are ion-implanted using the photoresist film and the silicon nitride film 14 as a mask. Implantation is performed to form a high-concentration impurity region 15b of the p-channel MISFET Qp. Further, a photoresist film is formed in a memory cell forming region and a region of the peripheral circuit region where the p-channel MISFET Qp is formed. Using the nitride film 14 as a mask, an impurity such as phosphorus is ion-implanted to form a high-concentration impurity region 15b of the n-channel MISFET Qn.

Next, a silicon oxide film having a thickness of, for example, 400 nm is formed by a CVD method, and the silicon oxide film is polished and flattened by a CMP (Chemical Mechanical Polishing) method to form an insulating film 16.

Thereafter, as shown in FIG. 5B, connection holes corresponding to the pattern BP of the connection plug 21 and the pattern SNCT of the connection plug 22 are opened, and after plug-in implantation is performed, polycrystalline doped with impurities is formed. A silicon film is deposited, and the polycrystalline silicon film is polished by a CMP method to form connection plugs 21 and 22 (FIG. 6). FIG.
2, (a), (b), (c) and (d) show a cross section taken along line CC, AA line, DD line and BB line in FIG. 2, respectively. Hereinafter, FIGS.
The same applies to 0, 12, 14 to 19.

The plug implanter can, for example, make phosphorus ions have an acceleration energy of 50 keV and a dose of 1 × 10 ¹³ / cm ² . Further, the introduction of impurities into the polycrystalline silicon film can be performed by introducing phosphorus having a concentration of 2 × 10 ²⁰ / cm ³ by, for example, a CVD method. In addition, this connection hole is 2
An opening is formed by stepwise etching, so that excessive etching of the semiconductor substrate 1 can be prevented. In addition, connection plug 2
1 and 22 can also be formed by an etch-back method.

Next, the insulating films 17a, 17 for forming the wirings
b and 17c are sequentially formed, and a tungsten film 33 is formed on the insulating film 17c (FIG. 7). Insulating film 17a,
As the layers 17b and 17c, a silicon oxide film, a silicon nitride film and a silicon oxide film can be applied, respectively. The silicon oxide film and the silicon nitride film can be formed by a CVD method or a sputtering method.

Next, a photoresist film 34 is formed on the tungsten film 33. The photoresist film 34 is formed as shown in FIG.
9 and as shown in FIG. 9, an opening is formed in a region where the bit line BL is formed. That is, in the memory cell formation region, the photoresist film 34 is formed linearly. For this reason, even if it is fine patterning, diffraction of exposure light hardly occurs, and exposure can be performed with high accuracy, which is advantageous for miniaturization.

Next, the tungsten film 33 is etched using the photoresist film 34 as a mask (FIG. 9). The patterned tungsten film 33 is used as a mask when etching the insulating film 17c. In addition, as described later, it functions as a part of a mask when forming the wiring groove 18b in the insulating film 17a.

Next, after removing the photoresist film 34, the insulating films 17c and 17b are etched using the patterned tungsten film 33 as a mask.
A wiring groove 18a is formed in the insulating film 17c (FIG. 10).

In forming the wiring groove 18a, first, as a first etching, the insulating film 17c is etched using the tungsten film 33 as a mask. This first etching is
The etching is performed under the condition that the etching rate of the insulating film 17c (eg, a silicon oxide film) is high and the etching rate of the insulating film 17b (eg, a silicon nitride film) is low. That is, in the first etching, the insulating film 17b (for example, a silicon nitride film) functions as an etching stopper for the insulating film 11c (for example, a silicon oxide film). By providing the insulating film 17b in this manner, sufficient over-etching can be performed in the first etching. The non-uniformity of the etching rate in the semiconductor wafer in the etching step appears as a variation in the etching depth. Even if the etching rate in the first etching has a variation in the wafer, sufficient over-etching is performed. By using the insulating film 17b as an etching stopper, the etching depth can be made uniform. Next, the insulating film 17b is etched as a second etching. The second etching is performed under the condition that the etching rate of the insulating film 17b (for example, a silicon nitride film) is low. The insulating film 17b can be formed to be thinner than the insulating film 17c. By forming such a thin film, even if over-etching is performed at the time of the second etching, the insulating film 17b is relatively thin, so Excessive etching of a certain insulating film 17a can be reduced. In other words, the etching of the insulating films 17c and 17b is divided into two stages, and the etching is performed under the above conditions, so that the depth of the wiring groove 18a can be made uniform and the wiring groove 18a can be formed reliably. .

Next, as shown in FIG. 11, a photoresist film 35 is formed, and the insulating film 17a is etched in the presence of the photoresist film 35 and the tungsten film 33 (FIG. 12). Thereby, the wiring groove 18b is formed. The photoresist film 35 is formed in a straight line parallel to the y direction (the extending direction of the word line WL) as shown in the figure. That is, the photoresist film 35 has a connection plug BP (plug 2) connecting the central portion of the active region L1 and the bit line BL.
Conversely, it is formed in a stripe shape so as to cover the capacitor electrode connection holes SNCT at both end regions of the active region L1 so that the region where 1) is formed is not covered.

On the other hand, at this stage, the tungsten film 33 still exists. Therefore, the tungsten film 3
Insulating films 17a, 17b, 17 in the region where 3 is formed
c is not etched even if the photoresist film 35 does not exist. That is, the region of the insulating film 17a to be etched is a region where the tungsten film 33 is not formed and is not covered with the photoresist film 35. That is, the etching at this stage is only at the bottom of the wiring groove 18a that is not covered with the photoresist film 35.

As described above, by etching using the photoresist film 35 and the tungsten film 33 as a mask, the wiring groove 18b is self-aligned with respect to the wiring groove 18a in the y direction (the extending direction of the word line WL). Formed. As described later, the bit line BL is formed in the wiring groove 18a.
Are formed, and the bit line BL and the plug 21 are connected to the wiring groove 18.
b, the wiring groove 18b functions as a bit line connection hole. That is, the wiring groove 18b functioning as the bit line connection hole can be formed in a self-aligned manner with respect to the bit line BL, and the electrical connection between the bit line BL and the plug 21 can be realized easily and with high reliability.

Further, the accuracy of the mask for opening the bit line connection hole can be reduced. In other words, the alignment of the wiring groove 18b, which is a bit line connection hole, in the y direction need not be performed because the wiring groove 18a (tungsten film 33) is already self-aligned, and the photoresist film 35 has an opening above the plug 21. Such patterning is sufficient, and it is not necessary to increase the processing accuracy. The opening width of the photoresist film 35 (the width of the region where the photoresist film 35 is not formed) can be formed to be larger than the width of the plug 21, and alignment for forming the photoresist film 35 by the margin of the width is performed in the x direction. May be shifted. Even if such a shift occurs, the wiring groove 18b
As long as the bit line BL is connected to the plug 21 via the
It does not hinder the performance of AM.

Next, as shown in FIG. 13, a photoresist film 36 is formed, and a connection hole connected to the source / drain region (high concentration impurity region 15b) of the MISFET in the peripheral circuit region is opened. In the step of opening the connection hole, two-stage etching of a first etching using the silicon nitride film 14 as a stopper and a second etching for etching the silicon nitride film 14 are performed to form a surface of the semiconductor substrate 1. Excessive etching of the isolation region 7 can be prevented. This connection hole is for connecting the first layer wiring 20 directly to the high-concentration impurity region 15b, thereby reducing the wiring resistance in the peripheral circuit region and improving the performance of the DRAM. Note that a connection plug may be formed in advance in a region where the connection hole is formed.

The thicknesses of the insulating films 17a, 17b, 17c can be, for example, 200 nm, 50 nm, and 200 nm, respectively. The depths of the wiring grooves 18a and 18b can be, for example, 250 nm and 200 nm, respectively, and the width of the wiring groove 18a can be 180 nm.

Next, for example, by sputtering,
A 00 nm tungsten film 37 is formed on the entire surface of the semiconductor substrate 1 (FIG. 14). Here, the tungsten film 37 is illustrated, but another metal film, for example, a copper film or the like may be used. However, in consideration of a decrease in reliability due to thermal diffusion of metal atoms to the semiconductor substrate 1, the metal film is preferably a high melting point metal. For example, molybdenum, tantalum, niobium and the like can be exemplified.

Next, the tungsten film 37 and the tungsten film 33 are polished by, for example, a CMP method, and the tungsten film 3 except for the tungsten film 33 and the wiring groove 18a is polished.
7 are removed, and the bit line BL and the first layer wiring 20 are formed (FIG. 15). Note that an etch-back method can be used to remove the tungsten film 37.

Next, for example, a CV
A silicon oxide film is deposited by the method D, and the silicon oxide film is polished and planarized by the CMP method.
To form Thereafter, a silicon nitride film 24 and a polycrystalline silicon film 38 are deposited on the entire surface of the semiconductor substrate 1. Phosphorus having a concentration of, for example, 3 × 10 ²⁰ / cm ³ can be introduced into the polycrystalline silicon film 38, and its thickness is, for example, 100 nm.

Next, an opening is formed in the polycrystalline silicon film 38 according to the SNCT pattern shown in FIG. The diameter of the opening is, for example, 0.22 μm. Thereafter, a polycrystalline silicon film similar to the polycrystalline silicon film 38 is deposited on the entire surface of the semiconductor substrate 1 to a thickness of 70 nm, and this is anisotropically etched to form a sidewall spacer 39 on the side wall of the opening. The width of the sidewall spacer 39 is about 70 nm
And the diameter of the opening is the side wall spacer 39
Is reduced to 80 nm.

Next, etching is performed by using the polycrystalline silicon film 38 and the sidewall spacers 39 as a hard mask to form the capacitor electrode connection holes 26 (FIG. 16). The diameter of the capacitor electrode connection hole 26 is 80 nm, and its depth is about 300 nm.

As described above, since the diameter of the capacitor electrode connection hole 26 can be reduced, even if the mask for forming the opening is misaligned, it does not contact the bit line BL.

Next, a polycrystalline silicon film filling the capacitor electrode connection hole 26 is deposited, and this polycrystalline silicon film,
The connection plug 25 is formed inside the capacitor electrode connection hole 26 by removing by the MP method or the etch back method (FIG. 1).
7). For example, phosphorus having a concentration of 3 × 10 ²⁰ / cm ³ can be introduced into the connection plug 25. When removing the polycrystalline silicon film, the polycrystalline silicon film 38, and the sidewall spacer 39, the silicon nitride film 24 can function as an etch stopper film by a CMP method or an etch back method.

Next, an insulating film 40 made of a silicon oxide film is deposited by, for example, a CVD method, and a groove 41 is formed in a region where the capacitor C is to be formed. The insulating film 40 can be deposited by plasma CVD, and its thickness is, for example, 1.2 μm.

Next, a polycrystalline silicon film 42 covering the groove 41
Is deposited on the entire surface of the semiconductor substrate 1, and a silicon oxide film 43 is further deposited on the entire surface of the semiconductor substrate 1 (FIG. 18). The polycrystalline silicon film 42 can be doped with phosphorus, and its thickness can be 0.03 μm. Since the thickness of the polycrystalline silicon film 42 is sufficiently smaller than the dimension of the groove 41, the polycrystalline silicon film 42 is deposited with good step coverage inside the groove 41. The silicon oxide film 43 is deposited so as to be buried inside the groove 41. In consideration of the embedding property in the groove 41, the silicon oxide film 43 can be an SOG film or a silicon oxide film formed by a CVD method using TEOS.

Next, the silicon oxide film 43 on the insulating film 40
And the polysilicon film 42 is removed, and the capacitor C
Is formed. The removal of the silicon oxide film 43 and the polycrystalline silicon film 42 is performed by an etch-back method or C
It can be performed by the MP method. After that, the silicon oxide film 43 and the insulating film 40 remaining inside the lower electrode 27 are removed by performing wet etching. Thereby, the lower electrode 27 is exposed. Note that a photoresist film may be formed in the peripheral circuit region, and the insulating film 40 may be left in the peripheral circuit region using the photoresist film as a mask. Note that the silicon nitride film 24 functions as an etching stopper in this wet etching step.

Next, after nitriding or oxynitriding the surface of the lower electrode 27, a tantalum oxide film is deposited,
8 is formed. The tantalum oxide film can be deposited by a CVD method using an organic tantalum gas as a raw material. At this stage, the tantalum oxide film has an amorphous structure. Here, a heat treatment is performed on the tantalum oxide film to form a crystallized (polycrystallized) tantalum oxide film (Ta ₂ O ₅ ).
The capacitance insulating film 28 may be formed as a stronger dielectric. Thereafter, the titanium nitride film serving as the plate electrode 29 is
The titanium nitride film and the polycrystalline tantalum oxide film are deposited by a VD method and patterned using a photoresist film to form a capacitance insulating film 28 and a plate electrode 29. Thus, the capacitor C including the lower electrode 27, the capacitor insulating film 28, and the plate electrode 29 is formed (FIG. 19). Note that the plate electrode 29 may be a polycrystalline silicon film containing phosphorus at a concentration of, for example, 4 × 10 ²⁰ / cm ³ , instead of the titanium nitride film.

Thereafter, the insulating film 30 is formed on the entire surface of the semiconductor substrate 1.
Is formed, a connection hole is formed in the insulating film 30, and, for example, a titanium film, a titanium nitride film, and a tungsten film are sequentially deposited on the insulating film 30 including the connection hole, and this is removed by a CMP method or an etch-back method. To form a plug 32,
Thereafter, a laminated film composed of, for example, a titanium nitride film, an aluminum film, and a titanium nitride film is deposited on the insulating film 30 and is patterned to form the second-layer wiring 31. Thus, the DRAM shown in FIG. 3 is almost completed. Since the upper wiring layer can be formed in the same manner as the second-layer wiring 31, detailed description thereof is omitted.

According to the DRAM of the present embodiment, the wiring groove 18b functioning as a bit line connection hole is formed in the bit line BL.
The bit line B is etched by using the tungsten film 33 functioning as a mask for forming the wiring groove 18a in which is formed the photoresist film 35 formed in a stripe shape in the y direction (word line WL direction) as a mask.
L can be formed in a self-aligned manner. Thus, the electrical connection between the bit line BL and the plug 21 can be realized easily and with high reliability.

As shown in FIG. 20, an insulating film 44 having an etching selectivity with respect to the insulating film 17a can be formed between the insulating film 16 and the insulating film 17a.
20 (a), (b) and (c) are cross-sectional views showing this case in the order of steps, and FIG. 20 (a) is a sectional view of FIG.
FIG. 20C corresponds to the step of FIG.
Examples of the insulating film 44 include a silicon nitride film,
The film thickness is, for example, 50 nm.

By providing the insulating film 44 as described above, the etching at the time of forming the wiring groove 18b can be performed.
The etching can be performed by two-stage etching similarly to the etching of a. Thus, excessive etching of the wiring groove 18b can be prevented.

(Embodiment 2) FIGS. 21 to 26 are sectional views or plan views showing an example of a method of manufacturing a DRAM of Embodiment 2 in the order of steps. It should be noted that FIGS.
5 and 26, (a), (b), (c) and (d) respectively show a cross section taken along a line CC, a line AA, a line DD and a line BB in FIG. Show.

The DRAM according to the present embodiment is similar to the DRAM according to the first embodiment.
Is different in the structure and manufacturing method of the bit line BL (first layer wiring 20). Therefore, only the differences will be described.

The manufacturing process of the DRAM of the present embodiment is the same as that of the first embodiment up to the process of FIG.

Thereafter, the wiring groove 1 is formed over the entire surface of the semiconductor substrate 1.
A tungsten film for embedding 8a is deposited. The thickness of the tungsten film is set to such a degree that the tungsten film is deposited with good coverage inside the wiring groove 18a, for example, 60 nm. By anisotropically etching this tungsten film, the wiring groove 18a is formed.
A sidewall spacer 45 made of tungsten is formed on the inner side wall (FIG. 21). The wiring groove 18a at this time
FIG. 22 shows a plane pattern of the side wall spacer 45 formed on the inner side wall thereof. A wiring groove 18b is formed in a region sandwiched between the sidewall spacers 45 as described below, and has a width of about 60 nm.

Next, the insulating film 17a is etched using the tungsten film 33 and the sidewall spacers 45 as masks to form wiring grooves 18b (FIG. 23). In addition,
No photoresist film is used during this etching. That is, the wiring groove 18b is etched using the tungsten film 33 and the sidewall spacer 45 as a mask without using a photoresist film.
Like a, it is continuously formed in the x direction (the direction in which the bit line BL extends). Part of the bit line BL is formed in the wiring groove 18b as described later, and the plug 2
The wiring groove 18b does not expose the plug 22 even if it is formed to extend continuously in the x direction. That is, the width of the wiring groove 18b is reduced by the formation of the sidewall spacer 45. For this reason, the bit line BL is not connected to the plug 22, and the insulation from the plug 22 is maintained.

A part of the bit line BL formed in the wiring groove 18b can be considered as a kind of bit line connecting portion. That is, the wiring groove 18b can be considered as a bit line connection hole. When considered in this way, the bit line connection hole is formed in a self-aligned manner with respect to the wiring groove 18a, that is, the bit line BL, and the fine processing becomes easy as in the first embodiment.

In this embodiment, a kind of bit line connection hole can be formed without using a photoresist film, and the process can be simplified.

Next, as shown in FIG. 24, a photoresist film 36 is formed, and a connection hole connected to the source / drain region (high concentration impurity region 15b) of the MISFET in the peripheral circuit region is opened. This step is the same as that shown in FIG.
This is the same as the third step.

Next, similarly to the first embodiment, a tungsten film 37 having a thickness of 300 nm is formed by, for example, a sputtering method.
Is formed on the entire surface of the semiconductor substrate 1 (FIG. 25), and the tungsten film 37 and the tungsten film 33 are polished by, for example, a CMP method (FIG. 26). At this time, the upper part of the sidewall spacer 45 is also polished, and the surface is flattened. As a result, the bit lines BL and the first layer wirings 20 composed of the sidewall spacers 45 and the tungsten film 37 are formed. Subsequent steps are the same as in the first embodiment.

According to the DRAM of this embodiment, the sidewall spacer 45 is formed on the inner side wall of the wiring groove 18a, and the wiring groove 18b is formed by using this as a mask. Therefore, it is necessary to form a photoresist film. Absent. Therefore, the wiring groove 18b can be formed in a self-aligned manner with respect to the wiring groove 18a, and the process can be simplified. Furthermore, since the sidewall spacers 45 are made of tungsten which can be used as a part of the wiring (bit line BL, first layer wiring 20), the wiring height (the depth of the wiring groove 18a) can be reduced. As a result, it is possible to improve the performance of the DRAM, such as improving the sensitivity of detecting the accumulated charge by reducing the capacitance between wirings. Since the width of the wiring groove 18b is narrow, the width of a portion of the bit line BL connected to the plug 21 is formed to be narrow. Therefore, the contribution of the inter-wiring capacitance in the narrow wiring width region can be reduced.

Although the present embodiment is characterized in that a photoresist film is not formed when forming the wiring groove 18b, a photoresist film 46 can be formed as shown in FIG. The photoresist film 46 can be formed in the same manner as the photoresist film 35 of the first embodiment. In this case, as shown in FIG. 28, the wiring groove 18b is formed in the peripheral region of the plug 21, and is not formed continuously in the extending direction of the wiring groove 18a. Therefore, the bit line B
After forming the L, as shown in FIG.
A portion of the bit line BL filled in the wiring groove 18b (plug connecting portion 47) is formed on the upper portion, and no connecting portion is formed in the other bit line extending direction. Therefore, the capacity between the wirings can be further reduced, and the performance of the DRAM can be improved.

Also, as in this embodiment, the wiring groove 18a
When the sidewall spacer 45 is formed on the inner side wall of the semiconductor device, the contact region in the peripheral circuit region can be widened as shown in FIG. By increasing the contact area in the peripheral circuit region in this manner, a contact area in the peripheral circuit region can be secured and the contact resistance can be reduced.

Also, as in the first embodiment, the insulating film 16
Needless to say, an insulating film 44 having an etching selectivity with respect to the insulating film 17a can be formed between the insulating film 17a and the insulating film 17a.

(Embodiment 3) FIGS. 31 and 32 are sectional views showing an example of a method of manufacturing a DRAM of Embodiment 3 in the order of steps. 31 and 32,
(A), (b) and (c), or (d), (e)
And (f) are cross sections taken along the line AA in FIG.
The D line cross section and the BB line cross section are shown.

The DRAM of the present embodiment is similar to that of the first embodiment.
And the structure and manufacturing method of the bit line BL (first layer wiring 20), and the structure of the insulating film on which the bit line BL is formed. Therefore, only the differences will be described.

The manufacturing process of the DRAM of the present embodiment is the same as that of the first embodiment up to the process of FIG. However, in the present embodiment, the insulating film 48 in which the wiring groove is formed is not a three-layer film composed of the insulating films 17a, 17b, and 17c as in the first embodiment, but a single-layer film. The insulating film 48 can be, for example, a TEOS oxide film.

As in the step of FIG. 9 of the first embodiment, the tungsten film 33 is patterned, and then a tungsten film (not shown) covering the patterned tungsten film 33 is deposited. By performing the reactive etching, sidewall spacers 49 made of tungsten are formed on the side walls of the tungsten film 33 (FIGS. 31A, 31B and 31C). The patterning of the tungsten film 33 is performed with the minimum processing dimension of photolithography. By forming the sidewall spacer 49, a space smaller than the minimum processing dimension can be formed.

Next, the insulating film 48 is etched using the tungsten film 33 and the sidewall spacer 49 as a mask. Thereby, the wiring groove 50 is formed (FIG. 31).
(D), (e) and (f)). The wiring groove 50 is formed with a width equal to or smaller than the minimum processing dimension of photolithography as described above.

When forming the wiring groove 50, a photoresist film is not used as in the second embodiment. Thereby, the process can be simplified.

The plug 2 is located at the bottom of the wiring groove 50.
1 is exposed. Therefore, as explained below,
If the bit line BL is formed inside the wiring groove 50, the bit line itself is electrically connected to the plug 21, and there is no need to form a bit line connection hole. That is, it is possible to omit the formation of the bit line connection hole and eliminate the problem of the mask misalignment between the plug 21 and the bit line BL due to the patterning of the bit line connection hole.

Next, as in the first embodiment, after forming the connection holes of the peripheral circuit, a 300 nm-thick tungsten film 37 is formed on the entire surface of the semiconductor substrate 1 by, for example, a sputtering method (FIG. 32 ( a), (b) and (c)), the tungsten film 37, the side wall spacer 49 and the tungsten film 33 are polished by, for example, a CMP method (FIGS. 32 (d), (e) and (f)). This allows
A bit line BL (first layer wiring 20) is formed. The wiring width of the bit line BL formed in this manner is smaller than in the first and second embodiments. This makes it possible to increase the distance between the wires and reduce the capacitance between the wires. Therefore, the detection sensitivity of the accumulated charge can be improved, and the performance of the DRAM can be improved. Subsequent steps are the same as in the first embodiment.

According to the DRAM of this embodiment, the wiring groove 50 having the function of the bit line connection hole can be formed without using a photoresist film. This simplifies the process and avoids the problem of misalignment of the mask due to the formation of the bit line connection hole. In addition, since the wiring width of the bit line BL can be reduced, the distance between the wirings can be increased to reduce the capacitance between the bit lines, thereby improving the performance of the DRAM such as improving the detection sensitivity of the stored charge.

As shown in FIG. 33, at the time of patterning the tungsten film 33, the insulating film 48 serving as a base is excessively etched, and the bottom of the sidewall spacer 49 is formed at an altitude lower than the bottom of the tungsten film 33. (FIGS. 33 (a), (b) and (c)). In the bit line BL thus formed, a part of the side wall spacer 49 can be left near the surface of the insulating film 48 as a part thereof. A part of the side wall spacer 49 allows the bit line B
By increasing the cross-sectional area of L and reducing the wiring resistance, it is possible to contribute to higher performance of the DRAM.

In the present embodiment, as in the second embodiment, the contact region in the peripheral circuit region is formed as shown in FIG.
As in the first embodiment, a silicon nitride film or the like having an etching selectivity with respect to the insulating film 48 can be formed between the insulating film 16 and the insulating film 48 as in the first embodiment. It goes without saying that you can do it.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, in the first embodiment, the capacitor C
Although an example of a capacitor having a cylindrical lower electrode having an opening above has been described above, a simple stack type capacitor may be used.

The bit line BL of the present embodiment (first
The method of forming the layer wiring 20) is not limited to the DRAM,
The present invention can be applied to a logic circuit incorporating an AM, a microcomputer incorporating a flash memory incorporating a DRAM, and other system-embedded chips.

Further, the bit line BL (first
The method of forming the layer wiring 20) is not limited to the formation of the first layer wiring, but may be applied to the formation of the second layer wiring or more. In this case, as shown in FIG.
1 is formed on the insulating film 52 covering the N-th layer wiring 51.
+1) When the connection hole 53 of the layer wiring is opened, it can be formed so as to overlap the N-th layer wiring 51. Thereby, electrical connection between the N-th layer wiring 51 and the (N + 1) -th layer wiring can be easily performed.

The photoresist film formed on the tungsten film 33 can be a photoresist film 54 having a pattern having island-shaped openings as shown in FIG. By doing so, it is possible to reduce the number of wiring grooves 18b formed in a region that is not used for connection with the active region of the MISFET and the number of connection plugs formed in the wiring groove 18b, thereby promoting a reduction in bit line BL capacitance. can do. At this time, it is preferable that the length of the opening in the Y direction is set so that the opening does not cover an adjacent wiring groove, even in consideration of misalignment of the mask. 36 (a) to (d) and FIGS. 37 (a) to (d)
FIG. 36 is a cross-sectional view showing, in the order of steps, the method of manufacturing the DRAM according to the example shown in FIG. 35.

Further, a TiSi film, a laminated film of a TiSi film and a TiN film, etc. are provided between the tungsten film 33 forming the bit line BL and the connection plug and the connection plugs 21 and 22 formed of the polycrystalline silicon film. Forming the tungsten film 33 and the connection plug 21,
22 and can reduce the contact resistance.

[0109]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, in a miniaturized DRAM memory cell, an electrical connection between a bit line and a connection plug can be realized by self-alignment in a word line direction, and an electrical connection between a bit line and a connection plug can be realized. Can be realized simply and with high reliability. (2) According to the present invention, it is possible to simplify the process of forming a connection portion between a bit line and a connection plug. (3) According to the present invention, it is possible to reduce the capacitance between bit lines, improve the sensitivity of detecting stored charges, and improve the performance of the DRAM. (4) According to the present invention, the mask used for forming the wiring groove for burying the bit line is left, and the mask for forming the wiring groove for forming the connection plug inside is left. When used as one, the bit line and the connection plug are self-aligned in the width direction of the bit line. Therefore, no connection plug is formed below the insulating film in the same layer as the bit line defining the distance between the bit lines, and the distance between the connection plugs is also specified to be equal to or greater than the width of the insulating film. Is done. Therefore, it is possible to prevent an increase in capacitance between bit lines due to a shift between the connection plug pattern and the bit line pattern, and a short circuit between the connection plug and the bit line.

[Brief description of the drawings]

FIG. 1A is a plan view illustrating an example of an entire semiconductor chip on which a DRAM according to a first embodiment is formed, and FIG.
FIG. 2 is an equivalent circuit diagram of the DRAM of the first embodiment.

FIG. 2 is an enlarged plan view of a part of a memory array MARY in FIG. 1;

FIGS. 3A to 3D are partial cross-sectional views of a DRAM according to an embodiment of the present invention.

FIGS. 4A and 4B are diagrams illustrating DRA according to the first embodiment;
FIG. 6 is a cross-sectional view illustrating an example of a method for manufacturing M in the order of steps;
(C) is a plan view.

FIG. 5A is a cross-sectional view showing an example of a method for manufacturing the DRAM of the first embodiment in the order of steps, and FIG. 5B is a plan view.

FIGS. 6A to 6D are cross-sectional views illustrating an example of a method for manufacturing the DRAM of the first embodiment in the order of steps; FIGS.

FIGS. 7A to 7D are cross-sectional views illustrating an example of a method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 8 is a plan view showing an example of a method for manufacturing the DRAM of the first embodiment in the order of steps.

FIGS. 9A to 9D are cross-sectional views illustrating an example of a method of manufacturing the DRAM according to the first embodiment in the order of steps; FIGS.

FIGS. 10A to 10D are DRAMs according to the first embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIG. 11 is a plan view showing one example of a method of manufacturing the DRAM of the first embodiment in the order of steps;

FIGS. 12A to 12D are DRAMs according to the first embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIG. 13 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIGS. 14A to 14D are DRAMs according to the first embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIGS. 15A to 15D are DRAMs according to the first embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIGS. 16A to 16D are DRAMs according to the first embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIGS. 17A to 17D are diagrams illustrating a DRAM according to the first embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIGS. 18A to 18D are DRAMs according to the first embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIGS. 19A to 19D are DRAMs according to the first embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIGS. 20A to 20C are DRAMs according to the first embodiment;
FIG. 6 is a cross-sectional view showing another example of the manufacturing method of the present invention in the order of steps.

FIGS. 21A to 21D are diagrams illustrating a DRAM according to a second embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIG. 22 is a plan view showing one example of the method of manufacturing the DRAM of the second embodiment in the order of steps;

FIGS. 23A to 23D are diagrams illustrating a DRAM according to a second embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIG. 24 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the second embodiment in the order of steps;

FIGS. 25A to 25D are diagrams illustrating a DRAM according to a second embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIGS. 26A to 26D are diagrams illustrating a DRAM according to a second embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIG. 27 is a plan view showing another example of the method for manufacturing the DRAM according to the second embodiment in the order of steps;

FIGS. 28A to 28D are diagrams illustrating a DRAM according to a second embodiment;
FIG. 6 is a cross-sectional view showing another example of the manufacturing method of the present invention in the order of steps.

FIGS. 29A to 29D are diagrams illustrating a DRAM according to a second embodiment;
FIG. 6 is a cross-sectional view showing another example of the manufacturing method of the present invention in the order of steps.

FIG. 30 is a plan view showing still another example of the method for manufacturing the DRAM of the second embodiment.

FIGS. 31A to 31F are diagrams illustrating a DRAM according to a third embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIGS. 32A to 32F are diagrams illustrating a DRAM according to a third embodiment;
FIG. 4 is a cross-sectional view showing an example of the manufacturing method of the present invention in the order of steps.

FIGS. 33A to 33F are diagrams illustrating a DRAM according to a third embodiment;
FIG. 6 is a cross-sectional view showing another example of the manufacturing method of the present invention in the order of steps.

FIG. 34 is a sectional view showing another example of the present invention.

FIG. 35 is a plan view showing another example of the present invention.

36 (a) to (d) are cross-sectional views showing another example of a method for manufacturing a DRAM in the order of steps.

FIGS. 37A to 37D are cross-sectional views illustrating another example of a method for manufacturing a DRAM in the order of steps.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 1A semiconductor chip 2 p-type well 3 p-type well 4 n-type well 5 threshold voltage adjusting layer 6 deep well 7 isolation region 8 shallow groove 10 gate insulating film 11 gate electrode 11c insulating film 12 semiconductor region 13 cap insulating Film 14 silicon nitride film 15 semiconductor region 15a low-concentration impurity region 15b high-concentration impurity region 16 insulating film 17a insulating film (TEOS oxide film) 17b insulating film (silicon nitride film) 17c insulating film (TEOS oxide film) 18a wiring groove 18b wiring Groove 20 First layer wiring 21 Plug 22 Plug 23 Interlayer insulating film 24 Insulating film (silicon nitride film) 25 Connection plug 26 Capacitive electrode connecting hole 27 Lower electrode 28 Capacitive insulating film 29 Plate electrode (upper electrode) 30 Insulating film 31 Second Layer wiring 32 plug 33 tungsten film 34 photo Dist film 35 Photoresist film 36 Photoresist film 37 Tungsten film 38 Polycrystalline silicon film 39 Sidewall spacer 40 Insulating film 41 Groove 42 Polycrystalline silicon film 43 Silicon oxide film 44 Insulating film 45 Sidewall spacer 46 Photoresist film 47 Plug connection Part 48 insulating film 49 side wall spacer 50 wiring groove 51 Nth layer wiring 52 insulating film 53 connection hole BL bit line BP connection plug C capacitor L1 active area MARY memory array Qn n-channel MISFET Qp p-channel MISFET Qs selection MISFET SA sense amplifier SNCT Capacitor electrode connection hole WD Word driver WL Word line

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) LA16 MA06 MA16 MA17 PR29 PR36 PR40

Claims (21)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first semiconductor region, a second semiconductor region, and an isolation region separating the first and second semiconductor regions from each other; Forming a first insulating film on a main surface of the semiconductor substrate including upper portions of the first and second semiconductor regions; (c) forming a first insulating film on the main surface of the semiconductor substrate including upper portions of the first and second semiconductor regions; Forming a second insulating film on the insulating film, and (d) forming the second insulating film on the second insulating film.
Having a first and a second opening above the insulating film
(E) etching the second insulating film exposed at the bottoms of the first and second openings with the second insulating film so that the second insulating film has an etching rate with respect to the first film; Forming the first and second grooves by etching with a method larger than (f), forming a second film covering a part of the first and second grooves with the first and second grooves. Forming a step inside the groove and above the first film;
(G) removing the first insulating film exposed at the bottoms of the first and second grooves by a method in which an etching rate for the first insulating film is higher than an etching rate for the first and second films; Etching to form a third opening at the bottom of the first groove and forming a fourth opening at the bottom of the second groove; (h) removing the second film (I) the inside of the first and second grooves and the third
Forming a first conductor film on the second insulating film including the first insulating film and the inside of the fourth opening; and (j) forming the first conductive film on the first insulating film.
Forming a first wiring which is electrically connected to the first semiconductor region through the third opening inside the first groove by removing a part of the conductive film of Forming a second wiring electrically connected to the second semiconductor region through the fourth opening inside the second groove. 2. A method for manufacturing a semiconductor integrated circuit device having the following steps: (a) a first method in which a gate insulating film, a gate electrode and a pair of semiconductor regions are formed on a main surface of a semiconductor substrate,
And the second MISFET and the first and second M
Forming an isolation region separating the ISFET, (b)
Forming a first insulating film on a main surface of the semiconductor substrate including upper portions of the first and second MISFETs;
(C) forming a second insulating film on the first insulating film; and (d) forming a first film having first and second openings on the second insulating film. (E) removing the second insulating film exposed at the bottom of the first and second openings by etching the second insulating film at a rate higher than the etching rate of the first film. (F) forming a second film covering a part of the first and second grooves with the inside of the first and second grooves. (G) forming the first insulating film exposed at the bottom of the first and second trenches with the first insulating film at an etching rate of the first insulating film equal to the first insulating film; And etching by a method larger than the etching rate for the second film, The third opening is formed in part, forming a fourth opening in the bottom of the second groove, (h)
Removing the second film; (i) forming a first film on the second insulating film including the inside of the first and second grooves and the inside of the third and fourth openings; (J) removing a part of the first conductive film to form the first MISFET through the third opening inside the first groove by removing a part of the first conductive film; Forming a first wiring electrically connected to one of the pair of semiconductor regions, and forming the second wiring through the fourth opening in the second groove.
Forming a second wiring electrically connected to one of the pair of semiconductor regions of the ISFET; 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein: (k) a first capacitor electrically connected to the other of the pair of semiconductor regions of the first MISFET; Forming a second capacitor electrically connected to the other of the pair of semiconductor regions of the MISFET. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said step (d) comprises said first and second MISFETs.
Forming a third film on the main surface of the semiconductor substrate including an upper portion of the semiconductor film, forming a photoresist film having an opening on the third film, and opening the photoresist film A step of forming a second opening by etching the third film at the bottom of the first film and forming a first film composed of a part of the third film. Device manufacturing method. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein in the step (d), a film containing the same material as the first film on inner walls of the first and second openings. A method of manufacturing a semiconductor integrated circuit device, further comprising the step of forming a sidewall spacer constituted by: 6. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein said second film is a photoresist film. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein in the step (c), a first insulating film is formed, and a second insulating film is formed on the first insulating film. Forming a second insulating film composed of the first and second insulating films by forming a first insulating film; and the step (e) includes the first and second insulating films. The etching rate of the second insulating film exposed at the bottom of the opening of the second insulating film is lower than the etching rate of the first insulating film and the etching rate of the first insulating film. Etching by a large method, and then the first insulating film is
A step of forming the first and second grooves by etching using a method in which an etching rate for the first insulating film is higher than an etching rate for the first film. A method for manufacturing an integrated circuit device. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the second film formed in the step (f) has a fifth opening above a part of the first groove. And a sixth opening in a part of the second groove. The width of the fifth opening is larger than the width of the first groove, and the fifth opening The portion exposes not only a part of the first groove but also a part of the first film, and the width of the sixth opening is larger than the width of the second groove, A method of manufacturing a semiconductor integrated circuit device, wherein not only a part of the second groove but also a part of the first film is exposed by a sixth opening. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the second film formed in the step (f) has a fifth opening above a part of the first groove. A fifth opening having a sixth opening in a part of the second groove, wherein a width of the fifth opening is larger than a width of the first groove; By this, not only a part of the first groove but also a part of the first film on both sides of the first groove is exposed, and the width of the sixth opening is the second groove. And the sixth opening exposes not only a part of the second groove but also a part of the first film on both sides of the second groove. Of manufacturing a semiconductor integrated circuit device. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the first film is made of the same material as the first conductor film, and a part of the first conductor film. The method of manufacturing a semiconductor integrated circuit device, wherein in the step (j) of removing, the first conductive film is removed subsequently. 11. The method of manufacturing a semiconductor integrated circuit device according to claim 2, further comprising: (k) a step of forming a sidewall spacer made of a conductive film on an inner wall of the first and second grooves. The method of manufacturing a semiconductor integrated circuit device, wherein the etching in the step (g) is performed by a method in which an etching rate for the first insulating film is higher than an etching rate for the sidewall spacer. 12. A first and second MISFETs formed on a main surface of a semiconductor substrate, each having a source, a drain region, a gate insulating film and a gate electrode, and formed on a main surface of the semiconductor substrate, First MISF
ET source and drain regions and the second MISFET
An isolation region separating the source and drain regions of the first and second MISFETs; a first insulating film formed on the first and second MISFETs; and a second insulating film formed on the first insulating film A semiconductor integrated circuit device having: first and second conductors formed inside the second insulating film; and first and second wirings formed on the second insulating film. Wherein the first wiring is connected to the first wiring via the first conductor.
The MISFET is electrically connected to one of a source and a drain of the MISFET, and the second wiring is connected to the second conductor via the second conductor.
A semiconductor integrated circuit device electrically connected to one of a source and a drain of the MISFET, wherein the first and second conductors are not formed immediately below the second insulating film. 13. The semiconductor integrated circuit device according to claim 12, further comprising: a source of said first MISFET;
A semiconductor integrated circuit comprising: a first capacitance element electrically connected to the other of the drain; and a second capacitance element electrically connected to the other of the source and the drain of the second MISFET. Circuit device. 14. The semiconductor integrated circuit device according to claim 13, further comprising a sense amplifier formed on a main surface of said semiconductor substrate, wherein said first wiring and said second wiring are A semiconductor integrated circuit device connected via a sense amplifier. 15. The semiconductor integrated circuit device according to claim 13, further comprising a third conductor formed in said second insulating film between said first and second wirings, wherein said third conductor is formed between said first and second wirings. Of the first element via the third conductor.
A semiconductor integrated circuit device electrically connected to the other of the source and drain regions of the MISFET. 16. The semiconductor integrated circuit device according to claim 12, further comprising: a third insulating film formed below said first insulating film, wherein a third insulating film is formed inside said third insulating film. 3 conductors are formed, and the first conductor is:
A semiconductor integrated circuit device electrically connected to one of a source and a drain region of the first MISFET via the third conductor. 17. The semiconductor integrated circuit device according to claim 16, wherein said third conductor is made of said first MISFE.
A semiconductor integrated circuit device formed over one of a source and drain region of T and an upper portion of the isolation region. 18. The semiconductor integrated circuit device according to claim 16, wherein a length of said third conductor is longer than a length of said first conductor in a direction parallel to an extending direction of said first wiring. A semiconductor integrated circuit device characterized by being shorter than the above. 19. The semiconductor integrated circuit device according to claim 16, wherein said first conductor has a contact surface with said third conductor, said first conductor being closer to said first wiring than said third conductor. A semiconductor integrated circuit device protruding on both sides in a direction parallel to an extending direction. 20. The semiconductor integrated circuit device according to claim 16, wherein in a direction perpendicular to an extending direction of the first wiring in a plane parallel to a main surface of the semiconductor substrate,
The semiconductor integrated circuit device according to claim 1, wherein a length of the third conductor is longer than a length of the first conductor. 21. The semiconductor integrated circuit device according to claim 16, wherein the third conductor has a contact surface with the first conductor, the third conductor being closer to the first wiring than the first conductor. A semiconductor integrated circuit device protruding on both sides in a direction perpendicular to an extending direction.