JP2000138357A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily make connection holes and fill them with conductor films by connecting a lower wiring layer and an upper wiring layer through a first connection part in contact with the lower wiring and a second connection part in contact with the first connection part for reducing the aspect ratio of the connection holes. SOLUTION: Connection holes 17a and 17b are made in two operations and are respectively filled with conductor films 18a and 25a to form a connection part which connects between a lower wiring layer 14 and an upper wiring layer 26. Since necessary depth of the connection hole 17b is up to the exposure of the top of a plug 18a, the hole is shallower by the height of the plug 18a than a case where the hole is made until a part of the wiring 14 is exposed and the diameter of the connection hole 17b can be also increased. Accordingly, the aspect ratio is reduced and forming of connection holes 17a and 17b, and filling of the holes 17a and 17b with conductor films 18a and 25a can be performed more easily.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor integrated circuit device and a technology of the semiconductor integrated circuit device, and more particularly to a method of manufacturing a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory) and a technology of the semiconductor integrated circuit device. It is related to technology that is effective when applied to

[0002]

2. Description of the Related Art A DRAM has a high degree of integration and a low unit cost per bit because its memory cell is composed of one MIS transistor for selecting a memory cell and a capacitor connected in series with the MIS transistor. It is widely used as a main memory of various computers that require a large-capacity memory, a communication device, and the like.

Meanwhile, the memory capacity of the DRAM tends to increase more and more, and accordingly, the area occupied by the memory cell has to be reduced from the viewpoint of improving the integration degree of the memory cell of the DRAM.

However, the capacitance of an information storage capacitor (capacitor) in a memory cell of a DRAM is different from that of a DRAM.
It is known that a certain amount is required regardless of the generation from the viewpoint of considering the operation margin, soft error, and the like, and that in general, the proportional reduction cannot be performed.

[0005] Therefore, the development of a capacitor structure capable of securing a required storage capacity within a limited small occupied area has been promoted. One of them is to stack two layers of capacitor electrodes via a capacitor insulating film. A three-dimensional capacitor structure such as a so-called stacked capacitor is employed.

In a stacked capacitor, a capacitor electrode has a memory cell selection MOS / FET (Metal Oxide Semico
In general, a structure arranged in an upper layer of the nductor field effect transistor) is a cylindrical or fin-shaped capacitor structure. In any case, by increasing the dimension in the height direction of the capacitor, it is possible to secure a large storage capacity without increasing the dimension in the width direction of the capacitor (that is, with a small occupied area).

A DRAM having a memory cell is described in Japanese Patent Application Laid-Open No. Hei 7-122654 and the like. In this document, an information storage capacitor element is provided in a layer above a bit line, that is, a so-called capacitor-over-capacitor is provided. Bit line (Capacitor Over Bitline; hereinafter abbreviated as COB)
The structure is disclosed.

[0008]

However, the present inventor has found that the above-mentioned technology has the following problems.

That is, the aspect ratio of the connection hole for electrically connecting between different wiring layers or between the wiring and the semiconductor substrate is increased, and it is difficult to form the connection hole and bury the connection hole with a conductive film. This problem becomes a problem particularly in a connection hole portion connecting an upper wiring layer and a lower wiring layer of the capacitor when the information storage capacitive element of the DRAM is formed of a stacked capacitor. This is due to the fact that the capacitor tends to be higher from the viewpoint of increasing the capacity without increasing the occupied area, so that the connection hole becomes deeper.

Further, based on the results of the present invention, the inventor
Investigation of known examples from the viewpoint of DRAM wiring structure,
Such techniques are described, for example, in PCT Publication 97194.
68 were found. This publication discloses a structure in which three embedded wiring layers are provided between a capacitor of a DRAM and a semiconductor substrate. Although a structure in which plugs are stacked in multiple stages is disclosed herein, there is no mention of a structure in which a buried wiring in the same layer as a bit line is drawn to a wiring layer above a capacitor through plugs in multiple stages. It has not been.

An object of the present invention is to provide a technique capable of easily forming a connection hole for connecting different wiring layers and embedding the connection hole in a conductive film.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A method of manufacturing a semiconductor integrated circuit device according to the present invention is directed to a semiconductor integrated circuit in which a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the memory cell selection transistor are provided on a semiconductor substrate. A method of manufacturing a circuit device, comprising: forming a bit line and a first line on a semiconductor substrate;
Forming the wiring in the same wiring layer, forming the information storage capacitance element above the bit line without interposing another wiring layer, and forming a second wiring on the information storage capacitance element. Forming a first connection portion electrically connected between the first wiring and the second wiring in a state of being directly contacted with the first wiring; Forming a second connection portion electrically connected to the first connection portion in a state of being in direct contact with the first connection portion.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, the plane size of the second connection portion is larger than the plane size of the first connection portion.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, the first connecting portion may be formed so that the planar size of the second connecting portion can include a plurality of the first connecting portions within the planar size. Is larger than the plane size of the above.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the memory cell selection transistor are provided on a semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device, comprising: (a) forming a bit line and a first wiring in the same wiring layer on the semiconductor substrate;
(B) forming a first insulating film covering the bit lines and the first wiring on the semiconductor substrate; and (c) forming a first insulating film in a region other than the memory cell forming region in the first insulating film. Drilling a first connection hole through which the first wiring is exposed; and (d) forming a first connection portion by burying a first conductor film in the first connection hole. (E) forming a second insulating film made of a material having a relatively large etching selectivity with respect to the first insulating film so as to cover the upper surfaces of the first insulating film and the first connection portion; (F) forming an information storage capacitance element above the bit line in the memory cell formation region; and (g) forming the information storage region in a region other than the memory cell formation region. Between the wiring layer above the capacitive element for use and the first connection portion The second connection hole where the first connection portion is exposed is formed in the provided second insulation film and a third insulation film made of a material having a relatively large etching selectivity with respect to the second insulation film. Perforating; and (h) burying a second conductor film in the second connection hole to form a second connection portion electrically connected to the first connection portion in a state of being directly contacted with the first connection portion. And a step of performing

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the memory cell selection transistor are provided on a semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device, comprising: (a) forming a bit line and a first wiring in the same wiring layer on the semiconductor substrate;
(B) forming a first insulating film covering the bit lines and the first wiring on the semiconductor substrate; and (c) forming a first insulating film in a region other than the memory cell forming region in the first insulating film. Drilling a first connection hole through which the first wiring is exposed; and (d) forming a first connection portion by burying a first conductor film in the first connection hole. (E) forming an information storage capacitor in a region above the bit line in the memory cell formation region; and (f) forming the information storage capacitor in a region other than the memory cell formation region. Drilling a second connection hole exposing the first connection portion in an insulating film provided between an upper wiring layer and the first connection portion; and (g) the second connection hole. A second conductor film is embedded in the inside, and the second conductor film is in direct contact with the first connection portion. And a step of forming a second connecting portion that is gas-connected.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the memory cell selection transistor are provided on a semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device, comprising: (a) forming a bit line and a first wiring in the same wiring layer on the semiconductor substrate;
(B) forming a first insulating film covering the bit lines and the first wiring on the semiconductor substrate; and (c) forming a first insulating film in a region other than the memory cell forming region in the first insulating film. Drilling a first connection hole where the first wiring is exposed, and drilling a connection hole for an information storage capacitance element where the bit line is exposed in the memory cell formation region; d) burying a first conductor film in the first connection hole and the connection hole for the information storage capacitor, and forming a first connection portion and a connection portion for the information storage capacitor, respectively; (E) increasing the etching selectivity relative to the first insulating film so as to cover the upper surfaces of the first insulating film, the first connection portion, and the connection portion for the information storage capacitor. Forming a second insulating film made of a removable material; (f) In a region of the serial memory cells,
Forming an information storage capacitance element above the bit line; and (g) forming a wiring layer above the information storage capacitance element and the first connection portion in a region other than the memory cell formation region. And a second insulating film provided between the second insulating film and a third insulating film made of a material having a relatively large etching selectivity with respect to the second insulating film. (H) embedding a second conductor film in the second connection hole and electrically connecting the second conductor film in a state of being directly in contact with the first connection portion.
And forming a connection portion.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the memory cell selection transistor are provided on a semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device, comprising: (a) forming a bit line and a first wiring in the same wiring layer on the semiconductor substrate;
(B) forming a first insulating film covering the bit line and the first wiring on the semiconductor substrate; and (c) forming a first insulating film on the first insulating film with respect to the first insulating film. Forming a second insulating film made of a material having a relatively high etching selectivity; and (d) forming an information storage capacitor element above the bit line in the memory cell formation region. And (e) in a region other than the memory cell formation region, a first insulating film provided between the wiring layer above the information storage capacitor and the first wiring, a second insulating film Forming a connection hole between wiring layers exposing the first wiring in a third insulating film formed of a material and a material formed thereon and having a relatively high etching selectivity with respect to a second insulating film; And (f) a conductive film in the connection hole between the wiring layers. Forming a connection portion between wiring layers electrically connected in a state of being buried and being in direct contact with the first wiring, wherein the step of forming a connection hole between the wiring layers comprises the third insulating step. Forming a mask pattern for forming a contact hole on the film; and forming a mask pattern using the mask pattern as an etching mask while increasing an etching selectivity between the second insulating film and the third insulating film. By performing the etching process under the condition that the third insulating film is more easily removed by etching than the second insulating film, a part of the second insulating film is exposed on the third insulating film exposed from the mask pattern. A first etching process for drilling a first hole, and after the first etching process, an etching selectivity between the second insulating film and the third insulating film using the mask pattern as an etching mask. The second insulating film exposed from the bottom of the first hole is etched by performing the etching process under the condition that the second insulating film is more easily etched and removed than the third insulating film in a relatively large state. A second etching process for removing and exposing a second hole exposing a part of the first insulating film in the second insulating film; and after the second etching process, the second insulating film In a state where the etching selectivity between the first insulating film and the first insulating film is relatively large, the first insulating film is etched under conditions that are more easily removed by etching than the second insulating film. Removing the first insulating film exposed from the bottom to form a connection hole between the wiring layers where the first wiring is exposed.

Further, in the method for manufacturing a semiconductor integrated circuit device according to the present invention, the step (d) includes a step of forming a first electrode constituting the information storage capacitor, and a step of forming a surface of the first electrode. Forming a second electrode covering the capacitive insulating film, and forming the second electrode covering the capacitive insulating film.
The step includes drilling a second electrode lead-out connection hole penetrating the second electrode in the third insulating film, wherein the second electrode lead-out connection hole and the second electrode lead-out connection hole are provided. The step of forming a connection hole includes the step of forming a mask pattern for forming a connection hole on the third insulating film, and the step of forming a mask pattern of the second insulating film and the third insulating film using the mask pattern as an etching mask. The third insulating film exposed from the mask pattern is formed by performing the etching process under the condition that the third insulating film is more easily removed by etching than the second insulating film in a state where the etching selectivity is relatively large. To
A first hole for forming a connection hole between the wiring layers, the first hole exposing a part of the second insulating film, and a hole for forming a connection hole for leading out the second electrode. The second
A first hole that penetrates the first electrode and a first hole whose bottom extends to an intermediate position in the third insulating film; and after the first etching, the mask pattern is etched. As a mask, the second insulating film is etched under the condition that the etching selectivity between the second insulating film and the third insulating film is relatively large, and the second insulating film is more easily removed by etching than the third insulating film. By processing, the second insulating film exposed from the bottom of the first hole for the connection hole between the wiring layers is removed, and a part of the first insulating film is exposed for the connection hole between the wiring layers. Second to drill a second hole
After the second etching process and the second etching process, the first insulating film has the second etching property with the etching selectivity between the second insulating film and the first insulating film relatively increased. Etching is performed under conditions that are easier to remove by etching than the insulating film described above, thereby forming a connection hole between the wiring layers where the first wiring is exposed from the bottom of the second hole for the connection hole in the wiring interlayer insulating film. 3) an etching treatment step, wherein in the step (f), a conductive film is buried in a connection hole between the wiring layers and a connection hole for leading a second electrode, and each of the conductive films is directly contacted with the first wiring. Forming a connection portion between the wiring layers electrically connected to each other and a second electrode lead-out connection portion electrically connected to the second electrode.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a memory cell composed of a first MISFET and a capacitor connected in series to the first MISFET is formed in a first region of a semiconductor substrate. In the region, the second MISFE
A semiconductor integrated circuit device on which T is formed, wherein (a) forming a first wiring in a second region of a semiconductor substrate;
(B) forming a first insulating film on the first wiring; and (c) forming a first opening in the first insulating film and exposing a part of the first wiring. (D) a step of selectively forming a first conductor layer in the first opening; and (e) a step of forming a second insulation film on the first insulation film and the first conductor layer. f) forming a third insulating film on the second insulating film; (g) forming a second opening in the third insulating film in the first region; and (h) forming the second opening in the third region. Selectively forming a second conductor layer along the inner wall of the aperture;
(I) forming a fourth insulating film and a third conductive layer on the second conductive layer; and (j) forming the first insulating film on the third insulating film and the second insulating film in the second region. Forming a third hole so as to expose a part of the conductor layer, and (k) forming a fourth conductor layer in the third hole, In the forming step, the third insulating film is etched under a condition that an etching rate of the third insulating film is higher than that of the second insulating film. After the third insulating film is etched under a condition that the etching rate of the third insulating film is higher than that of the second insulating film, the second insulating film is etched by the second insulating film.
Under the condition that the etching rate of the insulating film becomes large, the second
The insulating film is etched.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a memory cell including a first MISFET and a capacitor connected in series to the first MISFET is formed in a first region of a semiconductor substrate. The second region has a second MIS
A semiconductor integrated circuit device in which an FET is formed,
(A) forming a first wiring in a second region of a semiconductor substrate; (b) forming a first insulating film on the first wiring; and (c) forming a first insulating film on the first insulating film. Forming a second insulating film; (d) forming a third insulating film on the second insulating film; and (e) forming a second opening in the third insulating film in the first region. Forming; and (f) selectively forming a first conductor layer along an inner wall of the second opening.
(G) forming a fourth insulating film and a second conductive layer on the first conductive layer; and (h) forming the first insulating film on the third insulating film and the second insulating film in the second region. Forming a third opening so as to expose a part of the wiring, and (i) forming a third conductor layer in the third opening, forming the second opening. In the step, the third insulating film is etched under a condition that an etching rate of the third insulating film is higher than that of the second insulating film. After the third insulating film is etched under the condition that the etching rate of the third insulating film is higher than that of the insulating film, the etching rate of the second insulating film is higher than that of the first insulating film. The etching is performed on the second insulating film under a large condition so that a part of the first wiring is exposed. In which etching is performed on the first insulating film.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. , And the repeated explanation is omitted).

(Embodiment 1) FIGS. 1 to 8 are cross-sectional views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.

In the first embodiment, for example, 256
A case where the technical idea of the present invention is applied to an M-DRAM will be described.

FIG. 1 is a sectional view showing a main part of the DRAM during a manufacturing process. The semiconductor substrate 1 is, for example, p-
Shaped silicon single crystal. A deep n-well 2nw is formed in the memory area (left side in FIG. 1) of the semiconductor substrate 1. Into the deep n-well 2nw, for example, phosphorus as an n-type impurity is introduced.

In this deep n-well 2nw, there is a p-well 3
pwm is formed. The p-well 3pwm is formed between the deep n-well 2nw and the p-well 3p
It is surrounded by an n-well provided on the side of wm and is electrically isolated from the peripheral circuit region and the like. For example, boron as a p-type impurity is introduced into the p-well 3pwm.

In the semiconductor substrate 1, a p-well 3pwm of a memory region is provided in a peripheral circuit region and the like (right side in FIG. 1).
A p-well 3pwp is formed in a depth region substantially the same as that of FIG. For example, boron as a p-type impurity is introduced into the p-well 3pwp.

In the semiconductor substrate 1, an n-well 3nwp is formed in a peripheral circuit region or the like in a region approximately as deep as the p-well 3pwm in the memory cell region.
For example, phosphorus or arsenic as an n-type impurity is introduced into the n-well 3nwp.

In the main surface of such a semiconductor substrate 1, for example, a shallow trench-buried type element isolation region (trench isolation) 4 is formed. That is, the element isolation region 4 is formed by embedding isolation insulating films 4b1 and 4b2 in isolation grooves 4a dug in the thickness direction of the semiconductor substrate 1.

The isolation insulating films 4b1 and 4b2 are made of, for example, silicon oxide. Note that this element isolation region 4
Is formed flat so that its height substantially matches the height of the main surface of the semiconductor substrate 1.

In this manufacturing process, a memory cell selecting MOSFET Q constituting a DRAM memory cell is formed on the p well 3pwm in the memory cell region. This memory cell selection MOS-FET Q
It has a pair of semiconductor regions 5a and 5b formed apart from each other over the well 3pwm, a gate insulating film 5i formed on the semiconductor substrate 1, and a gate electrode 5g formed thereon. . The memory cell selection MOS
The threshold voltage of the FET Q is, for example, 1 V or around it.

The semiconductor regions 5a and 5b are regions for forming the source / drain of the memory cell selecting MOS-FET Q. In this region, for example, arsenic as an n-type impurity is introduced. A memory cell selecting MOS is provided immediately below the gate electrode 5g between the semiconductor regions 5a and 5b.
The channel region of the FET Q is formed.

The gate electrode 5g is formed by a part of the word line WL. For example, the gate electrode 5g is formed by sequentially depositing an n-type low-resistance polysilicon film, a titanium nitride film and a tungsten film in order from the bottom.

The titanium nitride film in the gate electrode 5g prevents a silicide from being formed at a contact portion by a heat treatment during a manufacturing process when a tungsten film is directly stacked on a low-resistance polysilicon film. For the barrier metal film.

The barrier metal film is not limited to titanium nitride but can be variously modified. For example, tungsten nitride or the like may be used. This tungsten nitride has, for example, the following first to third excellent features.

First, tungsten nitride has high resistance to oxidation treatment. After patterning the gate electrode 5g and the like, the gate insulating film under the gate electrode 5g may be slightly scraped off. Therefore, a light oxidation process is performed to repair the scraping of the gate insulating film and the like after the patterning. Therefore, the barrier metal film is also preferably made of a material having high oxidation resistance.
In particular, in the case of a tungsten-based material, by controlling the atmosphere of light oxidation, a region where silicon is oxidized without oxidizing the tungsten-based metal can be widened. Second
In the case of tungsten nitride, the gate insulating film after light oxidation has a good withstand voltage. Third, in the case of tungsten nitride, the gate longitudinal resistance (resistance between metal and polysilicon)
Is small.

The tungsten film in the gate electrode 5g of the memory cell selecting MOS-FET Q has a function of reducing the wiring resistance. By providing this, the sheet resistance of the gate electrode 5g (ie, the word line WL) is reduced. 2
It can be reduced to about 2.5Ω / □. This is about 1/1 of the specific resistance of tungsten silicide of 15 to 10 μΩcm.
Can be 0.

Thus, the access speed of the DRAM can be improved. Further, since the number of memory cells that can be connected to one word line WL can be increased, the occupied area of the entire memory region can be reduced, and the size of the semiconductor chip can be reduced.

For example, in the first embodiment, 512 memory cells can be connected to the word line WL. This means that the size of the semiconductor chip can be reduced by about 6% as compared with the case where 256 memory cells can be connected to the word line WL. The effect of reducing the size is obtained. Therefore,
Since the number of semiconductor chips manufactured by one manufacturing process can be increased, cost reduction of the DRAM can be promoted. If the size of the semiconductor chip is not changed, the degree of element integration can be improved.

The gate insulating film 5i is made of, for example, silicon oxide, and has a thickness of, for example, about 7 nm. Further, the gate insulating film 5i may be formed by an oxynitride film (SiON film). Thus, the generation of interface states in the gate insulating film can be suppressed, and at the same time, electron traps in the gate insulating film can be reduced, so that the hot carrier resistance in the gate insulating film 5i can be improved. Becomes possible. Therefore, it is possible to improve the reliability of the extremely thin gate insulating film 5i.

As a method of oxynitriding the gate insulating film 5i, for example, when the gate insulating film 5i is formed by oxidation treatment, a high-temperature heat treatment is performed in an NH ₃ gas atmosphere or a NO ₂ gas atmosphere. A method of introducing nitrogen into the film 5i, a method of forming a gate insulating film 5i made of silicon oxide or the like, and a method of forming a nitride film on the upper surface thereof, a method of implanting nitrogen ions into the main surface of the semiconductor substrate, and then introducing the gate insulating film 5i. Or a method in which nitrogen is ion-implanted into a polysilicon film for forming a gate electrode, and then heat treatment is performed to deposit nitrogen on the gate insulating film.

On the gate electrode 5g of the memory cell selecting MOS-FET Q, that is, on the upper surface of the word line WL,
For example, a cap insulating film 6 made of silicon nitride is formed. Further, the cap insulating film 6, the gate electrode 5
g (word line WL) and adjacent word lines WL
An insulating film 7 made of, for example, silicon nitride is formed on the main surface of the semiconductor substrate 1 between them.

On the other hand, on the p well 3pwp in the peripheral circuit region (right side in FIG. 1), an n-channel type MOS-FE
TQn is formed. n-channel MOS ・ FE
TQn includes a pair of semiconductor regions 8a and 8b formed apart from each other above a p-well 3pWp and a semiconductor substrate 1
It has a gate insulating film 8i formed thereon and a gate electrode 8g formed thereon. In addition, this MOS
The threshold voltage of the FET Qn is, for example, about 0.1 V or around it.

The semiconductor regions 8a and 8b are regions for forming the source / drain of the n-channel type MOS FET Qn, and are provided between the semiconductor regions 8a and 8b immediately below the gate electrode 8g.・ FET
A channel region of Qn is formed.

The semiconductor regions 8a and 8b are LDD (Ligh
tly Doped Drain) structure. That is, the semiconductor regions 8a and 8b are respectively formed in the low concentration regions 8a1 and 8b1.
And high concentration regions 8a2 and 8b2. The low concentration regions 8a1 and 8b1 are formed on the channel region side, and the high concentration regions 8a2 and 8b2 are formed at positions separated from the channel region.

The low-concentration regions 8a1 and 8b1 are doped with, for example, an n-type impurity As. The high-concentration regions 8a2 and 8b2 are doped with, for example, n-type impurity As, but the impurity concentration is set higher than the impurity concentration in the low-concentration regions 8a1 and 8b1. Note that a silicide layer 8c made of, for example, titanium silicide is formed on the main surface of the semiconductor regions 8a and 8b.

The gate electrode 8g is formed by depositing, for example, an n-type low-resistance polysilicon film, a titanium nitride film and a tungsten film in order from the lower layer. 8 g of this gate electrode
Is a barrier metal film for preventing silicide from being formed at a contact portion by heat treatment during a manufacturing process when a tungsten film is directly stacked on a low-resistance polysilicon film. A tungsten nitride film may be used as the barrier metal.

The metal film such as a tungsten film in the gate electrode 8g has a function of reducing the wiring resistance. By providing this, the sheet resistance of the gate electrode 8g is reduced to about 2 to 2.5 Ω / □. Can be reduced to This makes it possible to improve the operation speed of the DRAM.

The gate insulating film 8i is made of, for example, silicon oxide, and has a thickness of the memory cell selecting MOS.
Like the gate insulating film 5i of the FET Q, the thickness is, for example, about 7 nm. Further, this gate insulating film 8i is formed as an oxynitride film (S
(iON film). This makes it possible to improve the hot carrier resistance of the extremely thin gate insulating film 8i as described above.

On the upper surface of the gate electrode 8g, a cap insulating film 6 made of, for example, silicon nitride is formed. The cap insulating film 6 and the gate electrode 8g
A sidewall 9 made of, for example, silicon nitride is formed on the side surface of.

The sidewalls 9 are mainly used for ion implantation for forming the low-concentration regions 8a1, 8b1 and the high-concentration regions 8a2, 8b2 of the n-channel MOSFET Qn on the semiconductor substrate 1. Used as a mask.

That is, after forming the gate electrode 8 g and before forming the side wall 9, impurities for forming the low concentration regions 8 a 1 and 8 b 1 are ion-implanted into the semiconductor substrate 1 using the gate electrode 8 g as a mask. Impurities for forming the high concentration regions 8a2 and 8b2 are ion-implanted into the semiconductor substrate 1 using the gate electrode 8g and the side wall 9 as a mask.

The n-well 3n in the peripheral circuit region
A p-channel type MOSFET Qp is formed on wp. The p-channel type MOSFET Qp is formed on a pair of semiconductor regions 10a and 10b formed above the n-well 3nWp and separated from each other, a gate insulating film 10i formed on the semiconductor substrate 1, and a gate insulating film 10i formed thereon. Gate electrode 10g. This MOS-FET
The threshold voltage at Qp is, for example, 0.1 V or around it.

The semiconductor regions 10a, 10b are regions for forming the source / drain of the p-channel type MOSFET Qp. The p-channel type MO is provided immediately below the gate electrode 10g between the semiconductor regions 10a, 10b.
A channel region of the S • FET Qp is formed.

The semiconductor regions 10a and 10b are LDD
(Lightly Doped Drain) structure. That is, the semiconductor regions 10a and 10b have low concentration regions 10a1 and 10b1 and high concentration regions 10a2 and 10b2, respectively. These low-concentration regions 10a1 and 10b1 are formed on the channel region side, and the high-concentration regions 10a2 and 10b1 are formed.
b2 is formed at a position separated from the channel region.

The low-concentration regions 10a1 and 10b1 are doped with, for example, p-type impurity boron. The high-concentration regions 10a2 and 10b2 are doped with, for example, a p-type impurity such as boron.
It is set higher than the impurity concentration in 1,10b1.
Note that a silicide layer 10c made of, for example, titanium silicide or the like is formed in an upper layer portion of the semiconductor regions 10a and 10b.

The gate electrode 10g is formed by depositing, for example, an n-type low-resistance polysilicon film, a titanium nitride film and a tungsten film in order from the bottom.

The titanium nitride film in the gate electrode 10g is for preventing silicide from being formed at the contact portion by heat treatment during the manufacturing process when a tungsten film is directly stacked on the low-resistance polysilicon film. Is a barrier metal film. A tungsten nitride film may be used as the barrier metal.

The metal film such as a tungsten film in the gate electrode 10g has a function of lowering the wiring resistance. By providing this, the sheet resistance of the gate electrode 10g is reduced to about 2 to 2.5 Ω / □. Can be reduced to This makes it possible to improve the operation speed of the DRAM.

The gate insulating film 10i is made of, for example, silicon oxide and has a thickness of the memory cell selecting MOS.
-Like the gate insulating film 5i of the FET Q, for example, 7 nm
It is about. Further, the gate insulating film 10i may be formed by an oxynitride film (SiON film). This allows
It is possible to improve the hot carrier resistance of the extremely thin gate insulating film 10i.

A cap insulating film 6 made of, for example, silicon nitride is formed on the upper surface of the gate electrode 10g. The cap insulating film 6 and the gate electrode 10
A side wall 9 made of, for example, silicon nitride or the like is formed on the side surface of g.

The sidewalls 9 are mainly used for ion implantation for forming the low-concentration regions 10a1, 10b1 and the high-concentration regions 10a2, 10b2 of the p-channel type MOSFET Qp on the semiconductor substrate 1. Used as a mask.

That is, after forming the gate electrode 10 g and before forming the sidewall 9, impurities for forming the low-concentration regions 10 a 1 and 10 b 1 are ion-implanted into the semiconductor substrate 1 using the gate electrode 10 g as a mask. Impurities for forming the high concentration regions 10a2 and 10b2 are ion-implanted into the semiconductor substrate 1 using the gate electrode 10g and the side wall 9 as a mask.

These n-channel type MOSFETs Q
A sense amplifier circuit, a column decoder circuit, a column driver circuit, a row decoder circuit, a row driver circuit, an I / O selector circuit, a data input buffer circuit, a data output buffer circuit, a power supply circuit, etc. of a DRAM by n- and p-channel MOSs. Is formed.

Such a memory cell selecting MOS-FE
Semiconductor integrated circuit elements such as TQ, p-channel type MOSFET Qp and n-channel type MOSFET Qn include interlayer insulating films 11 a to 11 a deposited on a semiconductor substrate 1.
1c.

The interlayer insulating films 11a to 11c are made of, for example, silicon oxide. Among them, the interlayer insulating film 11a is
For example, it is deposited by a SOG (Spin On Glass) film . The interlayer insulating films 11b and 11c are deposited by, for example, a plasma CVD method or the like. Then, the upper surface of the interlayer insulating film 11c is flattened so that the height in the memory region and the peripheral circuit region substantially match.

The interlayer insulating films 11a to 11a in the memory area
1c, connection holes 12a and 12b are formed in the insulating film 7 so that the semiconductor regions 5a and 5b are exposed. The size of the gate electrode 5g in the dimensions below the connection holes 12a and 12b
The dimension of the (word line WL) in the width direction is substantially defined by the portion of the insulating film 7 on the side surface of the adjacent gate electrode 5g (word line WL).

This is because the connection holes 12a and 12b are formed in a self-aligned manner by the insulating film 7 on the side surface of the gate electrode 5g (word line WL). That is, the connection holes 12a and 12b are formed in a state where the etching selectivity between the interlayer insulating films 11a to 11c and the insulating film 7 is increased.

In the exposure process for transferring the pattern of the connection holes 12a and 12b, the pattern of the connection holes 12a and 12b and the
Even if the plane position of the FET Qs relative to the active region is slightly shifted, part of the gate electrode 5g (word line WL) is not exposed from the connection holes 12a and 12b. Accordingly, since the alignment margin can be reduced, the size of the memory cell can be reduced.

Plugs 13a and 13b are embedded in the connection holes 12a and 12b, respectively. Plug 13
Reference characters a and 13b are made of, for example, low-resistance polysilicon containing n-type impurity phosphorus, and are electrically connected to the semiconductor regions 5a and 5b of the memory cell selecting MOS-FET Q, respectively. Note that a silicide film such as titanium silicide is formed on the upper surface of the plug 13b.

The interlayer insulating film 11d is formed on the interlayer insulating film 11c.
Has been deposited. The interlayer insulating film 11d is made of, for example, silicon oxide or the like, and is formed by, for example, a plasma CVD method or the like. The bit line BL and the first layer wiring 14 (14a to 14c) are formed on the interlayer insulating film 11d. This bit line BL and first layer wiring 1
4 has a width of, for example, about 0.1 μm and a thickness of, for example, 0.1 μm.
m.

The bit line BL is formed by depositing, for example, a titanium film, a titanium nitride film, and a tungsten film in this order from the bottom, and is electrically connected to the plug 13b through the connection hole 15 formed in the interlayer insulating film 11d. , Is electrically connected to the semiconductor region 5b of the memory cell selection MOSFET Q through the plug 13b.

The bit line BL extends in a direction crossing the extending direction of the word line WL. Therefore, the bit line BL is not normally shown in the cross section shown in FIG.
The bit line BL is shown for reasons such as showing the wiring layer where the bit line BL is arranged.

On the other hand, the first layer wiring 14 in the peripheral circuit area
Similarly to the bit line BL, for example, a titanium film, a titanium nitride film, and a tungsten film are sequentially deposited from the lower layer.
The constituent materials of the bit line BL and the first layer wiring 14 are not limited to those described above, and can be variously changed. For example, a single film of aluminum (Al) or a conductor film made of Al may be made of May be used as an alloy film or a single film of copper (Cu). Also, this bit line BL
Alternatively, the surface (the upper surface and the side surfaces) of the first layer wiring 14 may be covered with an insulating film made of, for example, silicon nitride.

The first layer wiring 14a is electrically connected to the semiconductor region 8a of the n-channel type MOSFET Qn through the connection hole 16 formed in the interlayer insulating films 11a to 11d. Further, the first layer wiring 14b is connected to the semiconductor region 8b of the n-channel type MOSFET Qn and the semiconductor region 1 of the p-channel type MOSFET Qp through the connection hole 16 in which the interlayer insulating films 11a to 11d are also drilled.
0a. Further, the first layer wiring 1
Reference numeral 4c is electrically connected to the semiconductor region 10b of the p-channel type MOSFET Qp through a connection hole 16 formed in the interlayer insulating films 11a to 11d.

On the upper surface of the interlayer insulating film 11d, interlayer insulating films (first insulating films) 11e to 11g are deposited in order from the lower layer, whereby the bit lines BL and the first layer wirings 14 are covered. I have. The interlayer insulating films 11e to 11g are
For example, it is made of silicon oxide or the like. Among them, the interlayer insulating film 11e is formed of, for example, an SOG film. The interlayer insulating films 11f and 11g are formed, for example, by plasma CV.
It is formed by the D method or the like. Then, the interlayer insulating film 1
The flattening process is performed so that the height of the upper surface of 1 g is substantially the same in the memory cell region and the peripheral circuit region.

First, for such a semiconductor substrate 1,
By performing the photolithography process and the dry etching process, as shown in FIG.
A connection hole (first connection hole) 17a for exposing a part of the first layer wiring 14b is formed in the holes 11g to 11g.

The depth of the connection hole 17a is, for example, 0.7 μm.
m, and the diameter is not particularly limited. For example, the gate processing length is about 1.5 times the gate processing length (0.2 to 0.2.
3 μm), preferably about 0.25 μm.

Subsequently, as shown in FIG.
A conductor film 18 is deposited on the upper surface of 1 g and in the connection hole 17a by a blanket CVD method or the like. That is, after a relatively thin conductor film is deposited by a sputtering method or the like, a relatively thick conductor film is deposited thereon by a CVD method or the like to form the conductor film 18. At this time, the connection hole 17a is completely buried with the conductor film 18 up to the upper portion. The thin conductor film is made of, for example, titanium nitride, and the thick conductor film is made of, for example, tungsten.
When the first layer wiring 14 exposed from the connection hole 17a is made of aluminum or polysilicon, a tungsten hexafluoride gas used for forming a thick conductor film by the CVD method reacts with aluminum or silicon to form a high-resistance three-fluoride gas. There is a problem that aluminum fluoride (AlF ₃ ) or highly volatile carbon tetrafluoride (CF ₄ ) is generated. The thin conductor film to be deposited before the deposition of the thick conductor film has a function of suppressing this. However, with the miniaturization (high aspect ratio) of the connection hole 17a, the thin conductor film is sufficiently deposited in the connection hole 17a. Because it may not be possible,
In some cases, the above-described problem becomes apparent. However, in the present embodiment, the first layer wiring 14 is made of tungsten (the connection hole 17).
a portion exposed from a), the above-described problem due to the reaction of the film forming gas does not occur. Therefore, the connection hole 17
Since the connection failure at a and the fluctuation and increase of the resistance can be suppressed,
It is possible to improve the yield and reliability of the semiconductor integrated circuit device.

Thereafter, the semiconductor substrate 1 is subjected to anisotropic dry etching or CMP (Chemical Mechanical Processing).
cal Polishing) process to make the interlayer insulating film 1
1 g of the conductive film 18 on the upper surface is removed, and the conductive film 18 is
By leaving the plug (first connection portion) 18a in the connection hole 17a as shown in FIG.
To form The plug 18a is electrically connected to the first layer wiring 14 in a state of being in direct contact therewith.

Since the connection hole 17a has a small diameter and is shallow, the aspect ratio can be reduced, and it is relatively easy to form the hole and fill it with the conductive film 18. Therefore, the plug 18a in the connection hole 17a and the first layer wiring 14b
Can be electrically connected well.

Next, a connection hole 19 is formed in the interlayer insulating films 11e to 11g in the memory cell region so that the upper surface of the plug 13a is exposed by photolithography and dry etching. A conductive film 20 is formed. This connection hole 1
Although the diameter of 9 is not particularly limited, it is, for example, about gate processing length to about 1.5 times (0.2 to 0.3 μm) the gate processing length, and preferably about 0.25 μm.

The plug 20 is formed by depositing a low-resistance polysilicon film doped with, for example, an n-type impurity (for example, P (phosphorus)) on the interlayer insulating film 11g and in the connection hole 19 by a CVD method or the like. The silicon film is formed by being etched back by the anisotropic dry etching method or the CMP method and left inside the connection hole 19.

However, in the first embodiment, after the plug 18a in the peripheral circuit area is formed, the plug 2a in the memory area is formed.
Although the case where 0 is formed has been described, the present invention is not limited to this, and may be reversed. That is, after the plug 20 in the memory area is formed, the plug 1 in the peripheral circuit area is formed.
8a may be formed.

Next, an insulating film (second insulating film) 21 made of, for example, silicon nitride having a thickness of about 100 nm is formed so as to cover the upper surface of the interlayer insulating film 11g, the exposed surface of the plug 18a, and the exposed surface of the plug 20. It is formed by a plasma CVD method or the like.

This insulating film 21 functions as an etching stopper when etching the silicon oxide film between the lower electrodes in the step of forming a storage electrode of the information storage capacitor element described later. Also, it functions so as to prevent the storage electrode of the information storage capacitor element from being collapsed. Further, the first embodiment
Functions as an etching stopper when the silicon oxide film on the plug 18a is removed by etching in the step of forming a connection hole that exposes the upper surface of the plug 18a.

Next, as shown in FIG. 5, an interlayer insulating film (third insulating film) 11h made of, for example, silicon oxide having a thickness of about 1.3 μm is formed on the insulating film 21 by using, for example, ozone (O _3). ) And tetraethoxysilane (TEOS) are deposited by a plasma CVD method or the like using a source gas, and then the interlayer insulating film 11h and the lower insulating film 21 are
A groove 22 that exposes the upper surface of the plug 20 is formed by photolithography and etching.

In forming the groove 22, an etching process is performed in a state where the etching selectivity between the silicon oxide film and the silicon nitride film is increased. That is, first, by performing an etching process such that the silicon oxide film is etched faster, the portion of the interlayer insulating film 11h exposed from the photoresist pattern is removed. At this time, since the lower insulating film 21 is made of silicon nitride or the like, it functions as an etching stopper. Subsequently, the insulating film 21 is removed by performing an etching process such that the silicon nitride is etched away faster. At this time, since the interlayer insulating film 11g under the insulating film 21 is made of silicon oxide or the like, it is not largely removed when the insulating film 21 is removed.

After the step of forming the groove 22, a conductive film made of low-resistance polysilicon doped with, for example, an n-type impurity (for example, P (phosphorus)) and having a thickness of about 60 nm is formed on the semiconductor substrate 1 by CVD. accumulate. This conductor film made of low-resistance polysilicon is used as a storage electrode material of an information storage capacitor.

Subsequently, a film thickness (for example, 2 μm) larger than the depth of the groove 22 is formed on the conductor film made of the low-resistance polysilicon.
m), an insulating film made of silicon oxide or the like is spin-coated, the insulating film is etched back, and furthermore, a conductive film made of low-resistance polysilicon on the interlayer insulating film 11h is etched back, thereby forming the groove 22. A conductor film made of low-resistance polysilicon is left inside (the inner wall and the bottom).

After that, the interlayer insulating film 11h in the peripheral circuit region
The insulating film inside the groove 22 and the interlayer insulating film 11h in the gap between the groove 22 are removed by wet etching using a photoresist film covering the mask as a mask to form the storage electrode (first electrode) 23a of the information storage capacitor. .

At this time, since the insulating film 21 made of silicon nitride or the like remains in the gap between the grooves 22, the upper portion of the lower interlayer insulating film 11g is not etched.

At this time, in the first embodiment, since the lower portion of the storage electrode 23a can be supported by the remaining insulating film 21, its fixing strength can be improved and its collapse can be prevented. It is possible to do.

Further, the interlayer insulating film 11h in the peripheral circuit region
Is arranged at one end at the boundary between the storage electrode 23a formed on the outermost side of the memory array and the peripheral circuit region. In this way, even if misalignment occurs at the end of the photoresist film, the groove 22 of the storage electrode 23a formed on the outermost side of the memory array is formed.
No insulating film remains in the inside, and the interlayer insulating film 11h in the peripheral circuit region is not etched.

Next, after the photoresist film is removed, the semiconductor substrate 1 is heat-treated at about 800 ° C. in an ammonia atmosphere to prevent oxidation of the low-resistance polysilicon forming the storage electrode 23a. After nitriding the surface of the storage electrode 23a made of silicon, the storage electrode 23a
An insulating film 23b made of, for example, tantalum oxide and having a thickness of about 20 nm is deposited on the upper part of a by CVD.

Subsequently, for example, 8
A heat treatment is performed at about 00 ° C. to activate the insulating film 23b made of tantalum oxide. This insulating film 23b is used as a capacitive insulating film material of the information storage capacitance element.

Thereafter, a conductor film made of, for example, titanium nitride having a thickness of about 150 nm is formed on the surface of the insulating film 23b by CV.
After the deposition by the D method and the sputtering method, the conductor film and the insulating film 23b are patterned by a photolithography technique and a dry etching technique.

Thus, the upper electrode (second electrode) 23
c, an insulation film 23b made of tantalum oxide or the like and a storage electrode 23a made of low-resistance polysilicon, for example, a crown-shaped information storage capacitance element C is formed. In this manner, a DRAM memory cell composed of the memory cell selecting MOS-FET Q and the information storage capacitor C connected in series thereto is completed.

Next, an interlayer insulating film (third insulating film) 1 made of, for example, silicon oxide having a thickness of about 100 nm is formed on the interlayer insulating film 11h so as to cover the information storage capacitive element C.
1i is deposited. The interlayer insulating film 11i is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Subsequently, after a photoresist pattern 24a for forming a connection hole in the peripheral circuit region is formed on the interlayer insulating film 11i, the photoresist pattern 24a is used as a mask to expose the interlayer insulating films 11i and 11h and the insulating film. By removing the film 21 by etching, a connection hole (second connection hole) 17b that exposes the upper portion of the plug 18a is formed. The diameter of the connection hole 17b is not particularly limited,
For example, the gate processing length × 1.5 to the gate processing length × 3 (0.3 to
0.6) μm, preferably about 0.4 μm, which is larger than the diameter of the connection hole 17a. The depth is not particularly limited, but is about 1.8 μm.

In forming the connection hole 17b, an etching process is performed in a state where the etching selectivity between the silicon oxide film and the silicon nitride film is increased. That is, first, the silicon oxide film is etched so as to be etched away more quickly, so that the interlayer insulating films 11i and 11h exposed from the photoresist pattern 24a.
Remove the part. At this time, since the lower insulating film 21 is made of silicon nitride or the like, it functions as an etching stopper. Subsequently, the insulating film 21 is subjected to an etching process so that the silicon nitride is etched away faster.
Remove the part. At this time, the interlayer insulating film 11g under the insulating film 21 is made of silicon oxide or the like.
1 is not significantly removed.

After the connection hole 17b is formed in the peripheral circuit region, a conductor film 25 is formed on the upper surface of the interlayer insulating film 11i and in the connection hole 17b with a blanket C, as shown in FIG.
It is applied by a VD method or the like.

That is, after a thin conductor film made of, for example, a titanium nitride film is deposited by a sputtering method or the like, a thick conductor film made of a tungsten film is deposited thereon by a CVD method or the like to form a conductor film 25. . At this time, the connection hole 17b is completely filled with the conductor film 25 up to the upper portion.

Thereafter, the semiconductor substrate 1 is subjected to an anisotropic dry etching treatment, whereby the interlayer insulating film 11 is formed.
By removing the conductor film 25 on the top surface i and leaving the conductor film 25 in the connection hole 17b, as shown in FIG.
A plug (second connection portion) 25a is formed in the connection hole 17b. The plug 25a is electrically connected to the plug 18a in a state of being in direct contact with the plug 18a.

Next, after a conductor film made of, for example, titanium nitride is deposited on the interlayer insulating film 11i by a sputtering method or the like, an aluminum alloy such as aluminum (Al) or an Al—Si—Cu alloy is sputtered thereon. Then, a conductor film made of, for example, titanium nitride or the like is deposited thereon by a sputtering method or the like.

Subsequently, the laminated conductor film is patterned by a photolithography technique and a dry etching technique, so that the second layer wiring 2 is formed as shown in FIG.
6 is formed. The width of the second layer wiring 26 is not particularly limited, but is, for example, about 0.7 μm, and the thickness is not particularly limited, but is, for example, about 0.8 μm.

Thereafter, the interlayer insulating films 11j, 11k, 11m made of, for example, silicon oxide are formed on the interlayer insulating film 11i.
Is deposited by a CVD method or the like, and a third-layer wiring is formed thereon in the same manner as the second-layer wiring 26.

Thereafter, a surface protective film made of, for example, a silicon oxide film alone or a laminated film of a silicon nitride film stacked on the silicon oxide film is deposited by CVD or the like so as to cover the third layer wiring. To manufacture a DRAM.

As described above, in the first embodiment, D
In the peripheral circuit area of the RAM, the connection holes 17a and 17b for electrically connecting the second layer wiring 26 and the first layer wiring 14 are formed twice, and the respective connection holes 17a and 17b are formed.
After piercing of 17b, a conductor film is embedded and plugs 18a and 25 are buried.
a. Accordingly, in the first embodiment, the first layer wiring 14 and the second layer wiring 26 are stacked by the two plugs 18a and 25a stacked in a state of being directly contacted with each other in the height direction between the wiring layers. The structure is such that they are electrically connected to each other.

By the way, in the peripheral circuit region of the DRAM, the connection hole for connecting the first layer wiring 14 and the second layer wiring 26 is formed by a single process, that is, in the second circuit,
Prior to the step of depositing a conductor film for forming a layer wiring, the first
In the case of a technique in which one connection hole is formed in the insulating film between the layer wiring 14 and the second layer wiring 26 so that a part of the first layer wiring 14 is exposed, the aspect ratio of the connection hole becomes large. ,
Drilling and embedding with a conductor film becomes difficult.

In the memory cell region, the first layer wiring 1
The information storage capacitance element C is provided between the fourth and second layer wirings 26, but the height thereof tends to be high from the viewpoint of securing a large capacitance with a small occupation area. Therefore, as the information storage capacitor C becomes higher, the insulating film between the first layer wiring 14 and the second layer wiring 26 in the peripheral circuit region becomes thicker, so that the connection hole becomes deeper and the aspect ratio becomes larger. Become. Further, in the case of the technique of drilling the connection hole at one time, the hole diameter must be set in accordance with the fine first-layer wiring 14, so that the hole diameter has to be fine, and the aspect ratio is large. Become. As a result, it becomes difficult to embed the conductor film in the connection hole,
Insufficient connection at the connection hole and fluctuation / increase in resistance occur, causing DRA
The yield and reliability of M may decrease.

Further, when the connection hole is formed once,
It is necessary to perform over-etching in consideration of the variation in the thickness of the interlayer insulating films 11h, 11g, 11f, and 11e within the wafer. However, due to this over-etching,
The connection hole reaches the surface of the semiconductor substrate, and there is a risk that the second layer wiring and the semiconductor substrate may be short-circuited.

On the other hand, in the first embodiment,
First layer wiring 14 and second layer wiring 26 in the peripheral circuit region
The connection holes for connecting the connection holes 17a and 17b are formed by dividing the connection holes 17a and 17b twice, and each of the connection holes is filled with a conductor film after each of the connection holes 17a and 17b. Since the embedding can be facilitated, the reliability of the connection between the first layer wiring 14 and the second layer wiring 26 can be improved, and the yield and reliability of the DRAM can be improved. I have.

In particular, in the first embodiment, the connection hole 17b opened immediately before the step of depositing the conductor film for forming the second layer wiring can be made shallower and its diameter can be made larger. Therefore, the aspect ratio can be reduced.

This is because the connection hole 17b is connected to the plug 18a.
Hole may be drilled to a depth at which the upper part of the plug 18a is exposed. Therefore, the depth is set to be greater than the height of the plug 18a (or the interlayer insulating film) as compared with the case of drilling a connection hole at which a part of the first layer wiring 14 is exposed. This is because the thickness can be reduced by the thickness of 11e to 11g). That is, the plug 18a in the connection hole 17a here has a function of making the connection hole 17b shallow and reducing its aspect ratio.

In the first embodiment, as shown in FIGS. 9 and 10, the diameter of connection hole 17b opened at a stage immediately before the step of depositing the conductor film for forming the second layer wiring is increased. As a result, the aspect ratio can be reduced. This is for the following reason, for example.

In the case of the technique of forming a connection hole such that a part of the first-layer wiring 14 is exposed in the peripheral circuit region, the diameter of the connection hole is determined by the width of the fine first-layer wiring 14 connected to the element, the first width.
Planar alignment with the layer wiring 14 and the adjacent first
Due to restrictions such as the distance between the layer wirings 14, the size cannot be made too large.

On the other hand, in the first embodiment, the connection hole 17b in the peripheral circuit region may be formed so that the upper portion of the plug 18a is exposed. Of the plug 18a. However, since the restriction is looser than the restriction from the first layer wiring 14, the diameter of the connection hole 17b can be set relatively large. Here, the plug 18a in the connection hole 17a has a restriction relaxing function so that the diameter of the connection hole 17b can be set large.

In FIGS. 9 and 10, the first layer wiring and the second layer wiring are shown.
The width of the first layer wiring 14 is changed to the width of the connection hole 17 as in the case of the normal setting in which the connection hole for connecting to the layer wiring is formed once.
The figure shows a case where the setting is made in consideration of a margin (0.15 μm) for a and 17b. That is, the connection holes 17a,
When the connection hole 17a is located at the center of the wiring, the connection holes 17a, 1
The wiring width is set so that a matching margin of 0.15 μm is provided on both sides of 7b. However, in the present embodiment, the connection hole 17a which needs to consider the misalignment with the first layer wiring 14 in the plane is formed in a layer lower than the formation layer of the information storage capacitor C and the first layer wiring 14 is formed. , The amount of planar misalignment generated between the connection hole 17a and the first-layer wiring 14 can be made relatively small, and without considering the planar misalignment. The width of the first layer wiring 14 can be set. That is, the first layer wiring 14
Is not restricted by the connection hole. The width of the first layer wiring 14 is not widened as a whole, and the first layer wiring 14
It is not necessary to provide a wide pattern in a part (where the connection holes 17a are arranged). Therefore, the width of the first layer wiring 14 can be reduced, and the first layer wiring 14 can be arranged at a high density. For example, the width of the first layer wiring 14 to which the connection hole 17a is connected can be made equal to the diameter of the connection hole 17a. For this reason, size reduction of the semiconductor chip can be promoted.

In the first embodiment, the following effects can be obtained.

(1) First in the peripheral circuit area of the DRAM
The connection holes for electrically connecting the layer wiring 14 and the second layer wiring 26 are divided into two stages of connection holes 17a and 17b, and plugs 18a and 25a are buried in each of them to form holes for the connection holes 17a and 17b. Embedding of the conductor film can be facilitated.

(2) By making the diameter of the connection hole 17b larger than the diameter of the connection hole 17a, the alignment accuracy in the photolithography step for forming the connection hole 17b can be eased. Further, it is possible to easily perform a drilling process in an etching process for forming the connection hole 17b. Furthermore, it is possible to easily and favorably embed the conductor film in the connection hole 17b.

(3) According to the above (1) or (2), the connection hole 1 for electrically connecting the first layer wiring 14 and the second layer wiring 26 is formed.
Since the conduction failure at 7a and 17b can be reduced, the yield and reliability of the DRAM can be improved.

(4) According to the above (1), when setting the height of the cylindrical information storage capacitance element C, it is possible to ease the restrictions imposed by the connection holes 17a and 17b formed in the peripheral circuit area. Thus, the information storage capacitor C can be made higher. Therefore, it is possible to increase the capacity that contributes to information storage without increasing the area occupied by the information storage capacitor element C and without newly introducing a sophisticated and complicated process technology.

(5) According to the above (4), the refresh characteristics of the DRAM and the reliability of the read / write operation can be improved without increasing the area of the memory cell region.

(Embodiment 2) FIGS. 11 to 18 are cross-sectional views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the second embodiment, for example, 256
A case where the technical idea of the present invention is applied to an M-DRAM will be described.

First, the interlayer insulating films 11d-1d shown in FIG.
In 1g, as shown in FIG. 11, a connection hole 19 exposing the upper surface of the plug 13a is formed by photolithography and dry etching.

Subsequently, a conductor film made of, for example, low-resistance polysilicon is deposited on the interlayer insulating film 11g and in the connection hole 19 by the CVD method, and then the conductor film is removed by an etch-back method, a CMP method, or the like. Also in this case, as in the first embodiment, the plug 20 is formed by leaving the conductor film only in the connection hole 19 and not on the upper surface of the interlayer insulating film 11g.

Thereafter, the interlayer insulating film 11g and the plug 2
After an insulating film (second insulating film) 21a made of, for example, silicon nitride or the like is deposited by a CVD method or the like so as to cover the upper surface of the O.sub.0, an interlayer insulating film (a second insulating film) made of, for example, silicon oxide or the like is formed thereon. 4h) is deposited by a CVD method or the like.

Next, as shown in FIG. 12, interlayer insulating films 11e to 11g, insulating film 21a and interlayer insulating film 11h
1 shows a connection hole 1 in which a part of the first layer wiring 14b is exposed.
7a is perforated by a photolithography technique and a dry etching technique. The diameter of the connection hole 17a is not particularly limited, but is, for example, a gate processing length to a gate processing length × 1.5 μm, and preferably about 0.25 μm. Also,
The depth is not particularly limited, but is, for example, about 1.2 μm.

Subsequently, a conductor film 18 is deposited on the upper surface of the interlayer insulating film 11h1 and in the connection holes 17a by a blanket CVD method or the like. That is, for example, after a thin conductor film made of a titanium nitride film is deposited by a sputtering method or the like, a thick conductor film made of a tungsten film is
The conductive film 18 is formed by being applied by the D method or the like.
At this time, the connection hole 17a is completely covered with the conductive film 18
To be embedded.

Thereafter, the conductor film 18 on the upper surface of the interlayer insulating film 11h1 is removed by subjecting the semiconductor substrate 1 to anisotropic dry etching or CMP to leave the conductor film 18 only in the connection hole 17a. As a result, as shown in FIG. 13, a plug (first connection portion) 18a is formed in the connection hole 17a.

Next, an insulating film (fifth insulating film) 21b made of, for example, silicon nitride or the like is deposited by CVD or the like so as to cover the upper surfaces of the interlayer insulating film 11h1 and the plug 18a. For example, an interlayer insulating film (sixth insulating film) 11h2 made of silicon oxide or the like is formed by CVD.
It is applied by a method or the like.

Subsequently, as shown in FIG. 14, the interlayer insulating films 11h1 and 11h2 and the insulating films 21a and 21b are
A groove 22 that exposes the upper surface of the plug 20 is formed by photolithography and etching.

In forming the groove 22, the interlayer insulating film 1
In the case where 1h1 is removed by etching, an etching process is performed in a state where the etching selectivity between the silicon oxide film and the silicon nitride film is increased.

That is, first, an etching treatment is performed so that the silicon oxide film is etched and removed faster, thereby removing the portion of the interlayer insulating film 11h1 exposed from the photoresist pattern. At this time, the lower insulating film 2
Since 1a is made of silicon nitride or the like, it functions as an etching stopper.

Subsequently, the insulating film 21a is removed by performing an etching process such that the silicon nitride is etched away more quickly. At this time, the interlayer insulating film 11g underlying the insulating film 21a is made of silicon oxide or the like.
When the insulating film 21a is removed, it is not significantly removed.

After the step of forming the groove 22, a conductive film made of low-resistance polysilicon doped with, for example, an n-type impurity (for example, P (phosphorus)) and having a thickness of about 60 nm is formed on the semiconductor substrate 1 by the CVD method. accumulate. This conductor film made of low-resistance polysilicon is used as a storage electrode material of an information storage capacitor.

Subsequently, a film thickness (for example, 2 μm) larger than the depth of the groove 22 is formed on the conductive film made of the low-resistance polysilicon.
m), an insulating film made of silicon oxide or the like is spin-coated, the insulating film is etched back, and a conductive film made of low-resistance polysilicon on the interlayer insulating film 11h2 is etched back. A conductor film made of low-resistance polysilicon is left inside (the inner wall and the bottom).

Thereafter, the interlayer insulating film 11h in the peripheral circuit region
Using the photoresist film covering 1 as a mask, the insulating film inside the groove 22 and the interlayer insulating film 11h2 in the gap between the grooves 22 are removed by wet etching to form the storage electrode 23a of the information storage capacitor.

At this time, since the insulating film 21b made of silicon nitride or the like remains in the gap between the grooves 22, the upper portion of the interlayer insulating film 11h1 below it is not etched. The interlayer insulating film 11h1 and the insulating film 21b have a function of preventing the storage electrode 23a from falling down. In this case, the insulating film 21b and the interlayer insulating film 11h
By the thickness of 1, the ability to prevent the storage electrode 23a from collapsing can be improved as compared with the case of the first embodiment.

The interlayer insulating film 11h2 in the peripheral circuit region
Is arranged at one end at the boundary between the storage electrode 23a formed on the outermost side of the memory array and the peripheral circuit region. In this way, even if misalignment occurs at the end of the photoresist film, the groove 22 of the storage electrode 23a formed on the outermost side of the memory array is formed.
The insulating film does not remain inside the semiconductor device and the interlayer insulating film 11h2 in the peripheral circuit region is not etched.

Next, as in the first embodiment,
Upper electrode 23c and insulating film 23 made of tantalum oxide or the like
For example, a cylindrical information storage capacitance element C composed of b and a storage electrode 23a made of low-resistance polysilicon is formed. As a result, a DRAM memory cell composed of the memory cell selection MOS-FET Q and the information storage capacitance element C connected in series thereto is completed.

Subsequently, an interlayer insulating film (seventh insulating film) made of, for example, silicon oxide having a thickness of about 100 nm is formed on the interlayer insulating film 11h2 so as to cover the information storage capacitive element C.
11i is deposited in the same manner as in the first embodiment.

Thereafter, a photoresist pattern for forming a connection hole in the peripheral circuit region is formed on the interlayer insulating film 11i, and the photoresist pattern is used as a mask to expose the interlayer insulating films 11i and 11h2 and the insulating film 21b. Is removed by etching to form a connection hole 17b such that the upper portion of the plug 18a is exposed, as shown in FIG.

The diameter of the connection hole 17b is, for example, about gate processing length (1.5 to 3.0 times) μm, preferably 0.4 μm.
And larger than the diameter of the connection hole 17a described above. Further, in the first embodiment, since the upper portion of the plug 18a is located at an intermediate position of the height of the information storage capacitive element C, the depth of the connection hole 17b may be made shallower than in the case of the first embodiment. it can. Therefore, it is possible to make the connection holes 17b easier to drill than in the first embodiment. The depth is not particularly limited, but is, for example, about 1.3 μm.

In forming the connection hole 17b, an etching process is performed in a state where the etching selectivity between the silicon oxide film and the silicon nitride film is increased. That is, first, the portions of the interlayer insulating films 11i and 11h2 exposed from the photoresist pattern are removed by performing an etching process so that the silicon oxide film is etched away faster. At this time, since the lower insulating film 21b is made of silicon nitride or the like, it functions as an etching stopper.
Subsequently, the insulating film 21 is removed by performing an etching process such that the silicon nitride is etched away faster. At this time, since the interlayer insulating film 11h1 under the insulating film 21b is made of silicon oxide or the like, the insulating film 2h
There is no significant removal when removing 1b.

After the connection holes 17b are formed in the peripheral circuit region, as shown in FIG. 16, the upper surface of the interlayer insulating film 11i and the connection holes 17b are formed in the same manner as in the first embodiment.
A conductive film 25 is adhered inside.

Subsequently, the semiconductor substrate 1 is subjected to an anisotropic dry etching treatment, whereby the interlayer insulating film 11 is formed.
By removing the conductor film 25 on the top surface i and leaving the conductor film 25 in the connection hole 17b, a plug (second connection portion) 25a is formed in the connection hole 17b as shown in FIG. I do.

In the second embodiment, the depth of the connection hole 17b is shallower than that in the first embodiment, so that it is easier to embed the conductive film than in the first embodiment.
As described above, also in the second embodiment, in the peripheral circuit region, the plug 25a is stacked on the plug 18a in direct contact with each other and is electrically connected to each other.

Thereafter, as shown in FIG. 18, after forming the second layer wiring 26 and depositing an interlayer insulating film made of, for example, silicon oxide on the interlayer insulating film 11i as in the first embodiment. A third-layer wiring is formed thereon in the same manner as the above-mentioned second-layer wiring 26, and is further nitrided on the silicon oxide film alone or on the silicon oxide film so as to cover the third-layer wiring. A DRAM is manufactured by depositing a surface protection film composed of a stacked film in which silicon films are stacked.

In the second embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

(1) Since the storage electrode 23a is supported by the interlayer insulating film 11h1 and the insulating films 21a and 21b when forming the information storage capacitive element C, the ability of the storage electrode 23a to prevent collapse can be improved. Becomes

(2) By setting the height of the uppermost portion of the plug 18a at a position halfway of the height of the information storage capacitive element C,
Since the connection hole 17b can be made shallower than in the case of the first embodiment, the aspect ratio can be made smaller. Therefore, it is possible to further easily form the connection hole 17b and bury the connection hole 17b with the conductive film.

(Embodiment 3) FIGS. 19 to 25 are cross-sectional views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the third embodiment, for example, 256
A case where the technical idea of the present invention is applied to an M-DRAM will be described.

First, the interlayer insulating films 11d-1d shown in FIG.
1g, as shown in FIG. 19, a connection hole 19 where the upper surface of the plug 13a is exposed and a connection hole 17a where a part of the first layer wiring 14b is exposed by photolithography and dry etching. .

That is, in the third embodiment, the connection hole 19 in the memory cell region and the connection hole 17 in the peripheral circuit region are provided.
and a at the same time. Thus, a series of photolithography processes of resist application, exposure, and development can be reduced by one time, so that the manufacturing process can be simplified. Further, since the number of photolithography steps can be reduced, the adhesion rate of foreign substances can be reduced, and the yield and reliability of the DRAM can be improved.

In this case, the diameter of the connection hole 19 is not particularly limited, but is, for example, about 0.2 μm, and the depth is not particularly limited, but is, for example, about 0.8 μm. Also, the diameter of the connection hole 17a in this case is not particularly limited,
For example, about 0.25 μm, the depth is not particularly limited,
For example, it is about 0.7 μm.

Subsequently, as shown in FIG. 20, after a conductive film 27 made of, for example, titanium nitride is deposited on the interlayer insulating film 11g and in the connection holes 17a and 19 by the CVD method, the conductive film 27 is etched. It is cut by the back method or the CMP method.

In this case, the conductive film 27 is
a, 19, but not on the upper surface of the interlayer insulating film 11g. Thereby, as shown in FIG. 21, the plug 27a is formed in the connection hole 19 and the plug 27b is formed in the connection hole 17a.

That is, in the third embodiment, when forming the plug 27a for the information storage capacitor in the memory cell area, the plug 27b in the peripheral circuit area is also formed at the same time. As a result, a series of processes such as deposition of the conductive film and etch back can be reduced by one time.
The number of DRAM manufacturing steps can be reduced and simplified.

However, the conductor film 27 for forming the plugs 27a and 27b is not limited to titanium nitride, and can be variously modified. For example, a laminated film in which tungsten is deposited on titanium nitride may be used. . In this case, the titanium nitride film is formed by, for example, a sputtering ring method,
The tungsten film may be formed by, for example, a CVD method,
Both may be formed by the CVD method.

Thereafter, the interlayer insulating film 11g and the plug 2
After an insulating film 21 made of, for example, silicon nitride or the like is applied by CVD or the like so as to cover the upper surfaces of 7a and 27b, an interlayer insulating film made of, for example, silicon oxide or the like is formed on the upper surface as shown in FIG. 11h is deposited by a CVD method or the like.

Next, in the same manner as in the first embodiment,
Upper electrode 23c and insulating film 23 made of tantalum oxide or the like
and a storage electrode 23a, for example, a cylindrical information storage capacitor C is formed. As a result, a DRAM memory cell composed of the memory cell selection MOS-FET Q and the information storage capacitance element C connected in series thereto is completed.

When the plug 27a is made of titanium nitride, the storage electrode 23a is preferably made of, for example, a polysilicon film, tungsten, or tungsten nitride. When the plug 27a is a stacked film of titanium nitride and tungsten, the storage electrode 23a may be made of, for example, tungsten or tungsten nitride.

Subsequently, an interlayer insulating film 11i made of, for example, silicon oxide having a thickness of about 100 nm is deposited on the interlayer insulating film 11h in the same manner as in the first embodiment so as to cover the information storage capacitive element C. .

Thereafter, a photoresist pattern 24a for forming a connection hole in the peripheral circuit region is formed on the interlayer insulating film 11i, and the photoresist pattern 24a is used as a mask to expose the interlayer insulating films 11i and 11h and the insulating film. By etching away the 21, a connection hole 17 b exposing the upper portion of the plug 27 b is formed in the same manner as in the first embodiment.

The diameter of the connection hole 17b is, for example, about 1.5 to 3.0 times the gate processing length, preferably about 0.4 μm, and is larger than the diameter of the connection hole 17a. The depth is not particularly limited, but is, for example, 1.8 μm
It is about.

After the connection holes 17b are formed in the peripheral circuit region, the upper surface of the interlayer insulating film 11i and the connection holes 17b are formed in the same manner as in the first embodiment, as shown in FIG.
The conductor film 25 is adhered to the inside, and the conductor film 25 on the upper surface of the interlayer insulating film 11i is removed by subjecting the semiconductor substrate 1 to anisotropic dry etching.
24B, the conductor film 25 in FIG.
As shown in FIG. 7, a plug 25a is formed in the connection hole 17b. Thus, also in the third embodiment, in the peripheral circuit region, the plug 25a is stacked on the plug 27b in direct contact with the plug 27b and is electrically connected to each other.

Then, as shown in FIG. 25, after forming the second layer wiring 26 and depositing an interlayer insulating film made of, for example, silicon oxide on the interlayer insulating film 11i, as in the first embodiment. A third-layer wiring is formed thereon in the same manner as the above-mentioned second-layer wiring 26, and is further nitrided on the silicon oxide film alone or on the silicon oxide film so as to cover the third-layer wiring. A DRAM is manufactured by depositing a surface protection film composed of a stacked film in which silicon films are stacked.

In the third embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

(1) The connection holes 17a in the peripheral circuit area are formed at the same time as the step of forming the connection holes 19 in the memory cell area, and the connection holes 19 and 17a are simultaneously buried, and plugs 27a and 27b are simultaneously formed in the respective holes. By doing so, the number of DRAM manufacturing steps can be significantly reduced, and the DRAM manufacturing steps can be simplified.

(2) The connection hole 17a in the peripheral circuit region is formed at the same time as the step of forming the connection hole 19 in the memory cell region, and the connection holes 19 and 17a are buried at the same time, and the plugs 27a and 27b are simultaneously formed in the respective holes. By doing so, it is possible to reduce the rate of occurrence of foreign substances generated during the manufacturing process of the DRAM, so that it is possible to improve the yield and reliability of the DRAM.

(Embodiment 4) FIGS. 26 to 28 are cross-sectional views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the fourth embodiment, for example, 256
A case where the technical idea of the present invention is applied to an M-DRAM will be described. In the fourth embodiment, the same steps as those of the first embodiment described with reference to FIGS.
After the plug 18a is formed as shown in FIG.
On 1 g, an insulating film 21 made of, for example, a silicon nitride film having a thickness of about 100 nm is formed in the same manner as in the first embodiment and the like. The difference from FIG. 4 is that the connection hole 19 of the memory cell is formed after the insulating film 21 is applied. And
The plug 2 is inserted into the connection hole 19 in the same manner as in the first embodiment.
0 is formed. Although the diameter of the connection hole 19 is not particularly limited, for example, the gate processing length to the gate processing length × 1.5 times μ
m, preferably about 0.25 μm. The order of forming the plugs 18a and 19 may be reversed.

Thereafter, as shown in FIG. 27, interlayer insulating film 11h made of, for example, silicon oxide or the like is formed so as to cover the upper surfaces of interlayer insulating film 11g and plugs 27a and 27b.
Is deposited by a CVD method or the like, and in the same manner as in the first embodiment, for example, a cylindrical information storage device composed of an upper electrode 23c, an insulating film 23b made of tantalum oxide or the like, and a storage electrode 23a. The capacitor C is formed. As a result, the DRA composed of the memory cell selecting MOS-FET Q and the information storage capacitive element C connected in series thereto
M memory cells are completed.

After that, in the same manner as in the first embodiment and the like, after forming an interlayer insulating film 11i and a photoresist pattern 24a for forming connection holes in the peripheral circuit region in this order from the lower layer on the interlayer insulating film 11h. By using this as a mask, the interlayer insulating films 11i and 11h and the insulating film 21 exposed from this portion are removed by etching, whereby the plug 1 is removed.
A connection hole 17b that exposes the upper portion of 8a is formed in the same manner as in the first embodiment.

Thereafter, a conductor film is buried in the connection hole 17b in the same manner as in the first embodiment, and a plug 25a is formed as shown in FIG. Hereinafter, the first embodiment will be described.
Therefore, the description is omitted.

In the fourth embodiment, the same effects as in the first embodiment can be obtained.

(Embodiment 5) FIGS. 29 and 32 are plan views of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIGS. 30 and 31 show one of the semiconductor integrated circuit devices of FIG. It is the principal part perspective view which fractured | ruptured the part.

In the fifth embodiment, FIGS.
As shown in FIG. 0 and FIG. 31, the diameter of the upper connection hole 17b is larger than the diameter of each connection hole 17a so as to encompass the two lower connection holes 17a, and One plug 25a is configured to be electrically connected to the plug 18a in the two connection holes 17a arranged in parallel in the lower stage in a state of being directly in contact with the plug 18a. That is, it is as follows.

The lower connection hole 17a and the upper connection hole 1
7b is a plan view of the first layer wiring 14 and the second layer wiring 26.
And is arranged in the intersection area. Of these, the lower two connection holes 17a are formed, for example, in a planar circular shape, and
They are arranged in parallel along the longitudinal direction of the layer wiring 14.
The plug 18a in the connection hole 17a is
And are electrically connected in direct contact with the However, the connection hole 17a is formed along the width direction of the first layer wiring 14 by two.
They may be arranged in parallel. That is, they are arranged along a direction perpendicular to the direction of the current flowing through the two fine connection holes 17a. As a result, the current flowing through the fine connection holes 17a can be dispersed, so that the electromigration resistance in the connection holes 17a and 17b can be improved. Further, the number of connection holes 17a is not limited to two.

On the other hand, the upper connection hole 17b is formed, for example, in the same plane circular shape as the lower connection hole 17a, but has a diameter larger than the diameter of the lower connection hole 17a. It is formed in a size including the connection hole 17a.

The plug 25a in the upper connection hole 17b is
The lower part is a plug 18a in the lower two connection holes 17a.
And is electrically connected to the second layer wiring 26 at the upper portion thereof. Thus, in the fifth embodiment, one plug 25a has two plugs.
By electrically connecting the plugs 18a, the resistance of the plugs 18a and 25a can be reduced. However, the planar shape of the connection hole 17b is not limited to a circular shape, but can be variously changed. For example, as shown in FIG. 32, an elliptical shape may be used. Also in this case, the two lower connection holes 17 are provided in the region indicating the upper connection hole 17b.
An area indicated by a is included.

According to the fifth embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

(1) In the connection holes 17a and 17b for electrically connecting the first layer wiring 14 and the second layer wiring 26, a plurality of connection holes 17a are arranged in parallel, so that the plug 25a and the first Since the resistance with the layer wiring 14b can be reduced, the overall wiring resistance can be reduced.

(2) By making the planar size of the connection hole 17b large enough to cover the two connection holes 17a in a plane, it is easy to form the connection hole 17b and embed it in the conductive film. Becomes possible.

(Embodiment 6) FIGS. 33 to 36 are fragmentary cross-sectional views of a semiconductor integrated circuit device according to still another embodiment of the present invention during a manufacturing step.

In the sixth embodiment, the present invention is applied to, for example, DR.
FIG. 33 is a sectional view of a main part during a manufacturing process applied to a method of manufacturing an AM. In the drawing, those having the same reference numerals as those of the first embodiment and the like are formed of the same material as those described in the first embodiment and the like. The total thickness of the interlayer insulating films 11e to 11g is, for example, about 0.4 μm,
The thickness of the insulating film 21 is, for example, about 0.1 μm, and the thickness of the interlayer insulating film 11 h is, for example, about 1.3 μm.
The thickness of i is, for example, about 0.6 μm (therefore, the total thickness of the interlayer insulating films 11 h and 11 i is, for example, about 1.9 μm). The insulating film 21 is used as an etching stopper when digging a groove when the storage electrode 23a of the information storage capacitor C is formed, as in the first embodiment.

First, in the sixth embodiment, after the interlayer insulating film 11i is formed in the same manner as in the first embodiment and the like,
A photoresist film 24b is formed thereon. The photoresist film 24b has a connection hole for a wiring layer connecting the first layer wiring and the second layer wiring, and the information storage capacitor C
Is a mask pattern for drilling a connection hole for extracting an electrode for extracting the plate electrode 23c of FIG. 1A, and has a plane circular opening where a part of the plane of the plate electrode 23c and the first layer wiring 14 is exposed. ing.

Subsequently, using the photoresist film 24b as an etching mask, the silicon oxide film is more easily etched and removed than the silicon nitride film in a state where the etching selectivity between the silicon oxide film and the silicon nitride film is relatively increased. By performing the etching process under the conditions, the interlayer insulating film 11i exposed from the photoresist film 24b,
11h is removed, and connection holes (first holes) 17c1 and 17d1 are formed in the peripheral circuit region of the DRAM.

The connection hole 17c1 is a hole for connecting between wiring layers, and the insulating film (second insulating film) 21 is exposed from the bottom surface thereof. The insulating film 21 in the connection hole 17c1
Functions as an etching stopper. In this etching process, for example, an etching process equivalent to 3.0 μm in terms of a silicon oxide film is performed under the condition that the selectivity to the silicon nitride film is 15, but the remaining amount of the insulating film 21 made of the silicon nitride film is the smallest. A thickness of about 0.02 μm was secured even in the part.

On the other hand, the connection hole 17d1 is a hole for leading out the plate electrode (second electrode) 23c, and penetrates through the interlayer insulating film 11i and the plate electrode 23c and is located at a depth of the lower interlayer insulating film 11h. It is dug to the position. Although the connection holes 17c1 and 17d1 are formed in the same processing step, one connection hole 17d1 cannot reach the insulating film 21 because the connection hole 17c1 where the insulating film 21 is exposed from the bottom is in the middle. While the plate electrode 23c is not interposed at the depth position and there is no obstacle, the connection hole 17d1 which terminates at the intermediate depth position of the interlayer insulating film 11h.
In this case, the upper electrode 23c is interposed at a depth position on the way, and the etching rate is delayed by a portion of the upper electrode 23c to be removed by etching.

Thereafter, using the photoresist film 24b as an etching mask, the insulating film 21 exposed from the connection hole 17c1 is selectively removed by etching with respect to the interlayer insulating films 11g, 11h and 11i, as shown in FIG. A connection hole (second hole) 17c2 extending from the bottom of the connection hole 17c1 toward the semiconductor substrate 1 is formed. That is, the etching process is performed under the condition that the etching selectivity between the silicon oxide film and the silicon nitride film is relatively large and the silicon nitride film is more easily removed by etching than the silicon oxide film.

Next, using the photoresist film 24b as an etching mask, the silicon oxide film is more easily etched and removed than the silicon nitride film in a state where the etching selectivity between the silicon oxide film and the silicon nitride film is relatively large. The interlayer insulating films 11e to 11g and 11h exposed from the bottoms of the connection holes 17c1 (17c2) and 17d1 are removed by etching.
As shown in FIG. 35, the connection holes 17c and 17d are formed.

A portion of first layer wiring 14 is exposed from the bottom of connection hole 17c. FIG. 35 shows a case where the relative plane position between the connection hole 17c and the first layer wiring 14 is slightly shifted for the sake of explanation. In the present embodiment, during this etching process, a 50% over-etching process (corresponding to 0.2 μm) is performed on the total thickness of the interlayer insulating films 11 e to 11 g of 0.4 μm, and as a result, the connection hole 17 c is out of contact. In the region, the bottom of the connection hole 17c is formed between the interlayer insulating films 11b to 11d under the first layer wiring 14.
It has been dug to the depth position on the way. However, the remaining amount of the insulating film of at least 0.4 μm is secured between the bottom of the connection hole 17 </ b> C and the semiconductor substrate 1 in the out-of-focus region, and there is no possibility that both are electrically connected. That is, since the amount of over-etching can be increased, even in the case of the connection hole 17c which is fine and has a high aspect ratio, it is possible to suppress the occurrence of conduction failure and increase / change in resistance inside the connection hole 17c. Therefore, the yield and reliability of the DRAM can be improved.

On the other hand, the insulating film 2 extends from the bottom of the connection hole 17d.
1 is exposed. In this etching process, the condition is such that the silicon oxide film is more easily removed by etching, so that the connection hole 17d is formed by the insulating film 21 made of a silicon nitride film.
Does not reach the first layer wiring 14. Normal,
The first layer wiring 14 is not provided immediately below the connection hole for leading out the plate electrode 23c because the connection hole may reach the wiring layer depth of the first layer wiring 14 at the time of the drilling. Since there is no such fear in the form,
The first layer wiring 14 can also be arranged immediately below the connection hole 17d for leading out the plate electrode 23c. Therefore, the size of the semiconductor chip can be reduced and the first layer wiring 14 can be reduced.
High density arrangement can be promoted.

Subsequently, as in the first embodiment and the like, a conductor film made of, for example, a titanium nitride film and a conductor film made of, for example, tungsten are sequentially applied from the lower layer, and the plug 25b is etched back. , 25c. Also in this case, since the first layer wiring 14 is made of tungsten, the first layer wiring 14 is not etched or a high-resistance layer is not formed during the process of forming the tungsten film for forming the plug. The plug 25b is electrically connected to the first layer wiring 14 in a state of being in direct contact therewith. The plug 25c is connected to the plate electrode 2c through a part of the plate electrode 23c exposed from the inner surface of the connection hole 17d.
3c.

Thereafter, as in the first embodiment and the like, after forming the second layer wiring 26, an interlayer insulating film 11j made of, for example, a silicon oxide film is formed on the interlayer insulating film 11i by CVD.
The second layer wiring 26 is coated by a method. afterwards,
After piercing the connection hole 28 in the interlayer insulating film 11j, a plug 29 is formed therein similarly to the plugs 25c and 25d,
Further, on the interlayer insulating film 11j, a third layer wiring 30 is
It is formed in the same manner as the layer wiring 26. In this way DRAM
To manufacture.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say,

For example, in the first to sixth embodiments,
The case where the shape of the information storage capacitor is cylindrical has been described. However, the present invention is not limited to this, and various applications are possible. For example, the invention can be applied to a fin-type information storage capacitor.

In the first to sixth embodiments,
In the case of forming an information storage capacitor, a method of forming a storage electrode in a groove after forming a groove in an interlayer insulating film has been described, but the method is not limited to this, and various changes can be made. For example, the following may be performed.

First, after a conductor film for forming a storage electrode is deposited on an interlayer insulating film, an insulating film is deposited thereon. Subsequently, the bottom of the storage electrode is formed by patterning the insulating film and the conductor film, and a pattern of the insulating film is formed thereon. Then, after depositing a conductor film for forming the storage electrode so as to cover the surface of the insulating film and the bottom of the storage electrode, the conductor film is etched back to leave the conductor film only on the side wall of the insulating film, and the storage electrode is formed. Is formed. Thereafter, the storage electrode is formed by removing the insulating film surrounded by the bottom and side walls of the storage electrode.

In the above description, the invention made mainly by the present inventor is referred to as the DRA which is the application field in which the invention is based.
Although the description has been given of the case where the present invention is applied to the M technology, the present invention is not limited to this. For example, an SRAM (Static Random
Access Memory) and flash memory (EEPROM;
Other semiconductor integrated circuit devices such as other memory circuit chips such as Electrically Erasable Programmable ROM), logic circuit chips such as microprocessors, or memory circuit chips with logic having a logic circuit and a memory circuit on the same semiconductor chip. Applicable to

[0209]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, in the peripheral circuit region of the DRAM, the connection hole for electrically connecting the first layer wiring and the second layer wiring is formed by the first connection hole and the second connection hole. The first and second buried conductor films are buried and formed in the respective connection holes, so that the first and second connection holes are drilled and the conductor film is formed. Can be easily embedded.

(2) According to the above (1), conduction failure in the first connection hole and the second connection hole can be reduced, so that the yield and reliability of the DRAM can be improved. .

(3) According to the above (1), when setting the height of the stack-type information storage capacitor, restrictions imposed by the connection holes drilled in the peripheral circuit area can be relaxed. It is possible to increase the capacitance of the storage capacitor.
Therefore, it is possible to increase the capacity that contributes to information storage without increasing the area occupied by the information storage capacitor element and without newly introducing a sophisticated and complicated process technology.

(4) According to the above (3), it is possible to improve the refresh characteristics of the DRAM and the reliability of the read / write operation without increasing the area of the memory cell region.

(5) According to the present invention, by making the diameter of the second connection hole larger than the diameter of the first connection hole, a photolithography step for forming the second connection hole is performed. , The alignment accuracy can be reduced. Also, the second
Can be easily performed in the etching step for forming the connection hole. Further, it is possible to easily and favorably embed the conductor film in the second connection hole.

(6) According to the present invention, the first connection hole in the peripheral circuit region of the DRAM is formed simultaneously with the step of forming the connection hole used for the information storage capacitor in the memory cell region. Of the DRAM by simultaneously burying the connection holes of
Can be greatly reduced, and the DRAM manufacturing process can be simplified.

(7) According to the present invention, the first connection hole in the peripheral circuit region of the DRAM is formed simultaneously with the step of forming the connection hole used for the information storage capacitor in the memory cell region. Of the DRAM by simultaneously burying the connection holes of
Therefore, the yield and reliability of the DRAM can be improved since the rate of occurrence of foreign substances generated during the manufacturing process can be reduced.

(8) According to the present invention, the diameter of the second connection hole is made larger than the diameter of the first connection hole so as to include a plurality of the first connection holes, and By electrically connecting one second buried conductor film in the connection hole and each first buried conductor film in the plurality of first connection holes, the second buried conductor film is formed. Since the resistance between the film and the lower connection portion can be reduced, the overall wiring resistance can be reduced.

(9) According to the present invention, the diameter of the second connection hole is made larger than the diameter of the first connection hole so that a plurality of the first connection holes can be included, and By electrically connecting one second buried conductor film in the connection hole and each of the first buried conductor films in the plurality of first connection holes, Drilling and embedding with a conductive film can be facilitated.

(10) According to the present invention, when a connection hole for electrically connecting a first wiring and a second wiring sandwiching an information storage capacitor in a DRAM is formed, an over-etching process is performed. In this case, a predetermined amount of an insulating film can be secured between the bottom of the connection hole and the semiconductor substrate in a region outside the connection hole. That is, since the amount of over-etching can be increased, even a fine connection hole having a high aspect ratio can be satisfactorily drilled, and the occurrence of poor conduction and an increase or variation in resistance can be suppressed. Therefore, it is possible to improve the yield and reliability of the semiconductor integrated circuit device.

(11) According to the present invention, by providing the second insulating film between the second electrode of the information storage capacitor and the first wiring, it is possible to draw out the second electrode. When forming the connection hole, the second insulating film can function as an etching stopper. For this reason, there is no possibility that the bottom of the connection hole reaches the first wiring in the lower layer.
The first wiring can be arranged directly below the connection hole. Therefore, the size reduction of the semiconductor chip and the first
It is possible to promote the high-density arrangement of the wirings.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention during a manufacturing step thereof;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

9 is a main part plan view showing connection holes of the semiconductor integrated circuit device of FIG. 8;

FIG. 10 is a plan view of a principal part showing connection holes of the semiconductor integrated circuit device of FIG. 8;

FIG. 11 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step;

12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 11;

13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 12;

14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 13;

15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 14;

16 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 15;

17 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 16;

18 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 17;

FIG. 19 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step;

20 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 19;

21 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 20;

FIG. 22 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 21;

23 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 22;

24 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 23;

25 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 24;

FIG. 26 is an essential part cross sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during a manufacturing step;

27 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 26;

28 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 27;

FIG. 29 is a plan view of relevant parts of a semiconductor integrated circuit device according to another embodiment of the present invention;

30 is a fragmentary perspective view of a part of the semiconductor integrated circuit device of FIG. 29, cut away;

FIG. 31 is a fragmentary perspective view of the semiconductor integrated circuit device of FIG. 29 with a part cut away;

FIG. 32 is a plan view of relevant parts of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 33 is an essential part cross sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during a manufacturing step;

34 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 33;

35 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 34;

36 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 35;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2nw deep n-well 3pwm p-well 3pwp p-well 4 element isolation region 4a isolation trench 4b1, 4b2 isolation insulating film 5a, 5b semiconductor region 5i gate insulating film 5g gate electrode 6 cap insulating film 7 insulating film 8a, 8b Semiconductor region 8a1, 8b1 Low concentration region 8a2, 8b2 High concentration region 8c Silicide layer 8i Gate insulating film 8g Gate electrode 9 Sidewall 10a, 10b Semiconductor region 10a1, 10b1 Low concentration region 10a2, 10b2 High concentration region 10c Silicide layer 10i Gate insulation Film 10g Gate electrode 11a to 11d Interlayer insulating film 11e to 11g Interlayer insulating film (first insulating film) 11h Interlayer insulating film (third insulating film) 11h1 Interlayer insulating film (second insulating film) 11h2 Interlayer insulating film 11i Interlayer insulating film (third insulating film) 12a, 12b Connection hole 1 3a, 13b Plug 14, 14a to 14c First layer wiring 15 Connection hole 16 Connection hole 17a Connection hole (first connection hole) 17b Connection hole (second connection hole) 18 Conductive film 18a Plug (first connection portion) 19) Connection hole 20 Plug (conductor film for capacitance element) 21 Insulating film (second insulating film) 21a Insulating film (second insulating film) 21b Insulating film (fifth insulating film) 22 Groove 23a Storage electrode (first electrode) 1 electrode 23b Capacitive insulating film 23c Plate electrode (second electrode) 24a, 24b Photoresist pattern 25 Conductive film 25a Plug (second connection part) 26 Second layer wiring 27 Conductive film 27a Plug (capacitor conductor) Film) 27b plug 28 connection hole 29 plug 30 third layer wiring Q memory cell selecting MOS / FET C information storage capacitance element Qn MOS • FET Qp MOS • FE T BL bit line WL word line

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kensei Hirasawa 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Keizo Kawakita 6-16, Shinmachi, Ome-shi, Tokyo No. 3 in Hitachi, Ltd. Device Development Center Co., Ltd. (72) Inventor Tadaki ▲ yoshi ▼ ▲ taka ▼ 6-16 Shinmachi, Shinmachi, Ome-shi, Tokyo 3 Co., Ltd. in Hitachi Device Co., Ltd. (72) Inventor Satoru Yamada 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Tsuyoshi Kawagoe 5-221-1, Josuihonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Systems Inc. (72) Inventor Toshihiro Sekiguchi 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Within the Development Center (72) Inventor Isamu Isano 6-16-16 Shinmachi, Ome-shi, Tokyo F-term in the Device Development Center, Hitachi, Ltd. F-term (reference) JA35 JA39 JA40 KA01 KA05 MA02 MA06 MA17 NA01 PR03 PR21 PR39 PR40 ZA12

Claims (29)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device, comprising a semiconductor substrate provided with a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the transistor. Forming a bit line and a first wiring on the same wiring layer on a semiconductor substrate; forming the information storage capacitive element above the bit line without interposing another wiring layer; Forming a second wiring in an upper layer of the storage capacitor element, and electrically connecting the first wiring and the second wiring in a state of being directly in contact with the first wiring. Forming a first connection portion and a second connection portion electrically connected to the first connection portion while being in direct contact with the first connection portion. Production method. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a plane dimension of said second connection section is larger than a plane dimension of said first connection section. A method for manufacturing a circuit device. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first wiring is made of tungsten or tungsten silicide, and said first connection part is formed of a first metal film and a CVD method thereon. And a second metal film made of tungsten formed by a method. 4. A method of manufacturing a semiconductor integrated circuit device, comprising a semiconductor substrate provided with a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the memory cell selection transistor. a) forming a bit line and a first wiring on the same wiring layer on the semiconductor substrate; and (b) forming a first insulating film covering the bit line and the first wiring on the semiconductor substrate. And (c) drilling a first connection hole in the first insulating film where the first wiring is exposed in a region other than the memory cell formation region; and (d) the first connection hole. Forming a first connection portion by burying a first conductor film in the connection hole of
(E) forming a second insulating film made of a material having a relatively large etching selectivity with respect to the first insulating film so as to cover the upper surfaces of the first insulating film and the first connection portion; (F) forming an information storage capacitance element above the bit line in the memory cell formation region; and (g) forming the information storage region in a region other than the memory cell formation region. A second insulating film provided between the wiring layer above the capacitive element for use and the first connecting portion, and a third insulating film made of a material having a relatively large etching selectivity with respect to the second insulating film. Drilling a second connection hole exposing said first connection portion in said insulating film; and (h)
Embedding a second conductive film in the second connection hole to form a second connection portion electrically connected to the first connection portion in a state of being directly contacted with the first connection portion. Of manufacturing a semiconductor integrated circuit device. 5. The step (g) of the method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the step of forming the second connection hole includes etching the second insulating film and the third insulating film. Performing an etching process under conditions in which the third insulating film is more easily etched away than the second insulating film with the selectivity increased, and etching the second insulating film and the third insulating film. Performing an etching process under conditions in which the second insulating film is more easily removed by etching than the first insulating film and the third insulating film with the selectivity increased. A method for manufacturing a circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein in the step (f), after a third insulating film is formed on the second insulating film, the third insulating film is formed. Forming a groove for forming an information storage capacitive element in the groove, forming a first electrode in the groove, forming a capacitive insulating film on a surface of the first electrode, Forming a second electrode covering the capacitive insulating film. In the step of forming the groove, the third electrode is formed in a state where the etching selectivity between the second insulating film and the third insulating film is increased. Performing an etching process under conditions in which the second insulating film is more easily etched away than the second insulating film;
Performing an etching process under conditions in which the second insulating film is more easily etched away than the first insulating film and the third insulating film in a state where the etching selectivity with respect to the first insulating film is increased. A method for manufacturing a semiconductor integrated circuit device, comprising: 7. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein a plane dimension of said second connection part is larger than a plane dimension of said first connection part. A method for manufacturing a circuit device. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein a plane dimension of said second connection portion is set so as to include a plurality of said first connection portions within said plane size. A method of manufacturing a semiconductor integrated circuit device, wherein the planar dimension of the connecting portion is larger than the connecting portion. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein said first wiring is made of tungsten or tungsten silicide, and said first conductor film of said first connection portion is made of a first metal. A method for manufacturing a semiconductor integrated circuit device, comprising: a film; and a second metal film made of tungsten formed on the film by a CVD method. 10. A method of manufacturing a semiconductor integrated circuit device, comprising a semiconductor substrate provided with a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the memory cell selection transistor. a) forming a bit line and a first wiring on the same wiring layer on the semiconductor substrate; and (b) forming a first insulating film covering the bit line and the first wiring on the semiconductor substrate. And (c) drilling a first connection hole in the first insulating film where the first wiring is exposed in a region other than the memory cell formation region; and (d) the first connection hole. Forming a first connection portion by burying a first conductor film in the connection hole of
(E) forming an information storage capacitor in a layer above the bit line in the memory cell formation region;
(F) In an area other than the memory cell formation area,
Drilling a second connection hole exposing the first connection portion in an insulating film provided between the wiring layer above the information storage capacitor and the first connection portion; (g ) The second
Forming a second connection portion electrically connected to the second conductor film in a state of being directly contacted with the first connection portion, by burying a second conductor film in the connection hole of the semiconductor device. A method for manufacturing an integrated circuit device. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein a plane dimension of said second connecting portion is
A method for manufacturing a semiconductor integrated circuit device, wherein the planar dimension of the first connection portion is larger than the planar size. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein a plane dimension of said second connecting portion is
A method for manufacturing a semiconductor integrated circuit device, characterized in that the plane dimensions of the first connection section are larger than the plane dimensions of the first connection section so that a plurality of the first connection sections can be included in the plane dimensions. 13. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein said first wiring is made of tungsten or tungsten silicide, and said first conductor film of said first connection portion is made of a first metal. A method for manufacturing a semiconductor integrated circuit device, comprising: a film; and a second metal film made of tungsten formed on the film by a CVD method. 14. A method of manufacturing a semiconductor integrated circuit device, comprising a semiconductor substrate provided with a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to said transistor. a) forming a bit line and a first wiring on the same wiring layer on the semiconductor substrate; and (b) forming a first insulating film covering the bit line and the first wiring on the semiconductor substrate. (C) forming a second insulating film on the first insulating film, the second insulating film being made of a material having a relatively high etching selectivity with respect to the first insulating film; Forming a fourth insulating film on the second insulating film, the fourth insulating film being made of a material having a relatively high etching selectivity with respect to the second insulating film; and (e) forming the first insulating film. , The second insulating film and the fourth insulating film Drilling a first connection hole exposing the first wiring in a region other than the memory cell formation region; and (f) burying a first conductor film in the first connection hole; Forming a first connection, (g).
Forming a fifth insulating film made of a material having a relatively high etching selectivity with respect to the fourth insulating film so as to cover the upper surfaces of the fourth insulating film and the first connection portion; (H) forming a sixth insulating film on the fifth insulating film, the sixth insulating film being made of a material having a relatively high etching selectivity with respect to the fifth insulating film; In the cell formation region, a groove for an information storage capacitor is formed in the second insulating film, the fourth insulating film, the fifth insulating film, and the sixth insulating film. Forming a storage capacitor element; (j) forming a seventh insulating film on the sixth insulating film so as to cover the information storage capacitor element; and (k) forming the memory cell. In a region other than the region, the seventh insulating film, the sixth insulating film, and the fifth insulating film The first connection portion is exposed to 2
And (l) embedding a second conductive film in the second connection hole, and electrically connecting the second conductor film in a state of being directly in contact with the first connection portion. Forming a connection portion. A method of manufacturing a semiconductor integrated circuit device, comprising: 15. The method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein in the step (k), the step of forming the second connection hole comprises the steps of: forming the fifth insulating film, the sixth insulating film, and the seventh insulating film. Performing an etching process under conditions in which the sixth insulating film and the seventh insulating film are more easily removed by etching than the fifth insulating film in a state where the etching selectivity with respect to the fifth insulating film is increased; In a state where the etching selectivity between the first insulating film, the sixth insulating film, and the seventh insulating film is increased, the fifth insulating film becomes the fourth insulating film, the sixth insulating film, and the seventh insulating film. Performing an etching process under conditions that are more easily removed by etching than the film. 16. The method for manufacturing a semiconductor integrated circuit device according to claim 14, wherein a plane dimension of said second connection portion is
A method for manufacturing a semiconductor integrated circuit device, wherein the planar dimension of the first connection portion is larger than the planar size. 17. The method for manufacturing a semiconductor integrated circuit device according to claim 14, wherein said first wiring is made of tungsten or tungsten silicide, and said first conductor film of said first connection portion is made of a first metal. A method for manufacturing a semiconductor integrated circuit device, comprising: a film; and a second metal film made of tungsten formed on the film by a CVD method. 18. A method for manufacturing a semiconductor integrated circuit device, comprising: a semiconductor substrate provided with a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the memory cell selection transistor. a) forming a bit line and a first wiring on the same wiring layer on the semiconductor substrate; and (b) forming a first insulating film covering the bit line and the first wiring on the semiconductor substrate. And (c) perforating a first connection hole in the first insulating film where the first wiring is exposed in a region other than a region where the memory cell is formed, and forming a region where the memory cell is formed Drilling a connection hole for an information storage capacitor in which the bit line is exposed; and (d) forming a first conductive film in the first connection hole and the connection hole for the information storage capacitor. Embedded in each of the first connection portions And forming a connection portion for the information storage capacitor, and (e) forming the first insulating film, the first connection portion, and the upper surface of the connection portion for the information storage capacitor so as to cover upper surfaces of the connection portion. Forming a second insulating film made of a material having a relatively large etching selectivity with respect to the first insulating film; and (f) storing information in the memory cell formation region above the bit line. (G) forming a second capacitor provided between the wiring layer above the information storage capacitor and the first connection portion in a region other than the memory cell formation region; Forming a second connection hole in which the first connection portion is exposed in a third insulating film made of a material having a relatively large etching selectivity with respect to the insulating film and the second insulating film; (H)
Embedding a second conductive film in the second connection hole to form a second connection portion electrically connected to the first connection portion in a state of being directly contacted with the first connection portion. Of manufacturing a semiconductor integrated circuit device. 19. A method for manufacturing a semiconductor integrated circuit device, comprising a semiconductor substrate provided with a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the memory cell selection transistor. Forming a bit line and a first wiring on the same wiring layer on a semiconductor substrate; forming the information storage capacitive element above the bit line without interposing another wiring layer; Forming a second wiring on the capacitive element for use, wherein the first wiring and the second wiring are provided between the first wiring and the second wiring in a region other than the formation region of the memory cell. Second
A method of manufacturing a semiconductor integrated circuit device, the method comprising: forming a plurality of connection portions for electrically connecting a plurality of wirings, wherein the plurality of connection portions are electrically connected to each other in a state of being in direct contact with each other. . 20. A method of manufacturing a semiconductor integrated circuit device, comprising a semiconductor substrate provided with a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the transistor. a) forming a bit line and a first wiring on the same wiring layer on the semiconductor substrate; and (b) forming a first insulating film covering the bit line and the first wiring on the semiconductor substrate. (C) forming a second insulating film on the first insulating film, the second insulating film being made of a material having a relatively high etching selectivity with respect to the first insulating film; Forming an information storage capacitor in a layer above the bit line in the memory cell formation region; and (e) wiring above the information storage capacitor in a region other than the memory cell formation region Layer and the said A first insulating film and a second insulating film provided between the first wiring and the first wiring, and a third insulating film formed on the second insulating film and made of a material having a relatively large etching selectivity with respect to the second insulating film. Drilling a connection hole between the wiring layers where the first wiring is exposed in the insulating film; and (f) embedding a conductive film in the connection hole between the wiring layers and directly contacting the first wiring. Forming a connection portion between wiring layers electrically connected to each other; and forming a connection hole between the wiring layers; forming a mask pattern for forming a connection hole on the third insulating film. And using the mask pattern as an etching mask, with the etching selectivity between the second insulating film and the third insulating film being relatively large, the third insulating film is better than the second insulating film. Perform etching treatment under conditions that are easy to remove by etching. The third exposed from the mask pattern
A first etching step of perforating a first hole exposing a part of the second insulating film in the insulating film; and after the first etching step, the second pattern is formed using the mask pattern as an etching mask. The second insulating film is etched under the condition that the second insulating film is more easily removed by etching than the third insulating film in a state where the etching selectivity between the third insulating film and the third insulating film is relatively increased. The second insulating film exposed from the bottom of the first hole is removed to remove the second insulating film.
A second etching step of perforating a second hole exposing a part of the first insulating film in the insulating film, and after the second etching step, the second insulating film and the first With the etching selectivity to the insulating film relatively high, the first insulating film is etched under conditions that are more easily removed by etching than the second insulating film, and is exposed from the bottom of the second hole. Removing the first insulating film to form a connection hole between wiring layers in which the first wiring is exposed. 21. The method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein in the step (d), a step of forming a first electrode constituting the information storage capacitive element and a step of forming the first electrode are performed. Forming a capacitive insulating film on the surface of the semiconductor device, and forming a second electrode covering the capacitive insulating film. The step (e) includes forming the second insulating film on the third insulating film. Forming a second electrode connection hole penetrating an electrode; and forming the second electrode connection hole and the second electrode connection hole on the third insulating film. Forming a mask pattern for forming a contact hole; and forming a third insulating film by using the mask pattern as an etching mask while relatively increasing an etching selectivity between the second insulating film and the third insulating film. The film is etched more than the second insulating film By performing the etching-treated with a amendable conditions, third exposed from the mask pattern
Forming, in the insulating film, a first hole for forming a connection hole between the wiring layers and a part of the second insulating film being exposed, and a connection hole for leading out the second electrode. A first hole penetrating the second electrode, the first hole penetrating through the second electrode, and having a bottom extending to an intermediate position of the third insulating film; and a first etching process. After the step, the second insulating film is larger than the third insulating film in a state where the etching selectivity between the second insulating film and the third insulating film is relatively large using the mask pattern as an etching mask. The second portion exposed from the bottom of the first hole for the connection hole between the wiring layers is formed by performing the etching process under the condition in which
Removing a second insulating film and exposing a second hole for a connection hole between the wiring layers exposing a part of the first insulating film; and after the second etching process, Etching is performed under conditions in which the first insulating film is more easily removed by etching than the second insulating film in a state where the etching selectivity between the second insulating film and the first insulating film is relatively large. A third etching process step of piercing a connection hole between wiring layers in which a first wiring is exposed from a bottom of the second hole for a connection hole in the wiring interlayer insulating film. A buried conductor film in a connection hole between the wiring layers and a connection hole for drawing out a second electrode, and a connection portion between the wiring layers electrically connected in a state of being directly in contact with the first wiring, respectively. A second electrode electrically connected to the second electrode The method of manufacturing a semiconductor integrated circuit device characterized by a step of forming a connection for out come. 22. The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein the first wiring is made of tungsten or tungsten silicide, and a connection between the wiring layers and a connection for leading a second electrode are formed. A method for manufacturing a semiconductor integrated circuit device, characterized in that a conductor film comprises a first metal film and a second metal film made of tungsten formed thereon by a CVD method. 23. A semiconductor integrated circuit device comprising a semiconductor substrate provided with a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series with the memory cell selection transistor. A bit line and a first wiring formed on the same wiring layer, an information storage capacitor provided above the bit line without interposing another wiring layer, and A second wiring provided between the first wiring and the second wiring in a region other than the memory cell formation region in a state in which the first wiring is in direct contact with the first wiring. A first connection electrically connected;
A second connection portion electrically connected to the first connection portion in a state of being directly contacted with the first connection portion, and the first wiring and the second wiring are electrically connected to each other. Semiconductor integrated circuit device. 24. The semiconductor integrated circuit device according to claim 23, wherein a plane dimension of said second connection part is larger than a plane dimension of said first connection part. 25. The semiconductor integrated circuit device according to claim 23, wherein said first wiring is made of tungsten or tungsten silicide, and said first connection part is made of a first material.
And a second metal film made of tungsten formed thereon by a CVD method. 26. A semiconductor integrated circuit device comprising a semiconductor substrate provided with a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the memory cell selection transistor. A first wiring and a bit line formed on the same wiring layer on the semiconductor substrate; and (b) a first insulating film covering the first wiring and the bit line;
(C) In an area other than the memory cell formation area,
A first connection hole drilled so that a part of the first wiring is exposed in the first insulation film; and (d) a conductor film is formed by being embedded in the first connection hole. A first connection portion, (e) an information storage capacitor formed in the upper layer of the bit line, and (f) a second wiring formed in a wiring layer above the information storage capacitor. (G) in a region other than the memory cell formation region, the insulating film between the second wiring and the first connection portion is overlapped with the second wiring in a plane, and the first wiring (H) a conductor film is embedded in the second connection hole so that a part of the connection portion is exposed, and the second wiring and the first connection portion are formed by embedding a conductive film in the second connection hole. A second connection portion electrically connected to the semiconductor integrated circuit device in a state of being directly contacted with the semiconductor integrated circuit device. 27. A semiconductor integrated circuit device comprising: a semiconductor substrate provided with a plurality of memory cells each including a memory cell selection transistor and an information storage capacitor connected in series to the memory cell selection transistor; A first wiring and a bit line formed on the same wiring layer on the semiconductor substrate; and (b) a first insulating film covering the first wiring and the bit line;
(C) a second insulating film formed on the first insulating film and made of a material having a relatively high etching selectivity with respect to the first insulating film; and (d) a second insulating film above the bit line. The information storage capacitor element provided on the wiring layer and having a first electrode, a capacitor insulating film formed on the surface thereof, and a second electrode formed thereon; (e) the information storage capacitor A second wiring formed on a wiring layer above the element;
(F) In an area other than the memory cell formation area,
A connection hole between wiring layers, which is formed in the insulating film between the first wiring and the second wiring, and electrically connects the first wiring and the second wiring; A connection portion between wiring layers formed by embedding a conductive film in the connection hole of
(H) In an area other than the memory cell formation area,
A connection hole for drawing out the second electrode, and
(I) an electrode lead-out connection portion formed by embedding a conductive film in the electrode lead-out connection hole; and between the electrode lead-out connection portion and the first wiring,
A semiconductor integrated circuit device, wherein the second insulating film is interposed, and the first wiring is provided immediately below the connection part for leading out the electrode. 28. A first MIS in a first region of a semiconductor substrate.
A method for manufacturing a semiconductor integrated circuit device in which a memory cell composed of an FET and a capacitor connected in series with the FET is formed, and a second MISFET is formed in a second region of the semiconductor substrate, comprising: Forming a first wiring in a second region of the semiconductor substrate; (b) forming a first insulating film on the first wiring; and (c) forming a first wiring on the first insulating film.
Forming an opening and exposing a part of the first wiring;
(D) a step of selectively forming a first conductor layer in the first opening; (e) a step of forming a second insulation film on the first insulation film and the first conductor layer; A) forming a third insulating film on the second insulating film; and (g) forming a second opening in the third insulating film in the first region.
(H) a step of selectively forming a second conductor layer along the inner wall of the second opening, and (i) a step of forming a fourth insulating film and a third conductor layer on the second conductor layer. (J) forming a third opening in the third insulating film and the second insulating film in the second region so as to expose a part of the first conductor layer; and (k) Forming a fourth conductor layer in the third opening, wherein the step of forming the second opening increases an etching rate of the third insulating film with respect to the second insulating film. The third insulating film is etched under the condition, and the step of forming the third hole is performed under the condition that the etching rate of the third insulating film is higher than that of the second insulating film. After the insulating film is etched, under the condition that the etching rate of the second insulating film is higher than that of the third insulating film, The method of manufacturing a semiconductor integrated circuit device characterized by etching the second insulating film is subjected. 29. A first MIS in a first region of a semiconductor substrate
A method for manufacturing a semiconductor integrated circuit device in which a memory cell composed of an FET and a capacitor connected in series with the FET is formed, and a second MISFET is formed in a second region of the semiconductor substrate, comprising: Forming a first wiring in a second region of the semiconductor substrate; (b) forming a first insulating film on the first wiring; and (c) forming a second wiring on the first insulating film.
Forming an insulating film; (d) forming a third insulating film on the second insulating film; and (e) forming a second opening in the third insulating film in the first region. Process and
(F) selectively forming a first conductive layer along the inner wall of the second opening; and (g) forming a fourth insulating film and a second conductive layer on the first conductive layer. (H) forming a third aperture in the third insulating film and the second insulating film in the second region such that a part of the first wiring is exposed; Forming a third conductor layer in the third opening, wherein the step of forming the second opening is such that the etching rate of the third insulating film is higher than that of the second insulating film. Then, the third insulating film is etched, and the step of forming the third opening is performed under the condition that the etching rate of the third insulating film is higher than that of the second insulating film. After the film is etched, the second insulating film is etched under a condition that the etching rate of the second insulating film is higher than that of the first insulating film. Etching is performed on the insulating film, further, a method of manufacturing a semiconductor integrated circuit device characterized by etching is applied to the first insulating film so as to expose a portion of said first wiring.