JP2001223532A - Radio receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulation system which solves the problems of a conventional technique and can cope even with demodulation processing of different modulation system and band. SOLUTION: This demodulation processing system is has a means which calculates a sampling frequency according to the center frequencies and the bandwidth information of HF, VHF and UHF band received signals, controls a PLL oscillator 6 or the oscillator 6 and the number of frequency divisions of a variable frequency divider performing frequency division of an output of the oscillator and converts an analog signal into a digital signal according to a sampling frequency that is lower than a double highest frequency inputted to an A/D converter 5 by controlling the sampling frequency of the converter 5, and a means which calculates a carrier frequency that is lower than the center frequency of a signal inputted to the converter 5 according to the sampling frequency and performs demodulation processing 13 by the carrier of digital signal processing subjected to frequency conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio receiver using digital signal processing, and more particularly to a receiver having an improved demodulation system.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration example of a conventional receiving apparatus, and FIG. 4 shows a configuration example of a digital signal processing portion.

In FIG. 3, a transmission / reception switch 31 is connected from an antenna.
As a result, the received signal is amplified by the high-frequency amplifier 32 at a predetermined amplification degree and input to the frequency converter 34. A carrier having a frequency relationship such that a predetermined intermediate frequency is output from the frequency converter 34 according to the relationship with the reception frequency by the carrier generator 33 is input to the frequency converter 34. This frequency relationship is controlled by frequency information from a control process or the like inside the receiving device (not shown).

The output from the frequency converter 34 becomes an intermediate frequency and is input to the A / D converter 35. A / D converter 3
In 5, the analog signal is converted into a digital signal by the sampling clock from the clock oscillator 36,
It is input to the DSP 37. Usually, a band limiting filter is inserted before the A / D converter 35, but is omitted here.

In the digital signal processing of the signal input to the DSP 37, a predetermined band filtering processing is performed by a BPF 38, and an amplification and control processing for an AGC (automatic gain control) processing is performed by an AGC control / amplification unit 39. It is. Thereafter, the demodulation processing unit 42 performs SSB demodulation processing in the HF (short wave) band, AM or FM demodulation processing in the VHF (ultra short wave) band, and AM demodulation processing in the UHF (ultra high frequency) band.

One of the demodulated signals is a D / A converter 43
The other is input to the AGC detection processing unit 40 for AGC amplification and control processing.

[0007] The low frequency signal input to the D / A converter 43 is sampled by a clock signal output from a clock oscillator 45 and input to a low frequency amplifier 44. After being amplified at a predetermined amplification degree in the low-frequency amplifier 44, a signal is output as a demodulated output.

The frequency converter 34 may provide a plurality of frequency conversions depending on the frequency band to be processed and the amplification factor.

FIG. 4 shows the configuration of the digital signal processing section of FIG. Frequency converter 34 in FIG.
Is input to an A / D converter 35, and is converted from an analog signal to a digital signal by a sampling clock from a clock oscillator 36. This signal is input to the control / interface processing unit 47. In the control / interface processing unit 47, DS
It performs processing such as control of a signal input to P37 and control of the DSP 37, and outputs the result to the DSP 37. The DSP 37 performs demodulation processing and outputs the result to the control / interface processing 47. The control / interface processing 47 performs the same control processing as that of the input signal, and outputs the result to the D / A converter 43. The D / A converter 43 converts the clock signal output from the clock oscillator 45 into an analog signal and outputs the analog signal as a demodulated wave. The memory 46 is used for temporarily storing data or programs.

[0010]

In the above-mentioned conventional configuration, the clock oscillator is fixed, so that it has a drawback that it cannot cope with signals of different modulation schemes and bands. Conventionally, sampling was performed at a frequency higher than twice the maximum frequency of the signal, so that the sampling clock must correspond to the highest frequency of the highest frequency band in order to support signals of different modulation schemes and frequency bands. However, since there is a limit due to the processing capability of the DSP, there is a limit to the contents to be processed.

For example, in the short wave band, if the intermediate frequency (IF) is 455 kHz and the modulation method is the SSB (single sideband) method, the required bandwidth is about 3 kHz. Since the highest frequency of the signal is about 458 kHz, the lowest sampling frequency is 916 kHz according to the Nyquist theorem, but it is actually at least about 1 M in consideration of the transition range of the band limiting filter.
Hz or higher. Assuming the processing capacity of DSP is 50MI
Assuming PS, the processing capacity is 50 instructions (assuming one instruction per cycle) without considering the DSP overhead.

An object of the present invention is to provide a demodulation process of a different modulation method and band, which is a problem of the prior art, because the sampling clock of the A / D converter cannot cope with the demodulation process. It is an object of the present invention to solve the problem that the demodulation process is limited by the processing capability, and to provide a demodulation system that can cope with demodulation processes of different modulation systems and bands.

[0013]

The object of the present invention is to provide the above-mentioned HF,
The sampling frequency is calculated based on the center frequency and the bandwidth information of the VHF and UHF band reception signals, and the frequency division number of the PLL oscillator or the variable frequency divider for dividing the PLL oscillator and the oscillator output is controlled based on the calculation result of the sampling frequency. Controlling the sampling frequency of the A / D converter to convert an analog signal into a digital signal at a sampling frequency lower than twice the highest frequency of the signal input to the A / D converter; Means for calculating a carrier frequency lower than the center frequency of the signal input to the A / D converter and performing demodulation processing using a carrier wave of digital signal processing which has been frequency-converted. Achieved.

When the carrier wave modulated wave is an input signal, it is a signal in which energy is concentrated around a carrier (center) frequency. The center frequency is fc, the bandwidth is Δf, and Δf / fc <<
1. The maximum frequency fmax is fc + 0.5Δf. Of course, the sampling frequency fs may be set to fs> fmax × 2, but if fs is high, there is a possibility that the processing becomes impossible because the processing capacity of the DSP is directly limited.

However, as shown in FIG. 5, the spectrum of the band signal may be anywhere in the region indicated by the solid line, and it is sufficient if the spectrum falls within that range. That is, the following equation should be satisfied.

[0016]

(Equation 1)

Where fc: center frequency, Δf: bandwidth,
fs: sampling frequency, n: positive integer Assuming that the sampling frequency fs can be set freely, the range of the sampling frequency is fc + Δf / 2 as in the case of Equation 1.
= Fu, fc−Δf / 2 = fl, then Equation 2 is obtained.

[0018]

(Equation 2)

With this method, it is possible to lower the sampling frequency. For example, fc = 455 kHz,
When the bandwidth is 6 kHz, the minimum sampling frequency is 1
2.05263158kHz ≦ fs ≦ 12.05333
333 kHz, and the allowable range of the deviation of fs is about 0.7.
Hz and an error of 50 ppm can be realized.
If fc = 455 kHz and bandwidth is 28 kHz, the minimum sampling frequency is 58.625 kHz ≦ fs ≦ 5.
In order to share with the former bandwidth at a high sampling frequency of 8.8 kHz, it is impossible to use the same sampling frequency no matter which N is applied according to Equation 2. Therefore, the sampling frequency must be set in accordance with the modulation schemes having different bandwidths.

Accordingly, in the present invention, data for setting a sampling frequency corresponding to a modulation method and a bandwidth is output from a DSP in order to set a different sampling frequency, whereby an A / S signal is output from a synthesizer oscillator such as a PLL.
The sampling clock is output to the D converter.

If the sampling frequency can be set freely, for example, if the sampling frequency is 48 kHz and the carrier frequency is 12 kHz, the carrier frequency table becomes 0.0, 1.0, 0.0 as shown in FIG. , -1.0
Since the sampling frequency and the carrier frequency are determined in advance and are multiples of each other, it is easy to store the carrier frequency table in memory without having to calculate it in advance. A table of carrier frequencies can be realized.

However, the sampling frequency is A / D
Since it is necessary to set according to the center frequency (or the highest frequency, etc.) and the band of the signal input to the converter, it generally differs depending on the communication system, frequency band, and the like. When the carrier frequency is the sampling frequency fs, the center frequency fc of the signal input to the A / D converter is fc−n fs
Therefore, it is generally not always the case that the sampling frequency and the carrier frequency become integral multiples of each other, and it is rather rare that the sampling frequency and the carrier frequency become integral multiples of each other. In Equation 2, f
If u = 458 kHz and fl = 455 kHz, fc =
If N = 35, which is 456.5 kHz, the range of the sampling frequency fs is as shown in Equations 3 and 4.

[0023]

(Equation 3)

[0024]

(Equation 4)

From the above equation, fs = 26.47 kHz is appropriate. In this case, the center frequency fc is converted to fc−n fs. If n = 17, fc−n fs = 456.
5-17 · (26.47) = 6.51 kHz.

In the case of an SSB modulated wave (USB: upper sideband), fcw (frequency of a carrier wave for demodulation) = fc−
Assuming 1.5 (kHz), 6.51−1.5 = 5.01
(KHz) Carrier frequency data when digital signal processing is performed by a DSP or the like is calculated by Equation 5.

[0027]

(Equation 5)

Thus, it is necessary to calculate the table data of such a carrier frequency.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a receiving apparatus according to the present invention, and FIG. 2 is a block diagram of a digital signal processing portion of the receiving apparatus.

In FIG. 1, a reception signal from an antenna is input to a high-frequency amplifier 2 by a transmission / reception switch 1, amplified at a predetermined amplification factor, and then input to a frequency converter 4. A carrier of a predetermined intermediate frequency is input to the frequency converter 4 by the carrier generator 3 according to the relationship with the reception frequency. This frequency relationship is controlled by frequency information from a control process or the like inside the receiving device (not shown).

The output from the frequency converter 4 becomes an intermediate frequency and is input to the A / D converter 5. In the A / D converter 5, the PL controlled by the sampling frequency control unit 7
L (Phase Locked Loop) oscillator 28
The digital signal is converted from an analog signal to a digital signal by the sampling clock from the digital signal processor and is input to the digital signal processor DSP8. Usually, a band limiting filter is inserted before the A / D converter 5, but is omitted here.

In the digital signal processing of the signal input to the DSP 8, a predetermined band filtering processing is performed by the BPF 9,
It is controlled so as to have a predetermined bandwidth. The output of the BPF 9 is input to an AGC control / amplification unit 10 where amplification and control processing for AGC (automatic gain control) processing is performed. After that, the demodulation processing unit 13 sets the SSB in the HF (short wave) band.
A demodulation process is performed on an AM or FM demodulation process in a VHF (ultra high frequency) band, and an AM demodulation process is performed on a UHF (ultra high frequency) band. One of the demodulated signals is a D / A converter 14
The other is input to the AGC detection processing unit 11 for AGC amplification and control processing.

The IF (intermediate frequency) signal input to the D / A converter 14 is sampled by the clock signal output from the clock oscillator 16, converted into an analog signal, and input to the low frequency amplifier 15. Low frequency amplifier 15
Then, after being amplified at a predetermined amplification degree, it is output as a demodulated output.

The carrier frequency calculator / controller 18 performs a calculation as in the example of Equation 5 based on the sampling frequency calculated by the sampling frequency controller 7, writes the calculated data in the memory 17, and stores the carrier wave of the DSP 8 in the carrier frequency. Generator 12
Is transferred, and a carrier wave for processing in the demodulation processing unit 13 is generated.

A plurality of frequency conversion processes in the frequency converter 4 may be provided depending on the frequency to be processed and the degree of amplification.

FIG. 2 shows the configuration of the digital signal processing section.

In FIG. 2, the IF from the frequency converter 4
The (intermediate frequency) signal is input to the A / D converter 5 and
The signal is converted from an analog signal to a digital signal by a sampling clock from the L oscillator 6. PLL oscillator 6
Is controlled by the control / interface processing unit 19 to output a sampling frequency adapted to a predetermined center frequency and bandwidth. The control processing of the control / interface processing unit 19 is the same as that of the sampling frequency control unit 7 in FIG.

The digital signal from the A / D converter 5 is input to a control / interface processing unit 19, which controls a signal to be input to the DSP 8 and controls the DSP 8, for example. Output to DSP8. The processing of the control / interface processing section 19 is the same as that of the carrier frequency calculation / control section 18 in FIG. D
In SP8, demodulation processing is performed using the carrier wave from the control / interface processing unit 19, and the demodulated signal is output to the control / interface processing unit 19. The control / interface processing unit 19 performs the same control processing as the input signal,
Output to the D / A converter 14. The D / A converter 14 converts the clock signal output from the clock oscillator 16 into an analog signal and outputs the analog signal as a demodulated wave. Memory 1
Reference numeral 7 is used for temporarily storing data or a program.

[0040]

As described in detail above, according to the demodulation processing method of the present invention, a different communication system (modulation method,
Hardware that can be shared by controlling the sampling clock and controlling the carrier frequency with software by the DSP. In addition, there is an advantage that versatility is remarkably improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a receiving device of the present invention.

FIG. 2 is a configuration diagram of a digital signal processing portion of the receiving device of the present invention.

FIG. 3 is a configuration diagram of a conventional receiving device.

FIG. 4 is a configuration diagram of a digital signal processing portion of a conventional receiving device.

FIG. 5 is a sampling waveform diagram of a band signal.

FIG. 6 is a diagram showing an example of a carrier frequency table.

[Description of Signs] 1 ... Transmission / reception switch 2, 2 ... High frequency amplifier, 3 ... Carrier generator, 4 ... Frequency converter, 5 ... A / D converter, 6 ... PLL
Oscillator, 7: sampling frequency control unit, 8: processor for digital signal processing (DSP), 9: BPF (band-pass filtering), 10: AGC (automatic gain control) control / amplification processing unit, 11: AGC (automatic) Gain control) detector, 12
... Carrier generator, 13 ... Demodulation processing unit, 14 ... D / A converter, 15 ... Low frequency amplifier, 16 ... Clock oscillator, 17
... memory, 18 ... carrier frequency calculation / control unit, 19 ... control / interface processing unit.

Claims (2)

[Claims] A high frequency (HF) band, a very high frequency (VHF) band,
Digital signal processor (DSP) in a radio receiving apparatus that performs demodulation processing, band-pass filtering (BPF) processing, and frequency number conversion processing of a received signal in an ultra high frequency (UHF) band
And an analog / digital converter (A / D converter) for converting the signal to be processed from an analog signal to a digital signal
And a digital / analog converter (D / A converter) for converting a signal processed by the DSP from a digital signal to an analog signal. The center frequency and bandwidth information of the HF, VHF, UHF band reception signal are provided. To control the frequency of the PLL oscillator or the variable frequency divider that divides the output of the PLL oscillator and the oscillator, based on the result of the calculation of the sampling frequency, and controls the sampling frequency of the A / D converter. Means for converting an analog signal into a digital signal at a sampling frequency lower than twice the highest frequency input to the A / D converter, and a frequency lower than the center frequency of the signal input to the A / D converter at the sampling frequency. Calculate the carrier frequency and perform demodulation using the carrier wave of the digital signal processing that has been frequency converted. Radio receiving apparatus characterized in that a demodulation processing method having a step, the. 2. The radio receiving apparatus according to claim 1, wherein
A radio receiving apparatus characterized in that the demodulation processing method has a memory for storing a table of carrier frequencies for demodulation processing.