JP2001223278A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory capable of realizing a decrease in a voltage of rewriting and assuring reliability of a storage such as a charge storage or the like without decelerating the rewriting speed. SOLUTION: A source region 2 and a drain region 3 are separately formed on a surface layer of a semiconductor substrate 1. A floating gate electrode 6 is disposed on the substrate 1 between the regions 2 and 3 via a tunnel insulating film 5. A control gate electrode 8 is disposed on the electrode 6 via an insulating film 7 between the gate layers. As a material of the film 5 and the film 7, an oxide film is used. A thickness t of the film 5 is 100 Å or more, and a thickness t' of the film 7 is less than 100 Å.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a nonvolatile semiconductor memory, and more particularly, to a nonvolatile semiconductor memory utilizing an FN tunneling current when rewriting data.

[0002]

2. Description of the Related Art FIG. 7 shows a configuration example of a nonvolatile semiconductor memory such as a flash memory. The memory cells 100 are arranged in a matrix, and each memory cell 100 has a large number of bits. FIG. 8 shows a basic configuration of the memory cell 100. A source region 21 and a drain region 22 for each cell are formed separately from each other in a surface layer portion of the semiconductor substrate 20, and a floating gate electrode (floating gate) is formed on the semiconductor substrate 20 between the two regions 21 and 22 via a tunnel insulating film 23. An electrode) 24 and a control gate electrode (control gate electrode) 26 on the floating gate electrode 24 via a gate interlayer insulating film 25.
Is extended, and the drain region 22 of each cell is connected to a bit line,
The source region 21 is connected to a source line, and the control gate electrode 26 is connected to a word line.

In a read operation, as shown in FIG. 8, a positive potential of 1 to 2 volts is applied to a drain region 22, a source region 21 is grounded, Vcc is applied to a control gate electrode 26, and a channel current flows. This is done by detecting whether or not it is not.

[0004] Data writing is performed as shown in FIG.
Vcc is applied to the drain region 22, the source region 21 is grounded, a high voltage Vpp (for example, +12 volts) is applied to the control gate electrode 26, hot electrons are generated near the drain, and the generated hot electrons are transferred to the floating gate. This is performed by injecting into the electrode 24 to increase the threshold voltage of the memory cell. That is,
At the time of writing, the drain region 22 of the selection transistor
, An intermediate potential Vcc (for example, 5.5 volts) higher than the ground potential source region 21 is applied, and at the same time, a higher potential Vpp (for example, 12 volts) than the drain potential is applied to the control gate electrode 26 of the selection transistor. By doing so, hot electrons are generated near the drain, and injected into the floating gate electrode 24.

In erasing data, as shown in FIG. 10, a high positive voltage (for example, +12 volts) is applied to the source region 21, the control gate electrode 26 is grounded,
This is performed by extracting electrons of the floating gate electrode 24 into the source region 21 by a tunnel effect. At this time, the drain region 22 is open.

Alternatively, as shown in FIG. 11, a negative high voltage (for example, -8 volts) is applied to the control gate electrode 26.
May be applied by applying a positive high voltage (for example, +10 volts) to the source region 21 and the substrate 20 to extract electrons of the floating gate electrode 24 to the substrate 20 region by a tunnel effect.

As described above, the erasing and writing operations of the flash memory are performed by passing the FN tunneling current to the tunnel insulating film 23. Therefore, conventionally, the thickness of the tunnel insulating film 23 has been reduced in order to facilitate the flow of current in the tunnel insulating film 23 and to improve the rewriting speed.

In the future, further miniaturization and lower power consumption will progress,
Accordingly, in the situation where the rewriting voltage must be lowered, further improvement in the thickness of the tunnel insulating film is required in order to secure a rewriting speed higher than the current state.

However, there is a limit to the thinning of the tunnel insulating film from the viewpoint of the leak current, and there is a limit to the thinning of the tunnel insulating film in terms of memory reliability such as charge retention due to minute leakage. However, it is becoming difficult to make the thickness of the tunnel insulating film thinner than the current thickness (a commonly used value is, for example, about 100 °).

Recently, the field of use of non-volatile semiconductor memory has been widened, and the environment in which the memory is used has become severe. Accordingly, it is necessary to ensure reliability at higher temperatures. Conventional film thickness (for example, 100
Ii) In some cases, it has to be made thicker.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and it is an object of the present invention to secure memory reliability such as charge retention and reduce rewriting voltage without reducing rewriting speed. It is an object of the present invention to provide a non-volatile semiconductor memory capable of realizing the structure.

[0012]

In the case of data erasing in FIG. 10, the electric field strength E of the tunnel insulating film 23 in the memory cell can be obtained from the capacitance coupling ratio.
Specifically, as shown in FIG. 6, the voltage applied to the tunnel insulating film 23 is V, the thickness of the tunnel insulating film 23 is t,
The applied voltage to the source region 21 is Vs, the applied voltage to the control gate electrode 26 is V _CG , the capacitance between the control gate electrode 26 and the floating gate electrode 24 is C1, the floating gate electrode 24 and the source region 21
Assuming that the capacitance between the two is C2 and the amount of charge in the floating gate electrode 24 is Qf,

[0013]

(Equation 1) Becomes

C1 and C2 greatly depend on the vertical and horizontal dimensions of the memory transistor structure.

[0015]

(Equation 2) Can be described.

Here, as is apparent from the above equation (2), the C1 value largely depends on the gate interlayer thickness t ', and the smaller the gate interlayer thickness t', the smaller the value of C1. Becomes larger. As a result, the V / t value and the E value increase as is apparent from the above-described equation (1). Therefore,
Even if the thickness t of the tunnel is increased in order to ensure high reliability, if the thickness t ′ of the gate interlayer is reduced, the electric field strength E of the tunnel insulating film can be ensured, and a decrease in the rewriting speed can be suppressed. It becomes possible.

Further, although becomes smaller (Vs -V _CG) when you try to lower the smaller to rewrite voltage value E value in the formula (1), the higher the C1 value t 'value is less as described above increases, it becomes possible to reduce the no (Vs -V _CG) value causing a decrease in the E value.

In consideration of the above, according to the first aspect of the present invention, the thickness of the tunnel insulating film and the thickness of the tunnel insulating film in the case where both insulating films are converted into the same material are used as the film thickness of the tunnel insulating film and the gate interlayer insulating film. It is characterized in that the thickness of the gate interlayer insulating film is made thinner. Therefore, it is possible to secure the reliability of the memory such as charge retention and reduce the voltage of rewriting without reducing the rewriting speed.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of the flash memory, and FIG. 2 is a sectional view taken along line AA of FIG.

As shown in FIG. 2, P as a semiconductor substrate
In the single-crystal silicon substrate 1, a P-type silicon layer 1a
Is formed with a P-well layer 1b. An N ⁺ type source region (impurity diffusion region) 2 and an N ⁺ type drain region (impurity diffusion region) 3 for each cell are provided in the surface layer portion of the P well layer 1b.
Are formed apart from each other. Further, the P well layer 1b
In FIG. 1, a band-like N ⁺
A source common line (impurity diffusion region) 4 extends, and the source region 2 of each memory cell is connected to the source common line 4. More specifically, as an N-type impurity, for example, As
(Arsenic). The N-type impurity region is formed by thermal diffusion after introducing As ions into the inside by ion implantation.

As shown in FIG. 2, a floating gate electrode (floating gate electrode) 6 made of polycrystalline silicon is provided on the single crystal silicon substrate 1 via a thin silicon oxide film 5 as a tunnel insulating film. The floating gate electrode 6 has a rectangular shape and
And the drain region 3 is extended.
More specifically, the floating gate electrode 6 is formed on the silicon oxide film 5 so as to cover the end portions of the N-type impurity regions 2 and 3. Floating gate electrode 6
A strip-shaped control gate electrode (control gate electrode) 8 is arranged on the upper surface of the semiconductor device via a silicon oxide film 7 as a gate interlayer insulating film. The control gate electrode 8 is made of polycrystalline silicon, and extends in parallel with the source common line 4 as shown in FIG.

As shown in FIG. 2, a silicon oxide film 9 is disposed on the single crystal silicon substrate 1 including the periphery of the control gate electrode 8. Silicon oxide film 9
A drain wiring 11 made of aluminum is disposed on the substrate, and the drain wiring 11 is formed in a contact hole (opening).
10, it is electrically connected to the drain region 3. In the present embodiment, a drain contact hole 10 common to two transistor cells is provided. Further, as shown in FIG. 1, contact holes (openings) 12a, 12b, 1 provided in the silicon oxide film 9 are formed.
Source wiring (not shown) is electrically connected to the source common line 4 through 3a and 13b. In the present embodiment, source contact holes 12a, 12b, 13a, and 13b are provided for every eight transistor cells.

FIG. 3 shows a peripheral circuit. X decoder 1
5 and a Y decoder / sense amplifier / write circuit 16. The X decoder 15 has word lines 1, 2, 3,.
n and j are connected to the control gate electrode 8 of each cell. The Y decoder / sense amplifier / write circuit 16 is connected to the drain region 3 of each cell via bit lines 1, 2, 3,..., M, k. The Y decoder / sense amplifier / write circuit 16 has source lines 1, 2, 3,.
, M and k are connected to the source region 2 of each cell.

The operation of the flash memory, that is, the read operation, the write operation, and the erase operation are described with reference to FIGS.
This is the same as that described with reference to 10 and 11, and the description thereof is omitted.

Here, when the data shown in FIG. 10 is erased, the floating gate electrode 6 and the source region 2 shown in FIG.
The electrons move in the overlap region between the two.
In this embodiment, the gate interlayer insulating film (silicon oxide film)
The thickness t ′ of the tunnel insulating film (silicon oxide film) 5
Is thinner than the film thickness t. Specifically, the thickness t of the tunnel insulating film 5 is set to 100 ° or more, and the thickness t ′ of the gate interlayer insulating film 7 is set to less than 100 °.
More specifically, for example, the thickness t of the tunnel insulating film 5 is set to 110 ° and the thickness t ′ of the gate interlayer insulating film 7 is set to 70 °.
And

FIG. 4 shows the dependence of the tunnel thickness and the gate interlayer thickness on the erase time. The horizontal axis of the figure indicates the film thickness of the gate interlayer insulating film 7, the vertical axis indicates the erasing time, and the film thickness t of the tunnel insulating film 5 is set to 150 °, 120 °, 110 °.
{, 100}, 90 ° are shown. Also, the control gate voltage Vcg = 0 volts and the source voltage Vs = 1
It is 2 volts. Note that both the tunnel insulating film and the gate interlayer insulating film are oxide films. From FIG. 4, for example,
Until now, in order to realize an erasing time of 10 msec, for example, the thickness t of the tunnel insulating film 5 should be set to 100 ° and the thickness of the gate interlayer insulating film 7 should be set to about 200 °.

However, if the tunnel thickness t is simply increased in order to ensure reliability at a high temperature as described in the prior art, the erasing time will be long. Specifically, in FIG. 4, for example, when the tunnel film thickness t is 110 °, the erasing time is about 300 msec.

FIG. 5 shows that the source voltage V
The erasing time when the voltage is reduced by setting s to 10 volts is shown. Other conditions are the same as those in FIG. In the case of FIG. 5, when the thickness t of the tunnel insulating film 5 is 100 ° and the thickness of the gate interlayer insulating film 7 is 200 °, the erase time is about 1000 m.
sec and 10 msec cannot be realized.

On the other hand, in the present embodiment, even if the tunnel film thickness t is increased to secure high reliability, an erasing time of 10 msec can be realized by reducing the gate interlayer film thickness t '. Specifically, in FIG. 4, for example, even if the tunnel thickness t is set to 110 °, the gate interlayer thickness t ′ is set to 110 °.
With a smaller thickness, an erasing time of 10 msec can be realized. In FIG. 5 (when the voltage is reduced), for example, even if the tunnel thickness t is 110 °, if the gate interlayer thickness t ′ is smaller than about 70 °, an erasing time of 10 msec can be realized.

As described above, by making the gate interlayer thickness t 'smaller than the tunnel thickness t, (i) high memory reliability can be secured without reducing the rewriting speed. (Ii) The rewrite voltage can be reduced without reducing the rewrite speed.

As described above, this embodiment has the following features. (A) When a silicon oxide film is used as the material of the tunnel insulating film 5 and the gate interlayer insulating film 7, the thickness t 'of the gate interlayer insulating film 7 is larger than the thickness t of the tunnel insulating film 5.
, The reliability of the memory such as charge retention can be ensured and the voltage for rewriting can be reduced without reducing the rewriting speed.

In the description so far, the tunnel insulating film and the gate interlayer insulating film have been compared as the same film (oxide film). However, in many cases, the gate interlayer insulating film is not formed with only one oxide film. Specifically, the tunnel insulating film is formed by thermally oxidizing the substrate, and the gate interlayer insulating film is also formed by forming the floating gate electrode and then thermally oxidized to form only one oxide film. In many cases, it has a three-layer structure of / nitride film / oxide film. Recently, a tunnel insulating film may have a multilayer structure of a nitride film and an oxide film. Thus, even when the same insulating film is used to form a multilayer structure using different dielectric constants such as an oxide film and a nitride film, the same film (for example, an oxide film) is converted into a film having a thickness greater than the tunnel thickness t. The thickness t ′ of the gate interlayer is reduced.

As described above, instead of using the same material (oxide film) as the material of the tunnel insulating film and the gate interlayer insulating film, an oxide film and a nitride film are used as at least one of the material of the tunnel insulating film and the gate interlayer insulating film. The thickness of the tunnel insulating film and the gate interlayer insulating film, including this case, may be used as the film thickness of the tunnel insulating film when both insulating films are converted to the same material. May be reduced.

In the above description, a flash memory has been described. However, the present invention may be applied to a nonvolatile semiconductor memory such as an EEPROM in addition to the flash memory.

[Brief description of the drawings]

FIG. 1 is a plan view of a flash memory according to an embodiment;

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a circuit diagram showing an electrical configuration of a peripheral circuit.

FIG. 4 is a diagram showing the dependency of a tunnel film thickness and a gate interlayer film thickness on an erase time.

FIG. 5 is a diagram showing the dependence of a tunnel film thickness and a gate interlayer film thickness on an erase time.

FIG. 6 is a diagram showing an electrical equivalent circuit of a memory cell.

FIG. 7 is a diagram showing a cell arrangement of a flash memory.

FIG. 8 is a cross-sectional view of a memory for explaining a read operation;

FIG. 9 is a cross-sectional view of a memory for explaining a writing operation.

FIG. 10 is a cross-sectional view of a memory for explaining an erasing operation.

FIG. 11 is a cross-sectional view of a memory for explaining an erase operation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P-type single crystal silicon substrate, 2 ... source region, 3 ... drain region, 4 ... source common line, 5 ... tunnel insulating film (silicon oxide film), 6 ... floating gate electrode,
7: gate interlayer insulating film (silicon oxide film); 8: control gate electrode.

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Claims (4)

[Claims] A source region and a drain region are formed in a surface layer portion of a semiconductor substrate with a space therebetween, and a floating gate electrode is disposed on the semiconductor substrate between the two regions via a tunnel insulating film, and a floating gate electrode is provided. A nonvolatile semiconductor memory having a control gate electrode disposed thereon with a gate interlayer insulating film interposed therebetween, wherein the thickness of the tunnel insulating film and the gate interlayer insulating film is the same as the thickness of both insulating films when converted to the same material. A non-volatile semiconductor memory, wherein the thickness of the gate interlayer insulating film is smaller than the thickness of the film. 2. The nonvolatile semiconductor memory according to claim 1, wherein an oxide film is used as a material of said tunnel insulating film and said gate interlayer insulating film. 3. The thickness of the tunnel insulating film is set to 100 ° or more, and the thickness of the gate interlayer insulating film is set to 10 ° or more.
3. The non-volatile semiconductor memory according to claim 2, wherein said non-volatile semiconductor memory is less than 0 °. 4. The nonvolatile semiconductor memory according to claim 1, wherein a laminate of an oxide film and a nitride film is used as at least one of the tunnel insulating film and the gate interlayer insulating film.