JP2001203445A - Method of manufacturing printed wiring board and jig for flattening - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a printed wiring board which can conduct a highly accurate flattening processing, while the occurrence of cracks in the board are avoided. SOLUTION: A solder resist layer 70, having an opening part 70a, is formed on the board 30. The opening part 70a on the chip-loading face-side of the substrate 30 is filled with solder paste and it is made to reflow. Then, solder bumps 76 are formed. The top parts of the solder bumps 76 are flattened and are made to uniform heights by the flattening processing for adding pressure force to the thickness direction of the substrate 30 by using a pair of jigs 11 and 12. Electronic components 14 are loaded on the chip non-loading face 10a-side of the substrate 30. A part release recessed part 13 for releasing the electronic components 14 is installed on the substrate abutting face 11a of the jib 11 which presses the chip non-loading face 10a-side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and a flattening jig used for manufacturing a printed wiring board.

[0002]

2. Description of the Related Art In general, a solder resist layer is formed on a surface layer on a chip mounting side surface of a substrate constituting a printed wiring board in order to protect a conductor circuit. Openings are formed at a plurality of positions in the solder resist layer, and pads that are a part of the conductor circuit are arranged therein. A hemispherical solder bump is provided on the pad. Usually, the above-mentioned solder bump is formed by providing a nickel plating layer, a gold plating layer, or the like on a pad, and then printing and filling a solder paste, followed by reflow. By mounting an IC chip on a printed wiring board using such bumps, the IC chip side and the printed wiring board side are electrically connected.

However, when a large number of minute solder bumps are to be formed, the height position of the top tends to vary. Therefore, the solder bumps having the reduced top portions have insufficient contact with the terminals on the IC chip side, and as a result, it is difficult to ensure high connection reliability between the IC chip side and the printed wiring board side. Become.

[0006] Therefore, a measure has been proposed in which, after reflow is performed to form solder bumps, the bump formation area on the chip mounting surface is pressed in the thickness direction of the substrate using a jig. It is considered that such a flattening process flattens the tops of the solder bumps so that all the tops have a uniform height.

[0005]

However, if the substrate 1
If the flattening process is performed with one jig 103 without supporting and fixing the central portion of the lower surface (non-chip mounting surface) 102 side of the substrate 01 at all, the central portion of the substrate may be bent by the pressing force (FIG. 13). Therefore, solder bump 1
It is difficult to make the tops of the 04s uniform, and the accuracy of fluttering also decreases.

To solve this problem, for example, FIG.
As shown in FIG. 4, the chip non-mounting surface 10 of the substrate 101
It is conceivable that the center part of No. 2 should be supported and fixed by using another jig 105, and in this state, a pressing force should be applied from both sides. However, a small electronic component 106 such as a capacitor may be mounted on the chip non-mounting surface 102 at a position just opposite to the bump formation area. In this case, the jig 105 does not include the substrate 101 but the electronic component 106.
Abuts. Here, since the constituent material of the electronic component 106 has a certain degree of hardness, even if a large pressing force is applied, the possibility that the electronic component 106 itself is broken is not so large. On the other hand, for the insulating layer and the like of the substrate 101, a resin material which is relatively brittle than a material for electronic components is usually used. Therefore, when the fluttering process is performed, the pressing force provided by the jig 105 is concentrated on a specific portion such as the insulating layer via the electronic component 106, and as a result, there is a problem that the insulating layer or the like is easily cracked.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a method of manufacturing a printed wiring board capable of performing a highly accurate fluttering process while avoiding the occurrence of cracks in a substrate. It is an object of the present invention to provide a jig for shining.

[0008]

In order to solve the above-mentioned problems, according to the present invention, a solder resist layer having a plurality of openings is formed on a substrate having a conductor circuit, and then the substrate is provided with a plurality of openings. After forming a plurality of solder bumps by filling a solder paste into the opening on the chip mounting surface side and reflowing, by applying a pressing force in the thickness direction of the substrate using a pair of jigs, In the method of manufacturing a printed wiring board for performing a flattening process of flattening a top portion of the solder bump to have a uniform height, when an electronic component is mounted on the chip non-mounting surface side of the substrate, the chip non-mounting surface The gist of the present invention is a method for manufacturing a printed wiring board, characterized in that a component escape recess for allowing the electronic component to escape is provided on a substrate contact surface of a jig for pressing the side. .

According to a second aspect of the present invention, in the first aspect, the jig is made of a hard and pressure-resistant material.
According to a third aspect of the present invention, in the first or second aspect,
It is assumed that one component escape recess is provided corresponding to a plurality of electronic components.

According to a fourth aspect of the present invention, in the thirteenth aspect, a convex portion is provided on a bottom surface of the component escape concave portion so as to be in contact with the chip non-mounting surface side of the substrate.
According to the invention as set forth in claim 5, a jig on the chip non-mounting surface side used in a fluttering process for applying a pressing force in a thickness direction of the substrate to flatten the top portion of the solder bump to have a uniform height. The gist of the present invention is a fluttering jig provided with a component escape recess on the substrate contact surface.

Hereinafter, the "action" of the present invention will be described. According to the first and fifth aspects of the present invention, since the pressing force is applied from both sides of the substrate, the substrate is less likely to bend, and highly accurate fluttering processing can be performed. Further, at the time of the fluttering process, since the electronic component can escape to the component escape recess provided on the substrate contact surface of the jig, the electronic component does not directly contact the substrate contact surface. Therefore, the pressing force does not concentrate on a specific portion such as an insulating layer via the electronic component. Therefore, cracks are less likely to occur on the substrate.

According to the second aspect of the invention, if the jig is made of a hard and pressure-resistant material, the jig is not deformed or broken by the pressing force at the time of the fluttering process. . Therefore, the fluttering process can be performed with higher accuracy.

According to the third aspect of the present invention, if one part-relief recess is provided for each of a plurality of electronic components, the production becomes simpler than the case where the part-relief recess is provided for each individual electronic component. Also, high cost is prevented.

According to the fourth aspect of the present invention, since the convex portion comes into contact with the chip non-mounting surface side of the substrate, the substrate becomes more difficult to bend. Therefore, the fluttering process can be performed with higher accuracy.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a printed wiring board by a semi-additive method according to one embodiment of the present invention will be described below.

First, a printed wiring board having a conductor circuit is formed on the surface of a substrate. As the substrate, a resin substrate such as a glass epoxy substrate, a polyimide substrate, a bismaleimide-triazine resin (BT resin) substrate, a ceramic substrate,
A metal substrate or the like can be used. An adhesive layer for electroless plating is formed on this substrate. The surface of the adhesive layer is roughened, and the entire roughened surface is subjected to thin electroless plating. Subsequently, a plating resist is formed on the roughened surface of the resin insulating layer. Thick electrolytic plating is applied to the non-formed portions of the plating resist. Next, after the unnecessary plating resist is removed, an etching process is performed to form a conductor circuit including the electrolytic plating film and the electroless plating film. Copper is preferably used for forming the conductor circuit.

On the substrate on which the conductor circuits are formed, plated through holes for conducting the front and back conductor circuits are formed. The plating through hole is filled with a resin filler, and an unnecessary portion of the resin filler exposed from the opening of the plating through hole is removed by grinding after drying.

Next, the conductor circuit exposed on the surface of the substrate is provided with a roughened surface. The roughened surface is preferably formed by etching, polishing, oxidizing, or redox-treating the surface of a conductor circuit made of copper. The roughened surface may be formed by providing a plating film on the surface of the conductor circuit.

The adhesive for electroless plating used in the present embodiment includes a heat-resistant resin particle soluble in a cured acid or oxidizing agent, and an uncured heat-resistant resin hardly soluble in an acid or oxidizing agent. What is dispersed inside is optimal. The reason is that when the above adhesive is used, the heat-resistant resin particles are dissolved and removed by treating with an acid and an oxidizing agent, so that a roughened surface having an octopus pot-shaped anchor can be easily obtained. is there.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles which have been particularly cured include (1) a heat-resistant resin powder having an average particle diameter of 10 μm or less, and (2) a heat-resistant resin powder having an average particle diameter of 2 μm or less. Agglomerated particles obtained by aggregating heat-resistant resin powder, (3) a mixture of a heat-resistant resin powder having an average particle diameter of 2 to 10 μm and a heat-resistant resin powder having an average particle diameter of 2 μm or less,
(4) pseudo particles obtained by adhering at least one of a heat-resistant resin powder having an average particle size of 2 μm or less and an inorganic powder to the surface of a heat-resistant resin powder having an average particle size of 2 to 10 μm; A mixture of a heat-resistant resin powder having a particle diameter of 0.1 to 0.8 μm and a heat-resistant resin powder having an average particle diameter of more than 0.8 μm and less than 2 μm, (6) an average particle diameter of 0.1 to 0.8 μm
It is desirable to use at least one of a heat-resistant resin powder of 1.0 μm. This is because, if these are used, an anchor having a more complicated shape can be formed.

As the heat-resistant resin hardly soluble in an acid or an oxidizing agent, a “resin composite composed of a thermosetting resin and a thermoplastic resin” or a “resin composite composed of a photosensitive resin and a thermoplastic resin” is used. It is desirable to use. The advantage of the former is that it has better heat resistance than the others. An advantage of the latter is that a via hole forming hole can be formed with high precision by photolithography.

As the thermosetting resin, epoxy resin, phenol resin, polyimide resin and the like can be used. When it is desired to impart photosensitivity to the resin, an acrylate reaction between methacrylic acid, acrylic acid, or the like and a thermosetting group is performed. In this case, it is particularly desirable to use an acrylate of an epoxy resin.

As the epoxy resin, novolak type epoxy resins such as phenol novolak type and cresol novolak type, and alicyclic epoxy resin modified with dicyclopentadiene can be used.

As the thermoplastic resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PP
E), polyetherimide (PI) and the like can be used.

The mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is set in the range of thermosetting resin (photosensitive resin) / thermoplastic resin = 95/5 to 50/50. Good. Within this range, a high toughness value can be ensured without impairing the heat resistance.

The mixing ratio of the heat-resistant resin particles is preferably 5% by weight to 50% by weight, more preferably 10% by weight to 40% by weight, based on the solid content of the heat-resistant resin matrix. As the heat-resistant particles, an amino resin (melamine resin, urea resin, guanamine resin), an epoxy resin, or the like is preferably used.

The adhesive may be composed of two layers having different compositions. Next, after performing a curing treatment, holes for forming via holes are formed in the resin insulating layer derived from the adhesive for electroless plating.

When the resin matrix of the adhesive for electroless plating is a thermosetting resin, the holes are perforated using laser light, oxygen plasma or the like. When the resin matrix of the adhesive for electroless plating is a photosensitive resin, the holes are formed by exposure and development. In the exposure and development process, a photomask made of a glass substrate on which a circular pattern is drawn is brought into close contact with the photosensitive resin insulating layer, and is exposed and exposed.
Development takes place.

Next, the surface of the resin insulating layer (adhesive layer for electroless plating) provided with holes for forming via holes is roughened. In particular, in the present embodiment, the surface of the adhesive layer is roughened by dissolving and removing the heat-resistant resin particles present on the surface of the adhesive layer for electroless plating with an acid or an oxidizing agent.

In the acid treatment, an inorganic acid such as hydrochloric acid or sulfuric acid can be used, and an organic acid such as formic acid or acetic acid can be used. In particular, it is desirable to use an organic acid. The reason is that it is difficult to corrode the metal conductor layer exposed from the via hole during the roughening treatment.

In the oxidation treatment, it is desirable to use chromic acid or permanganate (such as potassium permanganate). The maximum roughness of the roughened surface obtained by the roughening treatment (Rm
ax) is preferably 0.1 μm to 20 μm. If the maximum roughness is too large, the roughened surface itself is easily damaged or peeled. Conversely, if the maximum roughness is too small, the adhesion will decrease. In particular, in the semi-additive method as in the present embodiment, the maximum roughness is preferably set to about 0.1 μm to 5 μm. The reason is that in this range, the electroless plating film can be removed while maintaining the adhesion.

Next, after providing a catalyst nucleus on the roughened surface,
A thin electroless plating film is formed on the entire surface of the resin insulating layer.
This electroless plating film is preferably formed by electroless copper plating. The thickness of the electroless copper plating film is 1μ.
m to 5 μm, and particularly preferably 2 μm to 3 μm. As the electroless copper plating bath, those having a general liquid composition can be used.

Specifically, for example, copper sulfate: 29
g / l, sodium carbonate: 25 g / l, EDTA: 14
It is preferable to use a liquid composition comprising 0 g / l, sodium hydroxide: 40 g / l, and 37% formaldehyde: 150 ml (PH = 11.5).

Next, a photosensitive resin film (dry film) is laminated on the thus formed electroless plating film. On this photosensitive resin film, a photomask on which a plating resist pattern is further drawn is arranged in close contact with it. By performing exposure and development processing in this state, a plating resist having a predetermined pattern is formed.

Next, an electroplating film is formed on a portion of the electroless copper plating film where a resist is not formed, thereby providing a conductor circuit and a conductor portion serving as a via hole. As the electrolytic plating, electrolytic copper plating is desirable. Further, the thickness of the electroless copper plating film is preferably set to 10 μm to 20 μm.

Next, after the unnecessary plating resist is removed, the electroless plating film located under the plating resist is removed by etching. As a result, an independent conductor circuit having a two-layer structure composed of the electroless plating film and the electrolytic plating film and a via hole having the same two-layer structure are obtained. In the etching, a mixed solution of sulfuric acid and hydrogen peroxide, an etching solution such as sodium persulfate, ammonium persulfate, ferric chloride, and cupric chloride are used. The palladium catalyst nucleus provided on the roughened surface is dissolved and removed by chromic acid, sulfuric acid and hydrogen peroxide.

Next, a roughened surface is formed on the surface layer of the conductor circuit. The roughened surface is desirably formed by etching, polishing, oxidizing, oxidizing and reducing a conductor circuit made of copper, or by plating.

Next, a solder resist layer is formed on the conductor circuit. The thickness of the solder resist layer in the present embodiment is preferably 5 μm to 40 μm. If the solder resist layer is too thin, it may not function as a dam for preventing the flow of solder. Conversely, if the solder resist is too thick, it becomes difficult to form an opening and cracks are more likely to occur on the solder side due to contact with the solder.

For the formation of the solder resist layer, bisphenol A type epoxy resin, bisphenol A type epoxy resin acrylate, novolak type epoxy resin, novolak type epoxy resin acrylate were cured with an amine type curing agent or an imidazole curing agent. Resin or the like can be used.

In particular, when a solder bump is formed in an opening provided in a solder resist layer, use of a novolak type epoxy resin or an acrylate of a novolak type epoxy resin containing an "imidazole curing agent" as a curing agent is required. preferable. The reason is that the solder resist layer having such a configuration has an advantage that migration of lead (a phenomenon in which lead ions diffuse in the solder resist layer) is small. Moreover, since the solder resist layer having such a configuration is a resin layer obtained by curing an acrylate of a novolak type epoxy resin with an imidazole curing agent, it has excellent heat resistance and alkali resistance.
Further, the solder resist layer is not deteriorated even at a temperature at which the solder melts (around 200 ° C.), and is not decomposed by a strongly basic plating solution such as nickel plating or gold plating.

Since such a solder resist layer is made of a resin having a rigid skeleton, peeling is likely to occur. However, the occurrence of such peeling is prevented by the presence of the roughened surface formed on the surface layer of the conductor circuit.

Here, as the acrylate of the novolak type epoxy resin, an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid, methacrylic acid or the like can be used.

The imidazole curing agent is desirably liquid at 25 ° C. The reason is that the liquid can be uniformly mixed. Such liquid imidazole curing agents include 1-benzyl-
2-methylimidazole (trade name: 1B2MZ), 1-
Cyanoethyl-2-ethyl-4-methylimidazole (trade name: 2E4MZ-CN) and 4-methyl-2-ethylimidazole (trade name: 2E4MZ) can be used.

The amount of the imidazole curing agent added is 1% by weight based on the total solid content of the solder resist layer composition.
Desirably, it is 10 to 10% by weight. The reason is that if the added amount is within this range, it is easy to mix uniformly.

As the solvent for the composition before curing the solder resist layer, it is desirable to use a glycol ether-based solvent. The reason is that it becomes a solder resist layer in which free oxygen is hardly generated, and it becomes difficult to oxidize the surface of the pad made of copper.

As such a glycol ether solvent, those having the following structural formula (1) are desirable, and further, diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMT)
At least one selected from G) is particularly desirable.

CH ₃ O— (CH ₂ CH ₂ O) _n —CH ₃ (n = 1 to 5) (1) The reason is that by heating to 30 ° C. to 50 ° C., these solvents In addition, benzophenone and Michler's ketone, which are reaction initiators, can be completely dissolved. The amount of the glycol ether solvent is 10% by weight to 4% by weight based on the total weight of the solder resist composition.
It is preferably 0% by weight.

The solder resist layer composition described above includes, in addition to the above, various antifoaming agents, leveling agents, thermosetting resins for improving heat resistance and base resistance and imparting flexibility, and improving resolution. For example, a photosensitive monomer can be added.

For example, as the leveling agent, one made of a polymer of an acrylate ester is preferable. As an initiator, "Irgacure I907" manufactured by Ciba-Geigy is used.
(Trade name) "and Nippon Kayaku's" DE "as a photosensitizer.
TX-S (product name). " Further, a dye or pigment may be added to the solder resist layer composition. The reason is that the coloring makes the wiring pattern less noticeable. It is desirable to use phthalocyanine green as such a dye.

As the thermosetting resin as an additional component, an A-type or F-type bisphenol-type epoxy resin can be used. The former is preferably selected when importance is placed on base resistance, and the latter is preferably selected when lower viscosity is required (when importance is placed on applicability).

As the photosensitive monomer which is an additive component, a polyacrylic monomer can be used. The reason is that the resolution can be improved by adding a polyvalent acrylic monomer. In particular,
It is desirable to use a polyacrylic monomer having a structure such as "DPE-6A (trade name)" manufactured by Nippon Kayaku Co., Ltd. or "R-604 (trade name)" manufactured by Kyoeisha Chemical Co., Ltd.

The viscosity of these solder resist layer compositions is 0.5 Pa · s to 10 Pa at 25 ° C.
S, more preferably 1 Pa · s to 10 Pa · s. The reason is that such a setting results in a viscosity that facilitates application with a roll coater.

After the formation of the solder resist layer as described above, openings are formed at predetermined locations by exposure and development. Next, a nickel plating layer is formed on the conductor circuit located at the opening of the solder resist layer by electroless plating. Examples of the nickel plating solution include nickel sulfate 4.5 g / l and sodium hypophosphite 25 g.
/ L, sodium citrate 40g / l, boric acid 12g /
1, thiourea having a composition of 0.1 g / l (PH = 11) is used.

Next, the inner wall surface of the opening of the solder resist layer is cleaned by treating it with a degreasing solution. Thereafter, a catalyst such as palladium is applied to the conductor portion exposed at the opening. Further, after activating the catalyst, the substrate is immersed in a plating solution to form a nickel plating layer on the conductor.

The thickness of the nickel plating layer is 0.5 μm to
The thickness is preferably 20 μm, particularly preferably 3 μm to 10 μm. If it is less than 0.5 μm, it will be difficult to establish a connection between the solder bump and the nickel plating layer. Conversely, if the thickness exceeds 20 μm, the solder bump may not completely fit in the opening, and the solder bump may be easily peeled.

Next, a gold plating layer having a thickness of about 0.03 μm is formed on the nickel plating layer by electrolytic gold plating. After forming the metal plating layer on the opening, a mask material is disposed on the solder resist layer on the chip mounting surface, and in this state, the solder paste is printed and filled in the plurality of openings. Thereafter, the solder bumps are fixed in the openings by reflow under a nitrogen atmosphere. At this point, the solder bump has a hemispherical shape.

As the solder paste for forming the solder bumps, those generally used for printed wiring boards can be used. Specifically, Pb-Sn
(Eg, Pb: Sn in the range of 9: 1 to 4: 6), Sn—Ag, Sn—Ag—Cu
It is desirable to use a system-based, Sn-Cu-based, or Sn-Sb-based one. In addition, Sn: Pb = 63:
When using a eutectic solder having a composition of 37, the reflow is preferably performed at 200 ° C to 230 ° C. Sn: Ag
= 96.5: 3.5 when a solder having a composition of:
The reflow is preferably performed at 200 ° C to 230 ° C.

The melting point of the solder paste is desirably less than 280 ° C. If the melting point exceeds 280 ° C., the resin used for the resin insulation layer and the solder resist layer may be dissolved, and the resin insulation layer and the conductor circuit may be peeled off, and the conductor circuit may be disconnected. Further, since the time required for heating is long, workability is deteriorated.

The viscosity of the solder paste is 100 Pa · s
It is preferable to set the pressure to 300 Pa · s. If the viscosity is too low, the solder bump cannot be maintained in a desired shape. Conversely, if the viscosity is too high,
This is because the solder paste cannot be efficiently filled into the opening.

At the position just opposite the bump formation area on the chip non-mounting surface of the substrate, several pads for connecting electronic components are formed by the above-described plating or the like. Small electronic components such as a chip capacitor, a chip resistor, a chip transistor, and a chip diode are joined to these pads via a solder layer. Further, on the outer peripheral side of the area where the pads for connecting electronic components are formed,
A large number of pads for connecting terminal pins are formed by the above-described technique such as plating. And these pads have
The terminal pins are joined via a solder layer.

Subsequently, a flattening process is performed using a pair of jigs (a lower jig 11 and an upper jig 12) as described below. As shown in FIG. 1, a lower jig 11, which is a jig for pressing the lower surface (non-chip mounting surface) 10a side of the printed wiring board 10, is made of a hard and pressure-resistant metal material such as stainless steel. Preferably, The advantages of metal materials are that they are relatively inexpensive and have excellent workability. Of course, a ceramic material such as silicon nitride can be used as long as it is hard and pressure-resistant.

Upper surface 11 of lower jig 11 (that is, substrate contact surface) 11
A component escape recess 13 for allowing the electronic component 14 to escape is provided at a substantially central portion of “a”. In the present embodiment, only one component escape recess 13 is provided corresponding to a plurality of electronic components 14.

Here, the depth of the component escape recess 13 is larger than the height of the largest one of the plurality of electronic components 14.
It is set to be at least 1 mm larger. The external shape of the component escape recess 13 is rectangular here, and its size is set to be large enough to surround the plurality of electronic components 14. The component relief recess 13 can be formed by counterboring. Of course, the part escape recess 13 may be formed by die molding or the like.

Then, the lower jig 11 thus configured
The printed wiring board 10 is placed horizontally on the upper surface (that is, the substrate contact surface 11a). At this time, the substrate contact surface 11
The outer peripheral portion a directly contacts the chip non-mounting surface 10a of the substrate 30. On the other hand, the central portion of the board contact surface 11a, that is, the place where the component escape recess 13 is provided, does not directly contact the board 30 or the electronic component 14.

On the other hand, the upper jig 1 is a jig for pressing the upper surface (chip mounting surface) 10b side of the printed wiring board 10.
2 is also preferably made of a hard and pressure-resistant metal material such as stainless steel, like the lower jig 11. Such an upper jig 12 is arranged above the center of the printed wiring board 10. The outer dimensions of the upper jig 12 are the chip mounting surface 1
The bump formation area is set to be equal to or larger than the bump formation area at 0b. Unlike the lower jig 11, the lower surface of the upper jig 12 (that is, the substrate contact surface 12a) is formed flat. The substrate contact surfaces 11a and 12a of the jigs 11 and 12 may be coated with a release agent for preventing solder paste from adhering.

The jigs 11 and 12 are driven in a vertical direction by a driving device (not shown). In this case, the lower jig 1
Only 1 may be driven, only the upper jig 12 may be driven, or both 11 and 12 may be driven.

Then, in the fluttering process,
By applying a pressing force in the thickness direction of the substrate using these jigs 11 and 12, the tops of the solder bumps 76 are flattened to have a uniform height.

It is desirable that the fluttering treatment is performed under heating rather than at room temperature. The reason is that the solder is softened under heating, so that the top of the solder bump 76 can be easily flattened even with a small pressing force. When performing the fluttering process under heating, it is desirable that one or both jigs 11 and 12 include a heating unit such as an electric heater. The heating means is jig 1
In addition to the jigs 11 and 12,
May be provided in the vicinity.

The temperature during the fluttering treatment is 60 ° C.
~ 10 ℃ lower than the melting point of the solder used (liquidus
If there is a solidus, the temperature is preferably set to 10 ° C. lower than the liquidus. When the temperature is lower than 60 ° C., the solder bumps 76 are not sufficiently softened, so that it is necessary to apply a large pressing force, which may lead to breakage of the solder bumps 76. On the other hand, if the melting point is exceeded, the solder bump 76 is melted, and a suitable shape as the solder bump 76 may be damaged. Further, there is a possibility that a bridge may occur between the molten solder bumps 76. When eutectic solder (Sn: Pb = 63: 37) is selected, the temperature is desirably set to 100 ° C to 160 ° C.

The pressing force during the fluttering process is 10 k
It may be set within the range of gf / cm ^{2 to} 150 kgf / cm ² . Within the above range, the solder bump 7
This is because the top of No. 6 can be flattened most efficiently. If the pressing force is less than 10 kgf / cm ² , the top of the solder bump 76 cannot be reliably flattened. Conversely, if the pressing force is higher than 150 kgf / cm ² , the solder bumps 76 may be damaged. The pressing force is 30 kgf / cm ^{2 to} 100 kgf / cm ²
It is more desirable to set within the range.

The time of pressurization by the jigs 11 and 12 is preferably set within 2 minutes, and more preferably within 1 minute. If the pressurization time exceeds 2 minutes,
In addition to a decrease in productivity, heat may be transmitted too much and lead to breakage of the solder bumps 76.

The height of the top of the solder bump 76 after the fluttering process (specifically, the height t1 of the top based on the conductor circuit exposed from the solder resist layer) is 5 μm to 100 μm. Preferably
In particular, it is desirable that the thickness be 10 μm to 50 μm.

Note that the preferable height t1 of the top part slightly differs depending on the thickness of the solder resist layer. For example, when the thickness of the solder resist layer is 20 μm, the height of the top is desirably set to 20 μm to 70 μm in order to improve the height uniformity and the reliability of connection. That is, it is desirable that the amount of the solder bump 76 projecting from the solder resist layer is set to 0 μm to 50 μm. If the protrusion amount is less than 0 μm, the solder bump 76 and the terminal on the IC chip side are likely to be unconnected. Conversely, if the amount of protrusion exceeds 50 μm, it is difficult to make the height t1 of the top of the solder bump 76 uniform. In addition, the size of the solder bump 76 itself must be increased, and a short circuit may easily occur after heating.

After the above-described fluttering treatment, a desired printed wiring board can be obtained through a dividing process for individual pieces, a plasma treatment step, and a check step for inspecting a short circuit / break of wiring.

[0075]

EXAMPLES AND COMPARATIVE EXAMPLES Hereinafter, a build-up multilayer printed wiring board 10 of Example 1 which embodies the present embodiment and a method of manufacturing the same will be described with reference to FIGS.

First, the multilayer printed wiring board 10 of the present embodiment
Is described. As shown in FIG. 2, a conductor circuit 34 is formed on an upper surface and a lower surface of the substrate 30 constituting the multilayer printed wiring board 10. Buildup layers 80A and 80B are formed on these conductor circuits 34, respectively. Each of the build-up layers 80A and 80B includes two resin insulating layers 50 and 91. Via holes 60 are formed in the resin insulating layer 50 located on the inner layer side, and conductive circuits 58 are formed on the upper surface of the resin insulating layer 50. Via holes 93 are formed in the resin insulating layer 91 located on the outer layer side, and a conductor circuit 92 is formed on the upper surface of the resin insulating layer 91.

Solder resist layers 70 and 71 are further formed on the outer layers of the via holes 93 and the conductor circuits 92. A plurality of openings 70a and 71a are formed at predetermined positions of the solder resist layers 70 and 71, respectively. Solder bumps 76 are formed on conductor circuits 92 or via holes 93 located on the bottom surface of opening 70a on the upper surface side.
Are formed. On the other hand, a solder layer is formed on the conductor circuit 92 or the via hole 93 located on the bottom surface of the opening 71a on the lower surface side.

A flat surface 77 is formed on the upper surface of the multilayer printed wiring board 10, that is, on the top of the solder bump 76 on the chip mounting surface 10b side. The pad and the IC chip 1 are connected via these solder bumps 76.
6 terminals (not shown) are joined. An electronic component 14 such as a chip capacitor or the like is joined to the lower surface of the multilayer printed wiring board 10, that is, the solder layer 78 on the side of the non-chip mounting surface 10a, which is located at the center of the substrate. T-type terminal pins 15 are joined to the solder layer 78 located at the outer peripheral portion of the substrate. Note that these terminal pins 15 are connected to a socket on the daughter board (not shown). The tops of all the solder bumps 76 on the upper surface side of the multilayer printed wiring board 10 are flattened by a fluttering process. As a result, the height t1 of the top is 20
μm. Therefore, IC
While holding the chip 16 in a horizontal state, the IC chip 16
Are securely bonded to the solder bumps 76.

Subsequently, the multilayer printed wiring board 1 of the present embodiment
0 will be described in the order of steps with reference to FIGS. Here, first, the multilayer printed wiring board 1 of the embodiment is used.
A.0 used in the production method of A.0. Adhesive for electroless plating,
B. Interlayer resin insulation, C.I. Resin filler, D.I. The composition of the raw material composition for the solder resist layer will be described. A. Raw Material Composition for Adjusting Adhesive for Electroless Plating (Adhesive for Upper Layer) [Resin Composition (1)] 80% by weight of 25% acrylate of cresol novolac type epoxy resin (Nippon Kayaku Co., Ltd., molecular weight 2500) 35 parts by weight of a resin solution dissolved in DMDG at a concentration of 3.35 parts by weight of a photosensitive monomer (manufactured by Toagosei Co., Ltd., trade name: Aronix M315), an antifoaming agent (manufactured by San Nopco, trade name: S-65) ) 0.5 parts by weight,
3.6 parts by weight of NMP were mixed under stirring to obtain a resin composition (1).
I got

[Resin Composition (2)] Polyethersulfone (PES) 12 parts by weight, average particle size of epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd .: polymer pole) 1.0 μm
After mixing 7.2 parts by weight of m and 3.09 parts by weight of an average particle diameter of 0.5 μm, 30 parts by weight of NMP was further added, and the mixture was stirred and mixed with a peas mill to obtain resin composition (2). I got

[Curing agent composition (3)] 2 parts by weight of an imidazole curing agent (trade name: 2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of a photoinitiator (trade name: Irgacure I-907, manufactured by Ciba Geigy) , Photosensitizer (Nippon Kayaku Co., Ltd.,
0.2 parts by weight of trade name: DETX-S) and 1.5 parts by weight of NMP were stirred and mixed to obtain a curing agent composition (3). B. Raw Material Composition for Adjusting Interlayer Resin Insulating Agent (Adhesive for Lower Layer) [Resin Composition (1)] 80% by weight of 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) 35 parts by weight of a resin solution dissolved in DMDG, 4 parts by weight of a photosensitive monomer (manufactured by Toagosei Co., Ltd., trade name: Aronix M315), and 0.5 of an antifoaming agent (manufactured by San Nopco, trade name: S-65) Parts by weight, NMP
3.6 parts by weight were stirred and mixed to obtain a resin composition (1).

[Resin Composition (2)] 12 parts by weight of polyether sulfone (PES) and an average particle diameter of 0.5 of epoxy resin particles (manufactured by Sanyo Chemical Industries, trade name: polymer pole)
μm, 14.49 parts by weight, and further mixed with N
30 parts by weight of MP was added, and the mixture was stirred and mixed with a peas mill.
A resin composition (2) was obtained.

[Curing agent composition (3)] 2 parts by weight of an imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-CN), 2 parts by weight of a photoinitiator (manufactured by Ciba Geigy, trade name: Irgacure I-907) Part, photosensitizer (Nippon Kayaku Co., Ltd.
0.2 parts by weight of trade name: DETX-S) and 1.5 parts by weight of NMP were stirred and mixed to obtain a curing agent composition (3). C. Raw material composition for adjusting resin filler [Resin composition (1)] bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., molecular weight 310, trade name: YL9)
83U) 100 parts by weight, spherical particles of SiO ₂ having an average particle diameter of 1.6 μm coated with a silane coupling agent on the surface (manufactured by Admatech, trade name: CRS 1101)
-CE, where the size of the largest particle is not more than the thickness (15 μm) of the inner layer copper pattern described later) 170 parts by weight,
Leveling agent (manufactured by San Nopco, trade name: Perenol S)
4) 1.5 parts by weight were stirred and mixed. The viscosity of the resulting mixture is 45,000 cps-49,000 at 23 ± 1 ° C.
The resin composition was adjusted to cps to obtain a resin composition (1).

[Curing Agent Composition (2)] As the curing agent composition (2), 6.5 parts by weight of an imidazole curing agent (trade name: 2E4MZ-CN, manufactured by Shikoku Chemicals Co., Ltd.) was used. D. Raw material composition for solder resist layer 50% epoxy group of cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) of 60% by weight dissolved in DMDG
Of a photosensitizing agent (molecular weight 40
80) of bisphenol A type epoxy resin (manufactured by Yuka Shell Co., trade name: Epicoat 1001) in which 46.67 g of 46.67 g was dissolved in methyl ethyl ketone 15.0.
g, imidazole curing agent (Shikoku Chemicals, trade name: 2E)
4MZ-CN) 1.6 g, polyvalent acrylic monomer as photosensitive monomer (Nippon Kayaku Co., Ltd., trade name: R604) 3
g, 1.5 g of a polyvalent acrylic monomer (manufactured by Kyoeisha Chemical Co., Ltd., trade name: DPE6A) and 0.71 g of a dispersion defoaming agent (manufactured by San Nopco, trade name: S-65). Then, 2 g of benzophenone (manufactured by Kanto Kagaku) as a photoinitiator and 0.2 g of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixture, and the viscosity was 2.0 Pa · s. (25 ° C.) to obtain a solder resist composition.

The viscosity was measured using a B type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.). In this case, 6
At 0 rpm, the rotor no. 4 and 6 rpm
In rotor No. 3 was used.

Subsequently, a multilayer printed wiring board 10 is manufactured using the above composition. (1) First, a copper-clad laminate 30A as shown in FIG. 3A was prepared as a starting material. The copper-clad laminate 30A of the present embodiment is formed by laminating a 18-μm copper foil 32 on both sides of a substrate 30 made of a glass epoxy resin or a BT (bismaleimide-triazine) resin having a thickness of 1 mm. This copper-clad laminate 30A is drilled with a drill,
A hole for forming a through hole was formed. Thereafter, after performing an electroless copper plating treatment, the copper foil 32 and the copper plating layer were etched in a pattern. As a result, as shown in FIG. 3 (b), an inner conductor circuit (specifically, an inner copper pattern) 34 is formed on both upper and lower surfaces of the substrate 30, and a plated through hole 36 for conducting the conductor circuit 34 is formed. Was formed.

(2) Substrate 3 on which conductor circuit 34 and the like are formed
Was washed with water and dried. Then, NaOH (10 g / l) .NaClO ₂ (40 g) was used as an oxidation bath (blackening bath).
/L).Na ₃ PO ₄ (6 g / l), Na as a reducing bath
Oxidation with OH (10g / l) · NaBH 4 (6g / l) - was reduced processing. As a result, as shown in FIG. 3C, the conductor circuit 34 and the plated through hole 36 are formed.
Was provided with a roughened surface 38.

(3) The resin filler 40 was obtained by mixing and kneading the previously prepared “C. Raw material composition for preparing resin filler”. (4) The resin filler 4 within 24 hours after preparation
By applying 0 to the substrate 30, the space between the conductor circuits 34 and the inside of the plated through holes 36 were filled with the resin filler 40.

In the present embodiment, application was performed by a printing method using a squeegee. In the first printing application step, the resin filler 40 was mainly filled in the plating through holes 36.
Thereafter, the temperature in the drying furnace was set to 100 ° C., and the applied resin filler 40 was dried for 20 minutes.

In the second printing application step, the resin filler 40 was filled in the recesses between the conductor circuits 34, which are mainly conductor circuits. Thereafter, the resin filler 40 was dried under the aforementioned drying conditions (see FIG. 3D).

(5) After the filling step of (4), one surface of the substrate 30 is polished with a belt abrasive paper (manufactured by Sankyo Rikagaku KK, #
600) by a belt sander polishing.
At this time, the surface of the conductor circuit 34 or the plated through hole 3
Care was taken not to leave the resin filler 40 on the surface of the land 36a of No. 6. Next, buffing was performed to remove scratches generated by belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate 30 (see FIG. 4A). Then at 100 ° C. for 1 hour,
A heat treatment at 150 ° C. for 1 hour is performed to obtain a resin filler 40
Was cured.

As described above, both surfaces of the substrate 30 were smoothed by removing the surface layer of the resin filler 40 filled in the plated through holes 36 and the like and the surface layer of the upper surface of the conductor circuit 34. That is, through this step, the resin filler 4
0 and the surface of the conductor circuit 34 are at the same height.

(6) Substrate 30 on which conductor circuit 34 is formed
After degreasing with an alkali, the substrate 30 was treated with a catalyst solution comprising palladium chloride and an organic acid to apply a Pd catalyst to the surface. After activating this catalyst, the substrate 30 was immersed in an electroless copper plating solution. Plating solution used herein, copper sulfate 3.9 × 10- ² mol / l, nickel sulfate 3.8 × 10- ³ mol / l, sodium citrate 7.8 × 10- ³ mol / l, hypophosphorous sodium phosphate 2.3 × 10- ¹ mol / l, the surfactant (Nisshin chemical industry Co., Ltd., trade name: Sir feel 65) 1.1 × 10-
^{It has} a composition of ⁴ mol / l (PH = 9).

One minute after the immersion, vibration was applied in the vertical and horizontal directions once every four seconds. As a result, a coating layer of a needle-like alloy made of Cu-Ni-P and a roughened layer 42 were provided on the surfaces of the lands 36a of the conductive circuits 34 and the plated through holes 36 (see FIG. 4B).

Further, tin borofluoride 0.1 mol / l
And a solution consisting of 1.0 mol / l thiourea and
By treating at 5 ° C. and PH = 1.2,
Copper was replaced with tin. As a result of such a Cu—Sn substitution reaction, a 0.3 μm thick Sn layer (not shown) was provided on the surface of the roughened layer 42.

(7) The previously prepared “B. Raw material composition for preparing interlayer resin insulating agent” is stirred and mixed, and the viscosity is adjusted to 1.5 Pa · s, whereby the interlayer resin insulating agent (lower layer 44) was obtained.

Next, the previously prepared “A. Raw material composition for preparation of adhesive for electroless plating” was stirred and mixed, and the viscosity was adjusted to 7 Pa · s, whereby the adhesive for electroless plating was prepared. A solution (for upper layer) 46 was obtained.

(8) The interlayer resin insulating material (for lower layer) 44 having the predetermined viscosity obtained in the above (7) is applied to both surfaces of the substrate 30 having undergone the above step (6) within 24 hours after preparation by a roll coater. And applied. The substrate 30 was left in a horizontal state for 20 minutes, and then dried (prebaked) at 60 ° C. for 30 minutes. Next, the photosensitive adhesive solution (for upper layer) 46 having a predetermined viscosity obtained in the above (7) was further applied to both surfaces of the substrate 30 within 24 hours after the preparation. The substrate 30
Was left in a horizontal state for 20 minutes, and dried (prebaked) at 60 ° C. for 30 minutes to finally form an adhesive layer 50α having a thickness of 35 μm (see FIG. 4C).

(9) In the step (8), the adhesive layer 5
A photomask film 51 on which a black circle 51a of 85 μmφ was printed was brought into close contact with both surfaces of the substrate 30 on which 0α was formed. In this state, 500 mJ / c with an ultra-high pressure mercury lamp
Exposure was performed at an intensity of m ² (see FIG. 4D). This is DM
Spray development using a TG solution,
Was exposed at an intensity of 3000 mJ / cm ² by an ultra-high pressure mercury lamp. Next, heat treatment (post-baking) was performed at 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours. Through such a series of exposure and development processes, a 35-μm-thick resin insulating layer (two-layer structure) 50 having 85 μmφ via-holes 48 with excellent dimensional accuracy was formed (see FIG. 5A). . In the via hole forming hole 48, a tin plating layer (not shown) was partially exposed.

(10) The substrate 30 on which the holes 48 are formed
Was immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the resin insulating layer 50. As a result of such a roughening treatment, a roughened surface 46a having a large number of irregularities was formed on the surface layer of the resin insulating layer 50 (see FIG. 5B). Thereafter, the substrate 30 was immersed in a neutralizing solution (manufactured by Shipley) and then washed with water.

Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate 30 which has been subjected to the roughening treatment, the catalyst is applied to the roughened surface 46a of the resin insulating layer 50 and the inner wall surface of the via hole forming hole 48. A nucleus was provided.

(11) The substrate 30 is immersed in an electroless copper plating solution having the following composition to form an electroless copper plating film 5 having a thickness of 0.6 μm to 1.2 μm over the roughened surface 46 a.
No. 2 was formed (see FIG. 5C). Here, the temperature of the plating solution was set to 65 ° C., and the immersion time was set to 20 minutes.

[Composition of Electroless Plating Solution] EDTA 0.08 mol / l Copper sulfate 0.03 mol / l HCHO 0.05 mol / l NaOH 0.05 mol / l α, α'-bipyridyl 80 mg / l PEG 0.10 g / l (12) A commercially available photosensitive dry film was attached on the electroless copper plating film 52 formed in the thin plating step of (11). In this state, 100 mJ / cm ²
And then developed with 0.8% sodium carbonate. As a result of such exposure and development processing, a plating resist 54 having a thickness of 15 μm was formed on the surface layer of the substrate 30 (see FIG. 5D).

(13) Next, an electrolytic copper plating film 56 having a thickness of 15 μm was formed on the non-resist-formed portion under the following conditions (FIG. 6A).
reference). Here, the current density is set to 1 A / dm ² ,
The immersion time was set to 65 minutes, and the liquid temperature was set to 22 ± 2 ° C.

[Composition of electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (manufactured by Atotech Japan Co., Ltd., trade name: Capalaside HL) 19.5 ml / l (14) Plating resist After exfoliating and removing 54 with 5% KOH, the electroless plating film 52 under the plating resist 54 was dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. As a result, a thickness of 18 μm (10 to 10) consisting of the electroless plating 52 film and the electrolytic copper plating film 56
30 μm) were obtained (see FIG. 6B).

Further, the surface of the electroless plating adhesive layer 50 between the conductor circuits 58 was etched by about 1 μm by immersing the substrate 30 in 80 g / l chromic acid set at 70 ° C. for 3 minutes. As a result, the palladium catalyst on the surface of the adhesive layer 50 was removed.

(15) By performing the same processing as in the above (6), a roughened surface 62 made of Cu-Ni-P is formed on the surfaces of the conductor circuit 58 and the via hole 60, and Sn
Substitution was performed (see FIG. 6 (c)).

(16) By repeating the above steps (7) to (14), a second resin insulating layer 91, via holes 93, and conductor circuits 92 were formed. Further, a roughened surface 94 was formed on the surface of the via hole 93 and the conductor circuit 92 (see FIG. 6D). Note that the upper conductor circuit 92
Was not substituted in the step of forming.

(17) The substrate 30 obtained in the above (16)
The above-mentioned “D. Raw material composition for solder resist layer” was applied to both sides of the sample at a thickness of 20 μm (see FIG. 7A).
Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a thickness of 5 mm on which a circular pattern is drawn
The photomask film (not shown) was brought into close contact with the substrate 30. In this state, it was exposed to ultraviolet light having an intensity of 1000 mJ / cm ² and developed with DMTG. 8 more
1 hour at 0 ° C, 1 hour at 100 ° C, 1 hour at 120 ° C,
Heat treatment was performed at 150 ° C. for 3 hours. As a result, openings 70a and 71a (opening diameter 2
Then, solder resist layers 70 and 71 having a thickness of 20 μm and having a thickness of 00 μm, respectively, were formed (see FIG. 7B).

(18) Thereafter, nickel chloride 2.3 × 1
0- ¹ mol / l, sodium hypophosphite 2.8 × 10
- ¹ mol / l, sodium citrate 1.6 × 10- ¹ m
The substrate 30 was immersed in an electroless nickel plating solution having a pH of 4.5 and consisting of ol / l for 20 minutes. As a result, a nickel plating layer 72 having a thickness of 5 μm was formed on the pads located at the openings 70a and 71a.

Further, the substrate 30 was coated with 7.6 × 10 ⁻³ mol / l of potassium gold cyanide, 1.9 × 10 ⁻¹ mol / l of ammonium chloride, and 1.
2 × l0- ¹ mol / l, sodium hypophosphite 1.7
× was immersed in an electroless gold plating solution consisting of 10- ¹ mol / l. The liquid temperature was set to 80 ° C., and the immersion time was set to 7.5 minutes. As a result, a gold plating layer 74 having a thickness of 0.03 μm was formed on the nickel plating layer 72 (FIG. 8A).
reference).

(19) Next, a mask material (not shown) is brought into close contact with the solder resist layer 70 on one side of the substrate 30, and in this state, a solder paste is placed on a pad or the like located in the opening 70a. (Sn: Pb = 63: 37) was printed.

Further, after the substrate 30 is inverted, a mask is brought into close contact with the solder resist layer 71 on the other side,
In this state, solder paste (Sn: Sb = 95: 5) was printed on the pads for connecting electronic components and the pads for connecting terminal pins located in the opening 71a. Then, by mounting the electronic component 14 using a chip mounter, the electronic component 14 was temporarily fixed on a pad for connecting the electronic component using the viscosity of the solder paste. Thereafter, the terminal pins 15 were erected using a dedicated pin erection jig, and the head of the terminal pins 15 was temporarily fixed on the terminal pin connection pads using the viscosity of the solder paste. Here, the viscosity of the solder paste was set to 200 Pa · s.

Then, by reflowing the substrate 30 at 260 ° C., the hemispherical solder bumps 7 are formed in the openings 70a.
6 was formed. At the same time, the electronic component 14 and the terminal pin 1 are connected to the pad in the opening 71a via the solder layer 78.
5 (see FIG. 8B).

Instead of the collective reflow as described above, for example, the following may be performed. 1) After reflowing the C4 bump at 230 ° C., flux cleaning is performed, and after solder printing of electronic components and pins, reflow is performed at 260 ° C. again. That is,
Perform reflow twice. 2) To prevent the solder of electronic components and pins from melting during IC chip assembly,
Electronic components and pins are connected using solder having a higher melting point than 4 bumps.

(20) Next, a flattening process was performed using the pair of stainless steel jigs 11 and 12 having the above-described structure under the following conditions. In the present embodiment, the jigs 11 and 12 each having an electric heater (not shown) are selected, and both the jigs 11 and 1 are energized by energizing the electric heater.
2 was heated to 100 ° C. for use.

First, the lower jig 11 was placed with the substrate contact surface 11a facing upward. Then, after positioning the plurality of electronic components 14 so as to be exactly arranged in the component escape recesses 13, the multilayer printed wiring board 10 is placed on the board contact surface 11 a.
Was placed horizontally (see FIG. 1B). As a result, the outer peripheral portion of the substrate contact surface 11a supported the chip non-mounting surface 11a of the substrate 30 (more specifically, a region between the component mounting area and the pin formation area on the surface).

Then, the upper jig 12 is moved down in the vertical direction to apply a pressing force in the thickness direction of the substrate 30, thereby flattening the top of the solder bump 76 to have a uniform height. (See FIGS. 1 and 9 (b)). In this embodiment, the pressing force is set to 50 kgf / cm ² ,
The pressurization time was set to 30 seconds.

As a result, a flat surface 77 having an area of about 50 μm ² as shown in FIG. 10 was formed on the top of the solder bump 76 obtained through the above processing. The height t1 of the top of each solder bump 76 is 20 μm.
And they were evenly aligned.

After the above-described fluttering treatment, a desired build-up multilayer printed wiring board 10 was obtained through an individual dividing step, a plasma treatment step, and a check step of inspecting for short-circuit and disconnection of wiring. [Embodiment 2] In Embodiment 2, the fluttering process was performed at normal temperature (about 25 ° C) without supplying electricity to the electric heaters of the jigs 11 and 12. Otherwise, a build-up multilayer printed wiring board 10 was manufactured basically in accordance with Example 1. Comparative Example 1 In Comparative Example 1, a lower jig made of stainless steel having a flat substrate contact surface (see FIG. 14) was used in place of the jig 11 of Example 1, and the same conditions as in Example 1 were used. Performed fluttering treatment. Otherwise, a build-up multilayer printed wiring board 10 was manufactured basically in accordance with Example 1. [Comparative Example 2] In Comparative Example 2, instead of the jig 11 of Example 1, a lower jig made of stainless steel having a flat substrate contact surface (see FIG. 14) was used. Further, the pressing force in the fluttering process is considerably smaller than that in the first embodiment (5 k
gf / cm ² ). Otherwise, a build-up multilayer printed wiring board 10 was manufactured basically in accordance with Example 1. [Method and Result of Comparative Test] Regarding the multilayer printed wiring boards 10 obtained in Examples 1 and 2 and Comparative Examples 1 and 2, first, the height t1 (average value and tolerance (μ
m)) was measured. After the mounting of the IC chip 16, the occurrence rate (%) of unbonding between the solder bump 76 and the terminal on the IC chip 16 side was examined. Furthermore, after a heat cycle, a conduction test was performed to determine the quality of the conduction state. Table 1 shows the results.

Further, by observing the chip non-mounting surface 10a side of the substrate 30 with the naked eye and a microscope, the occurrence of cracks in the resin portion such as the solder resist layer 71 was examined.

[0122]

[Table 1] For Examples 1 and 2, the top of the solder bump 76
Flat surface 77 having a sufficient area for mounting IC chip 16
Could be formed. In addition, the height t1 of the top of the solder bump 76 has been uniformed through the fluttering process. Therefore, the electrical connection between the terminals of the IC chip 16 and the solder bumps 76 was ensured. In addition, the conduction state after the heat cycle was extremely good, and it was found that the multilayer printed wiring board 10 had high reliability. In addition, the chip non-mounting surface 10a
No crack was generated in the resin portion on the side.

Also in Comparative Example 1, a flat surface 77 having a sufficient area for mounting the IC chip 16 could be formed on the top of the solder bump 76. In addition, the height t1 of the top of the solder bump 76 was made uniform, and the conduction state after the heat cycle was good. However, the resin portion on the chip non-mounting surface 10a side, in particular, the electronic component 1
In the vicinity of the corner of No. 4, the occurrence of a crack originating therefrom was observed. Therefore, it was hard to say that the multilayer printed wiring board 10 of Comparative Example 1 was excellent in reliability.

In Comparative Example 2, cracks did not occur in the resin portion due to insufficient pressing force in the fluttering process. However, due to insufficient pressing force, a flat surface 77 having a sufficient area for mounting the IC chip 16 could not be formed on the top of the solder bump 76. In addition, the height t1 of the top of the solder bumps 76 cannot be made uniform, and the first and second embodiments have different heights.
The tolerance was large compared to the others. For this reason, the conduction state after the heat cycle was not good. Therefore, it was hard to say that the multilayer printed wiring board 10 of Comparative Example 2 was also excellent in reliability.

Therefore, according to Examples 1 and 2 of the present embodiment, the following effects can be obtained. (1) In the first and second embodiments, since the pressing force is applied from both the upper and lower surfaces of the substrate 30, the substrate 30 is hardly bent. For this reason, compared with the case where only the upper jig 12 is used,
Highly accurate fluttering processing can be performed. In other words, the tops of the solder bumps 76 can be flattened so that all the tops have a uniform height. Therefore, if connection is made by the solder bumps 76 in this state, high reliability can be ensured at that portion.

In the flattening process, the lower jig 1
Component escape recess 13 provided on one substrate contact surface 11a
In addition, the electronic component 14 can be reliably released. Therefore, the electronic component 14 does not directly contact the substrate contact surface 11a. Therefore, the pressing force does not concentrate on a specific portion such as an insulating layer via the electronic component 14. Accordingly, cracks are less likely to occur in the substrate 30, and the multilayer printed wiring board 10 having excellent reliability can be obtained.

(2) In the first and second embodiments, the jigs 11 and 12 made of hard and pressure-resistant stainless steel are used. Therefore, the jigs 11 and 12 themselves are not deformed or broken by the pressing force at the time of the fluttering process. Therefore, the fluttering process can be performed with higher accuracy.

(3) In the first and second embodiments, only one component escape recess 13 is provided corresponding to the plurality of electronic components 14. Therefore, the manufacturing of the lower jig 11 is simpler than the case where the component escape recess 13 is provided for each individual electronic component 14, and the cost of the lower jig 11 is prevented from being increased accordingly. As a result, cost increase of the multilayer printed wiring board 10 is also prevented.

The embodiment of the present invention may be modified as follows. As in another example of the lower jig 11 shown in FIG. 11, a rib 18 may be provided on the bottom surface of the component escape recess 13 as a protrusion that contacts the chip non-mounting surface side of the substrate 30. In such a configuration, the upper surface of the rib 18 abuts on the central portion on the chip non-mounting surface 10a side, so that the portion is supported from below. For this reason, the substrate 30 is harder to bend than in the embodiment. Therefore, the fluttering process can be performed with higher accuracy. The shape of the projection is not limited to the rib 18, and may be, for example, a pillar.

As in another example of the lower jig 11 shown in FIG. 12, a buffer layer 19 made of a material softer than a jig material such as stainless steel is provided on the substrate contact surface 11a in FIG. It may be provided. In this case, it is preferable that a buffer layer 19 is also provided on the upper surface of the rib 18. As a material of the buffer layer 19, a resin represented by a silicone resin or the like, rubber, or the like is preferable. In particular, it is preferable to use an elastic body such as rubber. With such a configuration, it is possible to prevent the substrate 30 from being damaged, and to evenly apply a pressing force to the substrate 30.

The multilayer printed wiring board 10 may be manufactured by a semi-additive method as in the embodiment, or may be manufactured by a full-additive method. Further, the multilayer printed wiring board 10 has a build-up layer 80.
A, 80B may be provided only on one side, or may not be provided at all.

When a plurality of electronic components 14 are mounted, a component escape recess 13 may be provided for each electronic component 14. That is, it is also possible to provide a plurality of component escape recesses 13 on the board contact surface 11a.

The upper jig 12 does not necessarily have to be a flat plate, and may be, for example, a roller. next,
In addition to the technical ideas described in the claims, technical ideas grasped by the above-described embodiments are listed below together with their effects.

(1) In any one of claims 1 to 5, a soft material (for example, an elastic body) is provided on the substrate contact surface. Therefore, this technical idea 1
According to the invention described in (1), it is possible to prevent the substrate from being damaged and equalize the pressing force.

(2) In Claims 1 and 2, the component escape recesses are provided corresponding to individual electronic components. (3) In Claims 2 to 4, the jig is made of pressure-resistant steel. Therefore, according to the invention described in the technical idea 3, the flattening process does not cause deformation or destruction,
The fluttering process can be performed with higher accuracy. In addition, since it is excellent in workability, it is possible to process and form the component escape recess relatively easily and inexpensively.

[0136]

As described in detail above, according to the first aspect of the present invention, there is provided a method of manufacturing a printed wiring board capable of performing high-precision fluttering processing while avoiding the occurrence of cracks in a substrate. Can be provided.

According to the second and fourth aspects of the present invention, the fluttering process can be performed with higher accuracy. According to the third aspect of the invention, the manufacturing of the jig is simplified and the cost is prevented from being increased. As a result, the cost of the printed wiring board can be prevented from being increased.

According to the fifth aspect of the present invention, it is possible to provide a fluttering jig capable of performing a highly accurate fluttering process while avoiding the occurrence of cracks in a substrate.

[Brief description of the drawings]

FIG. 1A is a perspective view illustrating a use state of a fluttering jig according to an embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view taken along line AA.

FIG. 2 is a schematic cross-sectional view showing the entire multilayer printed wiring board of the embodiment.

FIGS. 3A to 3D are schematic cross-sectional views illustrating a manufacturing process of the multilayer printed wiring board according to the embodiment (Example 1).

FIGS. 4A to 4D are schematic cross-sectional views for explaining a manufacturing process.

5 (a) to 5 (d) are schematic cross-sectional views for explaining manufacturing steps in the same manner.

FIGS. 6A to 6D are schematic cross-sectional views for explaining a manufacturing process.

FIGS. 7A and 7B are schematic cross-sectional views for explaining a manufacturing process.

FIGS. 8A and 8B are schematic cross-sectional views for explaining a manufacturing process.

9A is an enlarged cross-sectional view of a solder bump before fluttering processing, and FIG. 9B is an enlarged cross-sectional view of a solder bump after fluttering processing.

FIG. 10 is an enlarged sectional view of a solder bump after a fluttering process.

FIG. 11 is a schematic cross-sectional view showing a use state of another example of a flattening jig.

FIG. 12 is a schematic cross-sectional view illustrating a use state of another example of the flattening jig.

FIG. 13 is a schematic cross-sectional view showing a state of a fluttering process when only one fluttering jig is used in the related art.

FIG. 14 is a schematic cross-sectional view showing a state of a fluttering process when a pair of flattening jigs is used in the related art.

[Explanation of symbols]

Reference numeral 10: build-up multilayer printed wiring board as a printed wiring board; 10a: chip non-mounting surface; 11: (lower) jig; 11a: (lower) jig substrate contact surface; 12: (upper) jig; 12a: (upper) jig substrate contact surface, 13: component escape recess, 14: electronic component, 19: rib as projection, 3
0: substrate, 34: conductor circuit, 70: solder resist layer, 70a: opening, 76: solder bump.

Claims (5)

[Claims] A solder resist layer having a plurality of openings is formed on a substrate having a conductive circuit, and a solder paste is filled in the openings on the chip mounting surface side of the substrate and reflowed to form a plurality of solder resist layers. After forming the solder bumps, the printed wiring is subjected to a flattening process for flattening the tops of the solder bumps to have a uniform height by applying a pressing force in the thickness direction of the substrate using a pair of jigs. In the method of manufacturing a board, when an electronic component is mounted on the chip non-mounting surface side of the board, a component escape for allowing the electronic component to escape to a board contact surface of a jig pressing the chip non-mounting surface side. A method for manufacturing a printed wiring board, wherein a concave portion is provided. 2. The method according to claim 1, wherein the jig is made of a hard and pressure-resistant material. 3. The electronic device according to claim 1, wherein the component escape recess is provided for each of a plurality of electronic components.
Or the method for producing a printed wiring board according to 2 above. 4. The method for manufacturing a printed wiring board according to claim 3, wherein a convex portion is provided on the bottom surface of the component escape concave portion so as to contact the chip non-mounting surface side of the substrate. 5. A jig on a chip non-mounting surface side used in a fluttering process for applying a pressing force in a thickness direction of a substrate to flatten a top portion of a solder bump to have a uniform height. A fluttering jig having a component escape recess on its substrate contact surface.