JP2001203370A - Power semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor element allowing required voltage for turning the element to the off state to be lowered to realize a low loss as a power switching element. SOLUTION: The power semiconductor element comprises a first conductivity type source region (1), source electrode (11), gate region (2) and a first conductivity type channel region (9) adjacent to the source region and the gate region on one main surface, a first conductivity type drain region (3), and a second conductivity type interrupt region (20) adjacent the source electrode extending toward the channel region on the other main surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device which performs high-current and high-voltage switching operations used in DC-AC conversion, inverters and the like in power transmission.

[0002]

2. Description of the Related Art A junction field effect transistor (JFET: Junction Field E) used for switching an inverter or the like.
ffect Transistor) is required to withstand high current and high voltage. FIG. 10 is a diagram showing a normal lateral JFET. A ground potential is applied to the source region 101, and a positive potential is applied to the drain region 103. Gate region 10
2, a pn junction is formed, and when the element is turned off, a negative voltage is applied to the gate electrode 112 so that the junction is in a reverse bias state. The electrons in the source region 101 are attracted to the positive potential of the drain region 103, and the channel region 1 under the gate region 102
09 and reaches the drain region 103.

In the above-mentioned lateral JFET, as shown in FIG. 10, since the source, gate and drain electrodes are on the same plane, the drain electrode and another electrode come close to each other via air. The pressure resistance of air is at most 3 kV / mm
Therefore, when a voltage of 3 kV or more is applied between the drain electrode and the other electrode in an OFF state where no current flows, it is necessary to separate the drain electrode from the other electrode by 1 mm or more. For this reason, the length of the channel region 109 from the source region 101 to the drain region 103 becomes longer,
Only a small amount of current can be passed, and a high current required for what is generally called a power transistor cannot be passed.

FIG. 11 shows a vertical JFET proposed and put to practical use in order to improve the above-mentioned disadvantages of the horizontal JFET.
Also known as an electrostatic induction transistor (hereinafter referred to as SIT (Static I
nduction Transistor). SIT
In this embodiment, a plurality of gate regions 102 are formed with p ⁺ regions into which high-concentration p-type impurities are implanted, and around them are formed n ⁻ regions with low-concentration n-type impurities. the n ^- is low n-type impurity concentration in the region, constantly expanding the depletion layer, the channel region is lost. For this reason, the saturation phenomenon of the drain current due to the pinch-off that occurs in the lateral JFET does not occur. The method of applying the potential to each of the source, gate, and drain regions is the same as that of the lateral JFET shown in FIG. The electrons in the source region 1 cross the potential barrier of the gate region and are attracted to the drain potential and drift in the depletion layer. When the drain potential is set to a high positive potential, the potential barrier for electrons in the gate region is reduced, and the drift current can be increased. Even if the drain potential is increased, the drain current does not saturate. Control of the drain current is usually performed by the gate potential and the drain potential. When the SIT shown in FIG. 11 is used for switching, in order to obtain a large current, the voltage must be increased in order to cause electrons to exceed a potential barrier, and even a small loss can be avoided. Did not.

[0005]

Therefore, in order to reduce the loss caused by the switching operation to the utmost and to make the manufacturing easy with a simple structure, a power semiconductor having the structure shown in FIG. The present inventors have proposed a device (Japanese Patent Application No. 11-366799).
In this structure, the gate potential is set to zero or positive with respect to the source potential to turn on. Also, the gate potential is turned off by setting the gate potential to a negative voltage with respect to the source potential.
State. With the structure shown in FIG. 12, high-speed high-voltage switching with extremely low loss is possible.

However, the vertical JFET shown in FIG.
Thus, although a low loss can be realized, it was necessary to apply a high negative voltage between the gate and the source in order to obtain a depletion layer necessary for turning off. This is because the vertical JFET shown in FIG. 12 has a structure in which the electric field in the channel region between the gate region and the source region is not easily increased. Since the absolute value of this negative voltage reaches 10 V or more,
In order to realize even lower loss, there has been a demand for lowering the voltage required for forming a depletion layer.

Accordingly, the present invention provides a switching element for high power, which realizes an even lower loss by using a switching element.
It is an object of the present invention to provide a power semiconductor device capable of lowering a voltage required for setting an FF state.

[0008]

According to a first aspect of the present invention, there is provided a power semiconductor device comprising: a first conductivity type source region provided on one main surface of a semiconductor substrate; A source electrode provided in contact with the source region, a gate region of the second conductivity type provided on one main surface side, a channel region of the first conductivity type in contact with the source region and the gate region, A drain region of the first conductivity type provided on the other main surface; and an interruption region of the second conductivity type in contact with the source electrode and extending toward the channel region.

With this structure, the electric field in the channel region from the portion of the gate region close to the source region toward the source region can be increased. For this reason, the depletion layer extending from the gate region / channel region interface to the channel region is:
It becomes easier to spread toward the source region. As a result, even if a large negative voltage is not applied between the source and the gate, the OF
The F state can be realized, and further low loss can be realized as a switching element for high power.

According to a second aspect of the present invention, in the power semiconductor device of the first aspect, the gate regions are provided on both sides of the channel region.

According to this structure, the depletion layer is extended from the interface between the gate region on both sides of the channel region to the channel region with a lower reverse bias voltage than in the prior art, so that the OF region is more reliably formed.
The F state can be realized.

According to a third aspect of the present invention, in the power semiconductor device of the first or second aspect, the interrupt region extends through the source region and into the channel region.

With this structure, the electric potential of the source electrode extends so as to approach the gate region, and the electric field in the channel region from the gate region to the tip of the interrupt region can be increased. As a result, the formation of a depletion layer in the channel region is facilitated, and the OFF state can be realized by applying a low negative voltage. Further, the withstand voltage performance in the OFF state can be improved.

According to a fourth aspect of the present invention, in the power semiconductor device according to any one of the first to third aspects, the interrupt region is divided into two or more regions with a region of the first conductivity type interposed therebetween.

With the above structure, the depletion layer is more likely to spread from the gate region / channel region interface toward the source electrode, and the OFF state can be realized with a negative voltage having a low absolute value. The two or more regions may be flat or columnar.

According to a fifth aspect of the present invention, in the power semiconductor device according to any one of the first to fourth aspects, a region in the channel region, which is in contact with the gate region and the source region, has a lower concentration than the channel region. A depletion layer promoting region of one conductivity type is provided.

The depletion layer extends from the interface between the gate region and the channel region toward the channel region in substantially proportion to the ratio of the impurity concentration of the second conductivity type in the gate region to the impurity concentration of the first conductivity type in the channel region. Extend. That is, it extends to the side where the impurity concentration is low, almost in proportion to the ratio of the impurity concentration. For this reason, by providing the depletion layer promoting region, it is possible to form the depletion layer by extending the depletion layer longer with a low reverse bias voltage and to combine the depletion layers extending from the gate regions on both sides to realize the OFF state. Becomes In other words, the depletion layers on both sides are unitedly suspended by a negative voltage having a smaller absolute value, so that the passage of charge carriers can be blocked.

According to a sixth aspect of the present invention, in the power semiconductor device according to any one of the first to fifth aspects, the semiconductor substrate is made of SiC.
It has become.

In the above configuration, switching of a large current having a high withstand voltage can be performed. As a result, it can be used as a high-voltage high-speed switching element with high withstand voltage and low loss.

[0020]

Next, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing the structure of an FET according to Embodiment 1 of the present invention. The source electrode 11 and the gate electrode 12 are provided on one main surface of the semiconductor substrate, and the drain electrode 13 is provided on the other main surface. The source region 1 is formed in contact with the source electrode 11, the gate region 2 is formed in contact with the gate electrode 12, and the drain region 3 is formed in contact with the drain electrode 13. The channel region 9 is provided in contact with the source region 1 and the gate region 2, and controls the ON state and the OFF state of the carrier by the potential of the gate region and the source region. To make the gate electrode ON, the same zero voltage or positive voltage as that of the source electrode is applied to the gate electrode to move the electrons in the source region 1 to the higher potential drain region 3. The drift region 4 serves as a path for electrons as carriers from the channel region 9 to the drain region 3. The width of the drift region 4 may be limited by the limited region of the p-type conductive region, or may not have the limited region as shown in FIG. This power semiconductor device is used to make DC / DC pulses easier to perform step-up / step-down by performing ON-OFF switching. A major feature of the power semiconductor device of FIG. 1 is that it has an interrupt region 20 that is in contact with the source electrode 11, penetrates the source region 1, and extends into the channel region 9.

Next, a method of manufacturing the power semiconductor device shown in FIG. 1 will be described. First, as shown in FIG. 2, n ⁺
An n-type semiconductor layer 32 and an n ⁺ -type semiconductor layer 33 are sequentially stacked on a type semiconductor substrate 31. Then, the above interrupt area 2
After opening the interrupt region forming hole at a position corresponding to 0, a p ⁺ type semiconductor is deposited in the interrupt region forming hole using a plasma CVD device or the like. This p ⁺ -type semiconductor layer can be formed by combining a semiconductor and a p-type impurity in the same manner as forming a plug in a contact hole. Next, as shown in FIG.
Ion Etching) to form the source region 1
Etch away other parts. Thereafter, as shown in FIG. 4, p-type impurity ions are implanted to form a gate region 2. Thereafter, when Ni is laminated as an electrode,
The power semiconductor device shown in FIG. 1 is completed. The electrodes in the first embodiment are provided so as to form an ohmic contact including the gate electrode. However, since the impurity concentration of each region is high, the formation of the ohmic contact is easy.

Next, how to form a depletion layer when a reverse bias voltage is applied between the source electrode 11 and the gate electrode 12 to turn off the source electrode 11 will be described. In FIG. 1, when a negative voltage is applied to the gate electrode 12 as compared with the source electrode 11, a reverse bias voltage is applied to the gate region / channel region interface. At this time, a depletion layer grows on the side of the channel region 9 having a low impurity concentration at the gate region / channel region interface. Due to the presence of the p-conduction type interrupt region 20 in contact with the gate electrode 12, as shown in FIG. 5, the depletion layer 21 tends to extend toward the source electrode side at a low voltage and spread. For this reason, the two depletion layers 21 extending from both sides of the channel region are united near the center of the width of the channel region 9 at the tip of the interrupt region 20 at a lower voltage than in the related art to form a barrier against electrons. Since electrons sense a potential barrier at the boundary with the p-type conductive region, it is not essential that the depletion layers unite with each other.
When the depletion layer 21 comes into contact with the depletion layer 21, the movement of electrons is blocked. As a result, the OFF state can be realized by a negative voltage having a smaller absolute value than in the related art, and a further lower loss can be achieved as a high-power switching element.

The semiconductor substrate used for the JFET shown in FIG. 1 is a SiC substrate having a thickness increased by crystal growth on a SiC substrate.
The layers were laminated. However, the material of the semiconductor substrate is not limited to SiC, but may be Si, GaAs.
Etc. may be used.

(Second Embodiment) FIG. 6 is a sectional view showing a power semiconductor device according to a second embodiment. A major difference from the power semiconductor device in the first embodiment is that a plurality of interrupt regions 20 are arranged. The method of manufacturing the semiconductor device shown in FIG. 6 is basically the same as the method described with reference to FIG. When a reverse bias voltage is applied between the source electrode and the gate electrode, the depletion layer 21 is reduced by the reverse bias voltage lower than in the prior art, as shown in FIG. It tends to extend toward the interrupt area 20 of the area. As a result, the OFF state can be realized with a voltage lower than that of the related art, and it is possible to further reduce the loss as a high-power switching element.

(Embodiment 3) In the power semiconductor device of Embodiment 3, in order to facilitate formation of a depletion layer extending toward channel region 9, n ⁻ layer 2 having a low impurity concentration is used.
2 (depletion layer promoting region) is arranged in contact with gate region 2 (FIG. 8). Further, the leading end of the interrupt region 20 extends right beside the gate region and extends to a position reaching the drift region. When a reverse bias voltage is applied to the power semiconductor element having this structure, the depletion layer extends from the interface between the gate region and the depletion layer promotion region into the depletion layer promotion region (n ⁻ layer) 22 at a very low reverse bias voltage. Therefore, a depletion layer as shown in FIG. 9 is formed by a very low reverse bias voltage, and an OFF state can be realized. As a result, it is possible to further reduce the loss as a high power switching element.

Although the embodiments of the present invention have been described above, the embodiments disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. Absent. The scope of the present invention is indicated by the description of the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0028]

According to the FET of the present invention, an OFF state can be realized by a reverse bias voltage having an absolute value smaller than that of a conventional one, and a power semiconductor element with much lower loss is provided as a high power switching element. It is possible to do.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a power semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view of a stage in which an interrupt region has been formed in the manufacture of the power semiconductor device of FIG. 1;

FIG. 3 is a cross-sectional view showing a stage after performing etching to form a source region and a channel region from the stage in FIG. 2;

FIG. 4 is a cross-sectional view at a stage where impurities are implanted to form a gate region.

FIG. 5 is a diagram showing a depletion layer formed by applying a reverse bias voltage to the power semiconductor device of FIG. 1;

FIG. 6 is a sectional view of a power semiconductor device according to a second embodiment.

7 is a diagram illustrating a depletion layer formed by applying a reverse bias voltage to the power semiconductor device of FIG. 6;

FIG. 8 is a cross-sectional view of a power semiconductor device according to a third embodiment.

9 is a diagram illustrating a depletion layer formed by applying a reverse bias voltage to the power semiconductor device of FIG. 8;

FIG. 10 is a cross-sectional view of a conventional lateral JFET.

FIG. 11 is a cross-sectional view of an SIT which is a conventional vertical JFET.

FIG. 12: Conventional vertical JFET (power semiconductor element)
FIG.

[Explanation of symbols]

1 source region, 2 gate region, 3 drain region,
4 Drift region, 21 Depletion layer formed when turned off, 9 Channel region, 11 Source electrode, 1
2 gate electrode, 13 drain electrode, 20 interrupt region, 21 depletion layer, 22 n ⁻ type semiconductor region (depletion layer promoting region), 31 semiconductor substrate, 32 n-type semiconductor layer, 3
3 n ⁺ type semiconductor layer.

Claims (6)

[Claims] A first conductive type source region provided on one main surface side of the semiconductor substrate; a source electrode provided on the source region in contact with the source region; A second conductivity type gate region provided on the surface side; a first conductivity type channel region in contact with the source region and the gate region; and a first conductivity type provided on another main surface of the semiconductor substrate. And a drain region of a second conductivity type, which is in contact with the source electrode and extends toward the channel region. 2. The power semiconductor device according to claim 1, wherein said gate region is provided on both sides of said channel region. 3. The interrupt region extends through the source region and into the channel region.
Or a power semiconductor device according to item 2. 4. The interrupt area is divided into two or more areas with a first conductivity type area interposed therebetween.
4. The power semiconductor device according to any one of 3. 5. A depletion layer promoting region of a first conductivity type, which is in contact with the gate region and the source region and is in the channel region and has a lower concentration than an impurity concentration of the first conductivity type of the channel region. The power semiconductor device according to claim 1, further comprising: 6. The power semiconductor device according to claim 1, wherein said semiconductor substrate is made of SiC.