JP2001203351A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the short channel effect in forming pocket regions on a semiconductor substrate without increasing the junction capacitance between a source-drain diffusion region and the semiconductor substrate. SOLUTION: Oblique ion implantation is executed at least twice at different implanting energies with different implanting doses to form first pocket regions 1061 having a high impurity concentration at the side faces of the source-drain diffusion regions, and second pocket regions 1062 having a low impurity concentration at the bottom faces.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a MIS semiconductor device having a pocket structure for suppressing a short channel effect and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with miniaturization of elements of a MIS semiconductor device, the channel length has become equal to the width of a depletion layer between a source and a substrate and between a drain and a substrate. For this reason, the threshold voltage decreases, and the off-leak characteristic deteriorates. This phenomenon is known as a short channel effect, and significantly restricts miniaturization of elements of a MIS semiconductor device.

As a method of suppressing the short channel effect, a pocket structure has been proposed. FIG. 4 shows an example of the pocket structure. 4, reference numeral 49 denotes a well region, 46 denotes a pocket region, 48 denotes a source / drain diffusion region, and 45 denotes a well region.
Is an extension region, 43 is a gate insulating film, 44 is a polysilicon gate electrode, and 47 is a sidewall.

In the above structure, the source / drain diffusion region 48 is located near the extension region 45.
The pocket region 46, which is an impurity region of the same conductivity type as the well region 49, is formed so as to be in contact with the well region 49, and the impurity concentration of the pocket region 46 is made higher than that of the well region 49. This is to suppress the extension of the depletion layer to the channel region and suppress the short channel effect.

[0005] An outline of the method of forming the pocket region is shown in FIG.
This will be described with reference to (B) and (C).

[0006] First, as shown in FIG.
00) An N-type well region 59 is formed on the Si substrate 51 by ion-implanting an N-type impurity. After that, ion implantation or the like for controlling the threshold voltage is performed, and a polysilicon gate electrode 54 is formed via the gate insulating film 53.

Then, as shown in FIG. 5B, a P-type impurity is implanted shallowly using the polysilicon gate electrode 54 as a mask to form a P-type extension region 5.
5 is formed. The implantation angle at this time is about 0 to 7 °, which is substantially perpendicular to the surface of the P-type Si substrate 51, that is, an angle substantially parallel to the normal 61.

Further, an N-type impurity is obliquely ion-implanted 82 at a large angle only once in one direction using the polysilicon gate electrode 54 as a mask to form an N-type pocket region 56 and heat treatment is performed. θ is an implantation angle of oblique ion implantation, and indicates an angle between the oblique ion implantation and a normal 61 perpendicular to the semiconductor substrate surface.

Thereafter, as shown in FIG. 5C, a sidewall 57 is formed of an insulator, and a P-type impurity is deposited at a high dose with a P-type impurity using the polysilicon gate electrode 54 and the sidewall 57 as a mask. Ion implantation is performed substantially perpendicularly to the surface of the substrate 51 to form a P-type source / drain diffusion region 58, and heat treatment is performed. After that, an interlayer insulating film, a wiring, and the like are formed according to a normal process.

Here, the P-type extension region 55,
The conditions for ion implantation at the time of forming each of the N-type pocket region 56 and the P-type source / drain region 58 will be described.

First, the P-type extension region 55
For example, it is formed by implanting BF ₂ at an implantation energy of 10 keV, an implantation dose of 5 × 10 ¹⁴ cm ⁻² , and an implantation angle of 0 to 7 °.

Next, the N-type pocket region 56 is formed, for example, by implanting As with an implantation energy of 140 keV and an implantation dose of 1 ×.
It is formed by implanting at 10 ¹³ cm ^{-2 at} an implantation angle of 25 °.

Next, a P-type source / drain region 58
Is formed, for example, by implanting BF ₂ at an implantation energy of 20 keV, an implantation dose of 4 × 10 ¹⁵ cm ⁻² , and an implantation angle of 0 to 7 °.

[0014]

However, the prior art shown in FIG. 5 has the following problems. That is, the N-type pocket region 5 formed by oblique ion implantation with a large inclination angle
In the formation of 6, the effect of suppressing the short channel effect increases as the implantation energy increases. This is a P-type source
This is because the N-type pocket region 56 is formed to cover the drain diffusion region 58. However, on the other hand, there is a problem that the junction capacitance with the bottom of the P-type source / drain diffusion region 58 increases.

The biggest cause of this problem is that, in the above-mentioned prior art, only one oblique ion implantation is required.
N-type pocket region 56 for suppressing short channel effect
When the impurity concentration of the P type source / drain diffusion region 58 is increased, the impurity concentration at both the side surface and the bottom surface of the P type source / drain diffusion region 58 increases, and the impurity concentration at the bottom surface of the P type source / drain diffusion region 58 cannot be reduced. is there.

In order to solve the above problem, the implantation angle θ of the oblique ion implantation with respect to the normal 61 perpendicular to the surface of the semiconductor substrate is further increased to, for example, 40 to 60 °, and the P-type source / drain Although a method of suppressing ion implantation into the bottom surface of the diffusion region 58 has been considered, there is a large influence on a substrate surface serving as a channel region immediately below the gate electrode 54, which makes it difficult to control a threshold voltage. Therefore, it is not preferable to adopt the method of increasing the injection angle θ.

More specifically, when the implantation angle θ is increased, the impurity concentration near the surface of the substrate increases, and the penetration directly below the gate electrode 54 increases.
As a result, the impurity concentration of the channel region increases as a whole, and the threshold voltage changes. In order to avoid this, it is necessary to reduce the implantation energy and the dose as compared with the conventional case.
For example, conventionally, when the implantation energy is 140 keV and the dose is 1 × 10 ¹³ cm ⁻² , the implantation angle θ
Is increased, the implantation energy and the dose are reduced to 100 keV and 7 × 10 ¹² cm ⁻² , respectively.
However, when the implantation energy and the dose are reduced, the ability to suppress the short channel effect is reduced.

Accordingly, an object of the present invention is to provide a structure in which, when a pocket region is formed, the impurity concentration is high on the side surface of the source / drain diffusion region and low on the bottom surface, thereby increasing the junction capacitance. Another object of the present invention is to provide a semiconductor device capable of suppressing a short channel effect.

Another object of the present invention is to provide a structure in which, when a pocket region is formed, the impurity concentration is high on the side surface of the source / drain diffusion region and low on the bottom surface. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can suppress a short channel effect without increasing the threshold voltage and does not affect a threshold voltage.

[0020]

To achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and a semiconductor device. A sidewall formed on a side surface of the gate electrode, a first conductivity type source / drain diffusion region formed on both sides of the gate electrode in the semiconductor substrate, and a vicinity of a surface in the semiconductor substrate below an end of the gate electrode. And an extension region of the first conductivity type formed in contact with the side surface of the source / drain diffusion region, and a second conductivity type contacting the bottom surface of the extension region and covering a part of the side surface of the source / drain diffusion region. , A first pocket region having a high impurity concentration, and the remaining and bottom portions of the side surfaces of the source / drain diffusion regions which are in contact with the bottom surface of the first pocket region (hereinafter referred to as bottom side surfaces). And a second pocket region of low impurity concentration in the second conductivity type covering the abbreviated).

According to this structure, the first pocket region of the second conductivity type and the high impurity concentration which covers a part of the side surface of the source / drain diffusion region is formed in the semiconductor substrate; Since two types of pocket regions are formed of a second conductivity type and a low impurity concentration second pocket region covering the bottom side surface of the region, the impurity distribution in the pocket region is reduced by the side surfaces of the source / drain diffusion regions. It can be dark and thin at the bottom. As a result, a pocket structure having a large effect of suppressing the short channel effect can be realized without increasing the junction capacitance.

It is preferable that the first pocket region covering a part of the side surface of the source / drain diffusion region is formed so that the impurity concentration peaks near the bottom surface of the extension region.

According to this structure, the peak position of the impurity concentration in the first pocket region is closer to the surface of the semiconductor substrate, so that a pocket structure in which the short channel effect can be further suppressed can be obtained.

In addition to the first pocket region and the second pocket region, the pocket region covers both side surfaces near the boundary where the extension region formed in the semiconductor substrate and the first pocket region are in contact with each other. In some cases, a third pocket region having two conductivity types and a low impurity concentration is provided.

With this configuration, the vicinity of the bottom surface of the side surface of the extension region is covered with the third pocket region, so that a pocket structure that can further suppress the short channel effect is obtained.

Next, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a step of forming the gate electrode after forming the gate electrode. Forming a first conductivity type extension region by shallow ion implantation of impurities into a semiconductor substrate as a mask; and, after forming the extension region, using a gate electrode as a mask at a first implantation energy and a first implantation dose. Forming a first pocket region of a second conductivity type and a high impurity concentration by implanting a large amount of impurities into the semiconductor substrate at a large oblique angle with a first oblique ion; and, after forming the extension regions, using the gate electrode as a mask. Impurities having a second implantation energy and a second implantation dose are introduced into the semiconductor substrate from the same direction as the first oblique ion implantation. Forming a second pocket region of a second conductivity type and a low impurity concentration by implanting a second oblique ion at an oblique angle; and, after forming the first and second pocket regions, electrically connecting the side surfaces of the gate electrode. Forming a sidewall as an insulator on the substrate, and forming a first conductive type source / drain diffusion region by ion-implanting impurities into the semiconductor substrate using the gate electrode and the sidewall as a mask after forming the sidewall. And a step of performing. The implantation angle of the oblique ion implantation with a large inclination angle is preferably in the range of 20 ° to 60 °.

According to this method, after forming the extension region, the first and second oblique ion implantations are used to implant the impurities at different implantation energies and different implantation doses at least twice from the same direction. By forming the pocket region, the first pocket region with a high impurity concentration on the side surface of the source / drain diffusion region and the second pocket region with a low impurity concentration on the bottom surface can be formed.

Therefore, a pocket structure having a large effect of suppressing the short channel effect can be realized without increasing the junction capacitance.

In addition, since it is not necessary to increase the implantation angle in the ion implantation for forming the pocket region, the threshold voltage can be prevented from being affected.

In the above manufacturing method, the second implantation energy may be higher than the first implantation energy and the second implantation dose may be smaller than the first implantation dose.
Is preferably performed.

By doing so, the first pocket region with a high impurity concentration formed in the semiconductor substrate and covering the side surface of the source / drain diffusion region, and the bottom side surface portion of the source / drain diffusion region And a second pocket region having a low impurity concentration covering the second pocket region can be selectively formed.

It is preferable that the first oblique ion implantation for forming the first pocket region has a larger implantation angle than the second oblique ion implantation for forming the second pocket region.

As described above, by making the implantation angle of the first oblique ion implantation larger than the implantation angle of the second oblique ion implantation, the peak position of the impurity concentration in the first pocket region having the high-concentration impurity can be set. It is possible to set the position closer to the surface of the semiconductor substrate than the side surface of the source / drain diffusion region, and it is possible to obtain a pocket structure having a greater effect of suppressing the short channel effect.

In addition, the implantation dose in the first oblique ion implantation with a large implantation angle is a part of the total implantation dose required to form the pocket structure, and is more effective than the second oblique ion implantation. By lowering the implantation energy of the first oblique ion implantation, a first pocket region that does not affect the threshold voltage can be formed.

In the above-described manufacturing method, after forming the extension region and at least before forming the sidewall, the impurity of the third implantation energy and the third implantation dose is implanted by using the gate electrode as a mask. Forming a third pocket region of a second conductivity type and a low impurity concentration by performing a third oblique ion implantation at a large inclination angle into the semiconductor substrate from the same direction as the ion implantation; May be performed under the condition that the implantation energy and the implantation dose are lower than those of the first oblique ion implantation and the implantation angle is larger than that of the first oblique ion implantation.

This makes it possible to form a third pocket region of low impurity concentration that covers the vicinity of the bottom surface of the side surface of the extension region formed in the semiconductor substrate.
A horizontal pocket structure in which the short channel effect can be further suppressed can be obtained.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS. 1 (A), 1 (B) and 1 (C). FIG. 1 shows an example applied to a P-channel MOSFET.

First, as shown in FIG. 1A, a trench 2A is formed in a P-type (100) Si substrate 1 by a known technique, and an oxide film 2 is buried therein to perform element isolation. Thereafter, for example, As ion implantation for adjusting the threshold voltage and P ion implantation for forming the N-type well region 9 are performed. After that, an oxide film serving as a gate insulating film of about 3 nm is provided by a thermal oxidation method or the like. Thereafter, polycrystalline silicon serving as a gate electrode is deposited to a thickness of about 200 nm on the oxide film, and after patterning by photolithography,
A gate oxide film 3 and a gate electrode 4 are formed by anisotropic etching.

Thereafter, as shown in FIG. 1B, for example, BF ₂ is implanted at an implantation energy of 10 keV and an implantation dose of 5 ×.
P-type extension regions 5 are formed by ion implantation at 10 ¹⁴ cm ^{-2 at} an implantation angle of 7 °.

Thereafter, for example, an implantation energy of 100 ke
V, the first oblique ion implantation 521 of As is performed at an implantation dose of 3 × 10 ¹³ cm ⁻² and an implantation angle of 25 ° to form an N-type first pocket region 161 to be a high-concentration first pocket region. . Further, the injection energy is continuously 140 ke.
V, an implantation dose of 1 × 10 ¹³ cm ⁻² , an implantation angle of 25 °, and a second implantation of As from the same direction as the first oblique ion implantation 521.
Is performed by oblique ion implantation 522 to form an N-type second pocket region 162 to be a low concentration second pocket region.
Is the angle of incidence of the ion beam with respect to the normal 61, and the oblique ion implantations 521 and 522 are performed at the same implantation angle.

After that, as shown in FIG. 1C, for example, a heat treatment is performed in a nitrogen atmosphere at 1000 ° C. for about 10 seconds, a CVD SiO ₂ film having a thickness of about 60 nm is deposited, and the gate electrode 4 is anisotropically etched. Side wall 7 on the side
To form

Then, for example, BF ₂ is implanted at an energy of 2
0 keV, implantation dose 4 × 10 ¹⁵ cm ⁻² , implantation angle 7
P type source / drain diffusion region 8
Is formed, and is heat-treated at, for example, 1000 ° C. for about 10 seconds in a nitrogen atmosphere.
61 and the N-type second pocket region 1062 can be formed.

The semiconductor device manufactured as described above includes a P-type Si substrate 1, a gate oxide film 3 formed on the P-type Si substrate 1, and a gate electrode 4 formed on the gate oxide film 3. A sidewall 7 formed on the side surface of the gate electrode 4, a P-type source / drain diffusion region 8 formed on both sides of the gate electrode 4 in the P-type Si substrate 1,
A P-type extension region 5 formed near the surface of the P-type Si substrate 1 below the end of the gate electrode 4 and in contact with the side surface of the P-type source / drain diffusion region 8 and a bottom surface of the P-type extension region 5 N-type first pocket region 1061 having a high impurity concentration and partially covering the side surface of P-type source / drain diffusion region 8, and first pocket region 10
61 and the remaining side surface and bottom surface of the P-type source / drain diffusion region 8 (that is, the bottom side surface).
And an N-type second pocket region 1062 having a low impurity concentration and covering the first region.

As described above, according to this embodiment,
After the formation of the P-type extension region 5, oblique ion implantation of impurities having different implantation energies at different implantation energies is performed twice or more, that is, the first implantation is performed with the first implantation energy and the first implantation dose. Oblique ion implantation and second oblique ion implantation performed at a second implantation energy higher than the first oblique ion implantation energy and at a second implantation dose smaller than the first implantation dose. By forming the N-type first pocket region 161 and the N-type second pocket region 162 by implantation, the N-type such that the impurity distribution is dense on the side surface of the P-type source / drain diffusion region 8 and thin on the bottom surface. First pocket region 1061 and N-type second pocket region 1062
Can be finally formed. Therefore, a pocket structure having a large effect of suppressing the short channel effect can be realized without increasing the junction capacitance.

In addition, since it is not necessary to increase the implantation angle in the ion implantation for forming the N-type first pocket region 1061 and the N-type second pocket region 1062, the threshold voltage is not affected. can do.

[Second Embodiment] Hereinafter, a second embodiment of the present invention will be described.
Will be described with reference to FIGS. 2A and 2B.

In the same manner as in the first embodiment, the N-type well region 9, gate oxide film 3, gate electrode 4
And a P-type extension region 5 is formed. Thereafter, as shown in FIG. 2A, a process for forming the N-type first pocket region 261 having a high impurity concentration is performed as follows. That is, for example, the first oblique ion implantation 621 of As is performed at an implantation energy of 100 keV, an implantation dose of 3 × 10 ¹³ cm ⁻² , and an implantation angle of 35 ° to form an N-type first pocket region 261 having a high impurity concentration.

Further, the injection energy is continuously 140 ke
V, a second oblique ion implantation 622 of As is performed from the same direction as the first oblique ion implantation 621 at an implantation dose of 1 × 10 ¹³ cm ⁻² and an implantation angle of 25 °, and an N-type second pocket having a low impurity concentration is used. A region 262 is formed.

Here, by setting the initial implantation angle to 35 °, as shown in FIG.
The pocket region 2061 is formed by the N-type first pocket region 106 in the first embodiment in which the implantation angle is 25 °.
The position closer to the substrate surface than 1 (near the bottom surface of the extension region 5) is the peak position of the impurity concentration, and the bottom surface is formed shallow.

Further, the N-type first pocket region 2061 having a high impurity concentration only needs to be formed on the side surface of the P-type source / drain diffusion region 8, so that the implantation angle is increased and the source / drain is increased as in the conventional process. The dose of implantation can be set lower than forming the pocket region covering the side and bottom surfaces of the diffusion region by one ion implantation. Therefore, the influence on the impurities in the channel region immediately below the gate electrode 4 is small. That is, in the second embodiment, P
Since the bottom side surface of the diffusion region 8 for the source / drain type is covered with the N-type second pocket region 2062 having a low impurity concentration,
Unlike the conventional process, it is not necessary to form the N-type first pocket region 2061 up to the bottom surface of the P-type source / drain diffusion region 8, so that the dose can be reduced.

Therefore, the N-type first pocket region 206
1 indicates that the impurity concentration peak position comes closer to the surface of the P-type Si substrate 1 than the N-type first pocket region 1061 when the implantation angle is 25 °, that is, the impurity in the N-type pocket region 2061 Can be made deeper in the side region closer to the surface of the semiconductor substrate than in the P-type source / drain diffusion region 8, and the distribution can be made higher than in the first embodiment.
Further, a pocket structure that suppresses the short channel effect can be obtained.

[Third Embodiment] Hereinafter, a third embodiment of the present invention will be described.
The embodiment will be described with reference to FIGS. 3 (A) and 3 (B).

An N-type well region 9, a gate oxide film 3, a gate electrode 4, and a P-type extension region 5 are formed in the same manner as in the first embodiment. Thereafter, as shown in FIG. 3A, a process for forming an N-type third pocket region 361 having a low impurity concentration is performed as follows. That is, for example, oblique ion implantation 721 of As is performed at an implantation energy of 60 keV, an implantation dose of 1 × 10 ¹³ cm ⁻² , and an implantation angle of 40 °.

Next, for example, an injection energy of 100 ke
V, an oblique ion implantation 722 of As is performed at an implantation dose of 2 × 10 ¹³ cm ⁻² and an implantation angle of 35 ° to form an N-type first pocket region 362 having a high impurity concentration. Further, an implantation energy of 140 keV and an implantation dose of 1 × 10
Oblique ion implantation of As at a implantation angle of 25 cm at ¹³ cm ^-2 72
3 to form an N-type second pocket region 36 having a low impurity concentration.
Form 3

Here, by adding ion implantation at an implantation angle of 40 ° first, as shown in FIG. 3B, three final N-type pocket regions 3061, 3062, and 3063 are obtained. . The N-type third pocket region 3061 having a low impurity concentration is formed between the P-type extension region 5 and the N-type third pocket region 3061.
Since the first pocket region 3062 is formed so as to extend over both side surfaces near the boundary where the first pocket region 3062 contacts, the depletion from the P-type source / drain diffusion region 8 immediately below the gate without affecting the impurities in the channel region. Reduce layer elongation. For the N-type first pocket region 3062 having a high impurity concentration and the N-type second pocket region 3063 having a low impurity concentration, the N-type first pocket region 2061 having a high impurity concentration and the N-type first pocket region 2061 having a low impurity concentration according to the second embodiment are used. Mold second pocket area 2
062.

According to this embodiment, since the vicinity of the bottom surface of the side surface of the extension region 5 is covered with the N-type third pocket region 3061, the pocket in which the short channel effect can be further suppressed as compared with the second embodiment. The structure is obtained.

In each of the above embodiments, each oblique ion implantation is performed by rotating the surface of the semiconductor substrate by, for example, 90 ° four times and implanting the gate electrode from four directions.

According to this structure, the pocket region does not vary depending on the gate electrode pattern formation direction, and a uniform pocket region can be obtained in each direction.

[0059]

As described above, according to the present invention,
A structure in which the impurity concentration in the pocket region is high on the side surface of the source / drain diffusion region and low on the bottom surface. Therefore, a pocket structure having a large effect of suppressing the short channel effect can be realized without increasing the junction capacitance.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are step-by-step sectional views showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention in order of process.

FIG. 4 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIGS. 5A, 5B and 5C are cross-sectional views in the order of steps showing a method for manufacturing another conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 P-type (100) Si substrate 2 A Trench groove 2 Oxide film 3 Gate oxide film 4 Gate electrode 5 P-type extension region 161 N-type first pocket region with high impurity concentration 162 N-type second pocket region with low impurity concentration 7 Side Wall 8 P-type source / drain diffusion region 9 N-type well region 1061 N-type first pocket region with final high impurity concentration 1062 N-type second pocket region with final low impurity concentration 261 N-type with high impurity concentration First pocket region 262 N-type second pocket region with low impurity concentration 2061 N-type first pocket region with final high impurity concentration 2062 N-type second pocket region with final low impurity concentration 361 N-type with low impurity concentration Third pocket region 362 N-type first pocket region 363 with high impurity concentration N-type second pocket region 3061 N-type third pocket region with final low impurity concentration 3062 N-type first pocket region with final high impurity concentration 3063 N-type second pocket region with final low impurity concentration 43 Gate insulating film 44 Gate electrode 45 Extension region 46 Pocket region 47 Side wall 48 Diffusion region for source / drain 49 Well region 51 P-type (100) Si substrate 53 Gate insulating film 54 Gate electrode 55 P-type extension region 56 N-type pocket region 57 Side wall 58 P-type source / drain diffusion region 59 N-type well region

Claims (7)

[Claims] A semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; a sidewall formed on a side surface of the gate electrode; A first conductivity type source / drain diffusion region formed on both sides of the gate electrode in the substrate; and a side surface of the source / drain diffusion region near a surface in the semiconductor substrate below an end of the gate electrode. A first conductivity type extension region formed in contact with the first conductivity type and a second conductivity type high impurity concentration first region in contact with a bottom surface of the extension region and partially covering a side surface of the source / drain diffusion region; A pocket region, and a second conductive type and low impurity that is in contact with the bottom surface of the first pocket region and covers the remaining side surface and the bottom surface of the source / drain diffusion region. A semiconductor device characterized by comprising a second pocket region concentration. 2. The method according to claim 1, wherein the first pocket region covering a part of a side surface of the source / drain diffusion region is formed such that a peak position of an impurity concentration comes near a bottom surface of the extension region. 2. The semiconductor device according to claim 1, wherein 3. As both pocket regions, in addition to the first pocket region and the second pocket region, both sides near a boundary where the extension region formed in the semiconductor substrate and the first pocket region are in contact with each other. 3. The semiconductor device according to claim 1, further comprising a third pocket region of a second conductivity type and a low impurity concentration covering the surface portion. A step of forming a gate insulating film on the semiconductor substrate; a step of forming a gate electrode on the gate insulating film; and after forming the gate electrode, impurities in the semiconductor substrate using the gate electrode as a mask. Forming a first conductivity type extension region by ion-implanting shallowly, and after forming the extension region, using the gate electrode as a mask, implanting an impurity with a first implantation energy and a first implantation dose. Forming a first pocket region of a second conductivity type and a high impurity concentration by implanting a first oblique ion at a large inclination angle into a semiconductor substrate; and forming a second pocket region with the gate electrode as a mask after forming the extension region. The impurity having the implantation energy of 2 and the second implantation dose is introduced into the semiconductor from the same direction as the first oblique ion implantation. Forming a second pocket region of a second conductivity type and a low impurity concentration by implanting a second oblique ion at a large tilt angle into the substrate; and forming the gate electrode after the formation of the first and second pocket regions. Forming a side wall that is an electrically insulating material on the side surface of the first conductive type by forming the side wall and then implanting impurities into the semiconductor substrate using the gate electrode and the side wall as a mask. Forming a source / drain diffusion region according to (1). 5. The method according to claim 1, wherein the second implantation energy is higher than the first implantation energy and the second implantation dose is smaller than the first implantation dose.
5. The method for manufacturing a semiconductor device according to claim 4, wherein said ion implantation is performed. 6. The first oblique ion implantation for forming the first pocket region has a larger implantation angle than the second oblique ion implantation for forming the second pocket region. 6. The method for manufacturing a semiconductor device according to claim 4, wherein: 7. After the formation of the extension region and before forming at least the sidewalls, the gate electrode is used as a mask with a third implantation energy and a third implantation energy.
A third oblique ion implantation into the semiconductor substrate at a large inclination angle from the same direction as the first ion implantation into the third pocket region having a second conductivity type and a low impurity concentration. Forming the third oblique ion implantation, the implantation energy and implantation dose of the third oblique ion implantation are lower than those of the first oblique ion implantation.
7. The method of manufacturing a semiconductor device according to claim 4, wherein the implantation is performed under a condition that the implantation angle is larger than the oblique ion implantation.