JP2001203217A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2001203217A
JP2001203217A JP2000014198A JP2000014198A JP2001203217A JP 2001203217 A JP2001203217 A JP 2001203217A JP 2000014198 A JP2000014198 A JP 2000014198A JP 2000014198 A JP2000014198 A JP 2000014198A JP 2001203217 A JP2001203217 A JP 2001203217A
Authority
JP
Japan
Prior art keywords
layer
crystal
semiconductor device
type
base layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000014198A
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Japanese (ja)
Other versions
JP4019590B2 (en
Inventor
Takeshi Meguro
健 目黒
Shunichi Minagawa
俊一 皆川
Junichi Igarashi
淳一 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
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Publication date
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Priority to JP2000014198A priority Critical patent/JP4019590B2/en
Publication of JP2001203217A publication Critical patent/JP2001203217A/en
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Publication of JP4019590B2 publication Critical patent/JP4019590B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a current amplification factor β does not decrease even if a dopant of exceeding 3×1018 cm-3 is doped into a sub-collector layer. SOLUTION: By providing an AlAs layer 3 between a sub-collector layer 2 and an collector layer 4 of an HBT epitaxial wafer acting as a semiconductor device, the current amplification factor β does not decrease even if the dopant of exceeding 3×1018 cm-3 is doped into the sub-collector layer 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ヘテロバイポーラ
トランジスタ等の半導体装置に関する。
The present invention relates to a semiconductor device such as a hetero bipolar transistor.

【0002】[0002]

【従来の技術】従来、ヘテロバイポーラトランジスタ
(HBT)のエミッタ層やベース層に着目して、各層の
結晶性やその界面を改善することにより、電流増幅率β
を向上させる試みが行われてきた。従って、ベース層よ
りも下にあるコレクタ層やサブコレクタ層について、こ
れら各層の結晶性と電流増幅率βとの関係についてはあ
まりよく研究されていなかった。
2. Description of the Related Art Conventionally, by focusing on an emitter layer and a base layer of a hetero bipolar transistor (HBT), the crystallinity of each layer and the interface between the layers have been improved, so that a current amplification factor β has been improved.
Attempts have been made to improve. Therefore, regarding the collector layer and the sub-collector layer below the base layer, the relationship between the crystallinity of each layer and the current amplification factor β has not been well studied.

【0003】[0003]

【発明が解決しようとする課題】ところで、最近になっ
てサブコレクタ層のドーピング濃度が電流増幅率βにか
なりの影響を与えることが分かってきた。HBTのよう
な縦構造のデバイスでは配線を引き出すための電極の面
積がかなり制限される。このため、十分に低いコンタク
ト抵抗を得るためには、サブコレクタ層をかなり高濃度
にn型ドーピングする必要がある。
By the way, it has recently been found that the doping concentration of the subcollector layer has a considerable effect on the current amplification factor β. In a device having a vertical structure such as an HBT, the area of an electrode for drawing out a wiring is considerably limited. For this reason, in order to obtain a sufficiently low contact resistance, it is necessary to dope the subcollector layer with n-type at a considerably high concentration.

【0004】しかしながら、ドーピング濃度が3×10
18cm-3を超えると、極端に電流増幅率βが低下すると
いう問題があった。
However, when the doping concentration is 3 × 10
When it exceeds 18 cm -3 , there is a problem that the current amplification factor β is extremely reduced.

【0005】そこで、本発明の目的は、上記課題を解決
し、サブコレクタ層に3×1018cm-3を超えてドーパ
ントをドーピングしても電流増幅率βが低下しない半導
体装置を提供することにある。
Accordingly, an object of the present invention is to solve the above problems and to provide a semiconductor device in which the current amplification factor β does not decrease even if the subcollector layer is doped with a dopant exceeding 3 × 10 18 cm −3. It is in.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に本発明の半導体装置は、GaAs基板上に、金属電極
とのオーミックコンタクトを形成するn型のGaAs結
晶からなるサブコレクタ層と、ベース層から電子を引き
抜くn型のGaAs結晶からなるコレクタ層と、電子の
流れを制御するp型のGaAs結晶か、InGaAs結
晶か、あるいはAlGaAs結晶からなるベース層と、
ベース層に対してヘテロ接合を形成し、電子をベース層
に注入し、ベース層からの正孔の注入を抑止するn型の
伝導を示すAlGaAs結晶からなるエミッタ層と、金
属電極とオーミックコンタクトを形成するn型のInG
aAs結晶からなるエミッタコンタクト層とが順次形成
された半導体装置において、サブコレクタ層と上記コレ
クタ層との間にAlAs層を設けたものである。
In order to achieve the above object, a semiconductor device according to the present invention comprises a subcollector layer made of an n-type GaAs crystal for forming an ohmic contact with a metal electrode on a GaAs substrate; A collector layer composed of an n-type GaAs crystal for extracting electrons from the layer, a base layer composed of a p-type GaAs crystal, an InGaAs crystal, or an AlGaAs crystal for controlling the flow of electrons,
A heterojunction is formed with the base layer, electrons are injected into the base layer, and an emitter layer made of an AlGaAs crystal exhibiting n-type conduction for suppressing injection of holes from the base layer, and a metal electrode and an ohmic contact are formed. N-type InG to be formed
In a semiconductor device in which an emitter contact layer made of an aAs crystal is sequentially formed, an AlAs layer is provided between a subcollector layer and the collector layer.

【0007】本発明の半導体装置は、GaAs基板上
に、金属電極とのオーミックコンタクトを形成するn型
の伝導を示すGaAs結晶からなるサブコレクタ層と、
ベース層から電子を引き抜くn型のGaAs結晶からな
るコレクタ層と、電子の流れを制御するp型のGaAs
結晶か、InGaAs結晶か、あるいはAlGaAs結
晶からなるベース層と、ベース層に対してヘテロ接合を
形成し、電子をベース層に注入し、ベース層からの正孔
の注入を抑止するn型のInGaP結晶からなるエミッ
タ層と、金属電極とオーミックコンタクトを形成するn
型のInGaAs結晶からなるエミッタコンタクト層と
が順次形成された半導体装置において、サブコレクタ層
とコレクタ層との間にAlAs層を設けたものである。
A semiconductor device according to the present invention comprises a subcollector layer made of a GaAs crystal exhibiting n-type conductivity for forming an ohmic contact with a metal electrode on a GaAs substrate;
A collector layer composed of an n-type GaAs crystal for extracting electrons from the base layer, and a p-type GaAs for controlling the flow of electrons
An n-type InGaP for forming a heterojunction with a base layer made of a crystal, an InGaAs crystal, or an AlGaAs crystal, injecting electrons into the base layer, and suppressing injection of holes from the base layer. An emitter layer made of a crystal, and n forming an ohmic contact with a metal electrode.
In a semiconductor device in which an emitter contact layer made of a type InGaAs crystal is sequentially formed, an AlAs layer is provided between a subcollector layer and a collector layer.

【0008】上記構成に加え本発明の半導体装置は、A
lAs層の厚さが少なくとも1nmであるのが好まし
い。
In addition to the above configuration, the semiconductor device of the present invention
Preferably, the thickness of the lAs layer is at least 1 nm.

【0009】上記構成に加え本発明の半導体装置は、基
板上の各層がMOVPE法又はMBE法によって成長す
るのが好ましい。
In addition to the above structure, in the semiconductor device of the present invention, each layer on the substrate is preferably grown by MOVPE or MBE.

【0010】本発明によれば、半導体装置のサブコレク
タ層とコレクタ層との間にAlAs層を設けることによ
り、サブコレクタ層に3×1018cm-3を超えてドーパ
ントをドーピングしても電流増幅率βが低下することが
ない。
According to the present invention, by providing an AlAs layer between a subcollector layer and a collector layer of a semiconductor device, even if a dopant is doped into the subcollector layer beyond 3 × 10 18 cm −3 , the current is reduced. The amplification factor β does not decrease.

【0011】[0011]

【発明の実施の形態】以下、本発明の実施の形態につい
て説明する。
Embodiments of the present invention will be described below.

【0012】本発明の半導体装置は、GaAs基板上
に、金属電極とのオーミックコンタクトを形成するn型
のGaAs結晶からなるサブコレクタ層と、ベース層か
ら電子を引き抜くn型のGaAs結晶からなるコレクタ
層と、電子の流れを制御するp型のGaAs結晶、In
GaAs結晶か、あるいはAlGaAs結晶からなるベ
ース層と、ベース層に対してヘテロ接合を形成し、電子
をベース層に注入し、ベース層からの正孔の注入を抑止
するn型のAlGaAs結晶か、あるいはInGaP結
晶からなるエミッタ層と、金属電極とオーミックコンタ
クトを形成するn型のInGaAs結晶からなるエミッ
タコンタクト層とが順次形成された半導体装置におい
て、サブコレクタ層とコレクタ層との間にAlAs層を
設けたものである。この結果、サブコレクタ層に3×1
18cm-3を超えてドーパントをドーピングしても電流
増幅率βが低下することがない。
A semiconductor device according to the present invention comprises a sub-collector layer made of an n-type GaAs crystal for forming an ohmic contact with a metal electrode on a GaAs substrate, and a collector made of an n-type GaAs crystal for extracting electrons from a base layer. Layer and a p-type GaAs crystal for controlling the flow of electrons, In
A base layer made of GaAs crystal or AlGaAs crystal, and an n-type AlGaAs crystal which forms a heterojunction with the base layer, injects electrons into the base layer, and suppresses injection of holes from the base layer; Alternatively, in a semiconductor device in which an emitter layer made of an InGaP crystal and an emitter contact layer made of an n-type InGaAs crystal forming an ohmic contact with a metal electrode are sequentially formed, an AlAs layer is formed between the sub-collector layer and the collector layer. It is provided. As a result, 3 × 1
Even if a dopant is doped beyond 0 18 cm -3 , the current amplification factor β does not decrease.

【0013】[0013]

【実施例】図1は本発明の半導体装置としてのHBTエ
ピタキシャルウェハの一実施例を示す構造図である。
FIG. 1 is a structural view showing an embodiment of an HBT epitaxial wafer as a semiconductor device of the present invention.

【0014】このHBTエピタキシャルウェハは、厚さ
約600μmの半絶縁性(S.I)GaAs基板1の上
に、厚さ約500nmのn+ GaAs層(サブコレクタ
層、Si濃度5×1018cm-3)2、厚さ約5nmのA
lAs層3、厚さ約500nmのn- GaAs層(コレ
クタ層、Si濃度2×1016cm-3)4、厚さ約70n
mのp+ GaAs層(ベース層、C濃度4×1019cm
-3)5、nAlx Ga1-x As層(x=0.3、Si濃
度5×1017cm-3)6、厚さ約50nmのnAlx
1-x Asグレーデット層(x=0.3→0、Si濃度
5×1017→5×1018cm-3)7、厚さ約100nm
のn+ GaAs層(Si濃度5×1018cm-3)8、厚
さ約50nmのn+ Iny Ga1-y Asグレーデット層
(y=0→0.5、Se濃度1×1019→4×1019
-3)9及び厚さ約50nmのn+ Iny Ga1-y As
層(y=0.5、Se濃度4×1019cm-3)10を順
次形成したものである。
This HBT epitaxial wafer has an n + GaAs layer (subcollector layer, Si concentration of 5 × 10 18 cm) having a thickness of about 500 nm on a semi-insulating (SI) GaAs substrate 1 having a thickness of about 600 μm. -3 ) 2, A with a thickness of about 5 nm
lAs layer 3, n - GaAs layer (collector layer, Si concentration: 2 × 10 16 cm −3 ) 4 having a thickness of about 500 nm, thickness about 70 n
m p + GaAs layer (base layer, C concentration 4 × 10 19 cm)
-3 ) 5, nAl x Ga 1-x As layer (x = 0.3, Si concentration 5 × 10 17 cm -3 ) 6, nAl x G with a thickness of about 50 nm
a 1-x As graded layer (x = 0.3 → 0, Si concentration 5 × 10 17 → 5 × 10 18 cm −3 ) 7, thickness about 100 nm
N + GaAs layer (Si concentration 5 × 10 18 cm −3 ) 8, n + In y Ga 1 -y As graded layer (y = 0 → 0.5, Se concentration 1 × 10 19 ) having a thickness of about 50 nm → 4 × 10 19 c
m -3) 9 and a thickness of about 50nm n + In y Ga 1- y As
The layers (y = 0.5, Se concentration 4 × 10 19 cm −3 ) 10 are sequentially formed.

【0015】このHBTエピタキシャルウェハは、サブ
コレクタ層2とコレクタ層4との間に厚さ5nmのAl
As層3が形成された構造となっている点に特徴があ
る。本発明のエピタキシャルウェハの構造と、従来のエ
ピタキシャルウェハの構造(AlAs層が無い点以外図
1に示した構造と同様である。)とで電流増幅率βのサ
ブコレクタ層2のドーピング濃度依存性を比較するた
め、両者共サブコレクタ層のドーピング濃度を変えたサ
ンプルを作製した。
The HBT epitaxial wafer has a 5 nm thick Al between the subcollector layer 2 and the collector layer 4.
It is characterized in that it has a structure in which the As layer 3 is formed. The dependency of the current amplification factor β on the doping concentration of the sub-collector layer 2 in the structure of the epitaxial wafer of the present invention and the structure of the conventional epitaxial wafer (same as the structure shown in FIG. 1 except that there is no AlAs layer). In both cases, samples were prepared in which the doping concentration of the subcollector layer was changed.

【0016】プロセスによりエミッタサイズ100μm
角の評価HBTを作製し、エミッタの電流密度103
/cm2 での電流増幅率βを比較した。
The emitter size is 100 μm depending on the process.
An HBT having an evaluation of angle was prepared, and the current density of the emitter was 10 3 A
/ Cm 2 was compared.

【0017】図2はサブコレクタのドーピング濃度と電
流増幅率βとの関係を示す図であり、横軸がサブコレク
タのドーピング濃度軸であり、縦軸が電流増幅率β軸で
ある。
FIG. 2 is a diagram showing the relationship between the doping concentration of the subcollector and the current amplification factor β. The horizontal axis is the doping concentration axis of the subcollector, and the vertical axis is the current amplification factor β axis.

【0018】同図より、従来品ではサブコレクタ層のキ
ャリア濃度3×1018cm-3を超えたあたりから電流増
幅率βが低下していくが、本発明品ではサブコレクタ層
のキャリア濃度が3×1018cm-3を超えても電流増幅
率βが低下せず一定で、かつ高い電流増幅率βを保って
いることが分かる。
As shown in the figure, in the conventional product, the current amplification factor β decreases from about 3 × 10 18 cm −3 of the carrier concentration of the subcollector layer. It can be seen that the current amplification factor β does not decrease even when it exceeds 3 × 10 18 cm −3 , and is constant and maintains a high current amplification factor β.

【0019】電流増幅率βと信頼性とには関係があり、
同じ構造の場合電流増幅率βが高いほど、信頼性が向上
することが分かっている。したがって、本発明により高
濃度にドーピングされたサブコレクタ層を有する構造で
も電流増幅率βを大幅に向上させることが可能になり、
素子の信頼性の向上もかなり期待できると言える。
There is a relationship between the current amplification factor β and reliability,
In the case of the same structure, it is known that the higher the current amplification factor β, the higher the reliability. Therefore, according to the present invention, it is possible to greatly improve the current amplification factor β even in a structure having a highly-doped subcollector layer,
It can be said that the reliability of the device can be considerably improved.

【0020】なぜ電流増幅率βが改善されるのかは明ら
かではないが、高濃度にドーピングされたサブコレクタ
層中には何らかの結晶欠陥が発生するものと考えられ、
この層の上にAlAs層を成長させることで結晶欠陥が
それより上のベース層やエミッタへ伝搬するのを防止す
ると考えられる。
Although it is not clear why the current amplification factor β is improved, it is considered that some crystal defects occur in the heavily doped subcollector layer.
It is considered that growing an AlAs layer on this layer prevents crystal defects from propagating to the base layer and the emitter above it.

【0021】次にAlAs層3の厚さについて述べる。Next, the thickness of the AlAs layer 3 will be described.

【0022】図3はAlAs層の厚さと電流増幅率βと
の関係を示す図であり、横軸がAlAs厚さ軸であり、
縦軸が電流増幅率β軸である。
FIG. 3 is a diagram showing the relationship between the thickness of the AlAs layer and the current amplification factor β, wherein the horizontal axis is the AlAs thickness axis,
The vertical axis is the current amplification factor β axis.

【0023】サブコレクタ層2のドーピング濃度は5×
1018cm-3とした。AlAs層3が無いと電流増幅率
βは110程度であるが、AlAs層3の厚さが1nm
になると電流増幅率βの向上が見られ、AlAsの厚さ
が5nmで電流増幅率βが150となり、以降AlAs
膜厚が厚くなっても電流増幅率βは変わらず150程度
であった。本実施例ではAlAs層3の厚さの上限につ
いては求めることができなかったが、あまり厚くなる
と、AlAs層3の電気抵抗が無視できなくなるので、
電流増幅率βが低下するものと考えられる。
The doping concentration of the subcollector layer 2 is 5 ×
It was 10 18 cm -3 . Without the AlAs layer 3, the current amplification factor β is about 110, but the thickness of the AlAs layer 3 is 1 nm.
, The current amplification factor β is improved, the current amplification factor β becomes 150 when the thickness of the AlAs is 5 nm, and thereafter, the AlAs
Even when the film thickness was increased, the current amplification factor β was unchanged at about 150. In the present embodiment, the upper limit of the thickness of the AlAs layer 3 could not be obtained. However, if the thickness is too large, the electrical resistance of the AlAs layer 3 cannot be ignored.
It is considered that the current amplification factor β decreases.

【0024】次にAlAs層3のキャリアタイプについ
て述べる。
Next, the carrier type of the AlAs layer 3 will be described.

【0025】本実施例ではAlAs層3はアンドープの
ものを用いたが、n型やp型にドーピングしたものでも
同様の効果があった。但し、p型のものはあまり厚くな
るとpn接合により電気抵抗が生じ、電流増幅率βを低
下させると考えられる。
In this embodiment, the undoped AlAs layer 3 is used. However, the same effect can be obtained by doping n-type or p-type. However, if the p-type is too thick, it is considered that an electric resistance is generated by the pn junction and the current amplification factor β is reduced.

【0026】次にサブコレクタ層2のドーパントについ
て述べる。
Next, the dopant of the subcollector layer 2 will be described.

【0027】本実施例ではn型のドーパントにSiを用
いたが、Seでも同様な現象が生じ、サブコレクタ層2
とコレクタ層4との間にAlAs層3を挿入することに
より、電流増幅率βの改善が見られた。
In this embodiment, Si is used as the n-type dopant.
By inserting the AlAs layer 3 between the gate electrode and the collector layer 4, the current amplification factor β was improved.

【0028】AlAs層3の挿入位置について述べる。The insertion position of the AlAs layer 3 will be described.

【0029】本実施例では、サブコレクタ層2とコレク
タ層4との間にAlAs層3を挿入した場合について説
明したが、サブコレクタ層2より上、かつベース層5よ
り下であれば効果がある。例えばコレクタ層4の途中に
AlAs層3を入れた場合にも同様の改善効果があっ
た。
In this embodiment, the case where the AlAs layer 3 is inserted between the sub-collector layer 2 and the collector layer 4 has been described. is there. For example, when the AlAs layer 3 is inserted in the middle of the collector layer 4, the same effect is obtained.

【0030】また、AlAs層3の代わりに高混晶(混
晶比0.5以上)のAlGaAs層を用いても効果が認
められたが、AlAs層に比べてその効果は小さかっ
た。
The effect was also observed when an AlGaAs layer having a high mixed crystal ratio (mixed crystal ratio of 0.5 or more) was used in place of the AlAs layer 3, but the effect was smaller than that of the AlAs layer.

【0031】以上において本発明によれば、高濃度にド
ーピングされた十分に抵抗の小さいサブコレクタ層を有
するHBTにおいて、電流増幅率βと信頼性を改善した
HBT及びそのエピタキシャルウェハを提供することが
できる。
As described above, according to the present invention, it is possible to provide an HBT having a current amplification factor β and improved reliability in an HBT having a sub-collector layer which is highly doped and has a sufficiently small resistance, and an epitaxial wafer thereof. it can.

【0032】[0032]

【発明の効果】以上要するに本発明によれば、次のよう
な優れた効果を発揮する。
In summary, according to the present invention, the following excellent effects are exhibited.

【0033】サブコレクタ層に3×1018cm-3を超え
てドーパントをドーピングしても電流増幅率βが低下し
ない半導体装置の提供を実現することができる。
It is possible to provide a semiconductor device in which the current amplification factor β does not decrease even if the subcollector layer is doped with a dopant exceeding 3 × 10 18 cm −3 .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置としてのHBTエピタキシ
ャルウェハの一実施例を示す構造図である。
FIG. 1 is a structural diagram showing one embodiment of an HBT epitaxial wafer as a semiconductor device of the present invention.

【図2】サブコレクタのドーピング濃度と電流増幅率β
との関係を示す図である。
FIG. 2 shows the doping concentration of the subcollector and the current gain β
FIG.

【図3】AlAs層の厚さと電流増幅率βとの関係を示
す図である。
FIG. 3 is a diagram showing a relationship between the thickness of an AlAs layer and a current amplification factor β.

【符号の説明】[Explanation of symbols]

1 S.IGaAs基板(基板) 2 n+ GaAs層(サブコレクタ層) 3 AlAs層 4 n- GaAs層(コレクタ層) 5 p+ GaAs層(ベース層) 6 nAlx Ga1-x As層 7 nAlx Ga1-x Asグレーデット層 8 n+ GaAs層 9 n+ Iny Ga1-y Asグレーデット層 10 n+ Iny Ga1-y As層1 S. IGAs substrate (substrate) 2 n + GaAs layer (sub-collector layer) 3 AlAs layer 4 n GaAs layer (collector layer) 5 p + GaAs layer (base layer) 6 nAl x Ga 1 -x As layer 7 nAl x Ga 1 -x As graded layer 8 n + GaAs layer 9 n + In y Ga 1- y As graded layer 10 n + In y Ga 1- y As layer

フロントページの続き (72)発明者 五十嵐 淳一 茨城県日立市日高町5丁目1番1号 日立 電線株式会社日高工場内 Fターム(参考) 5F003 AP00 AZ01 BB00 BB04 BC02 BC05 BE00 BE04 BF06 BG06 BM02 BM03 BP32 Continuation of the front page (72) Inventor Junichi Igarashi 5-1-1, Hidaka-cho, Hitachi-shi, Ibaraki F-term in the Hidaka Plant of Hitachi Cable Co., Ltd. 5F003 AP00 AZ01 BB00 BB04 BC02 BC05 BE00 BE04 BF06 BG06 BM02 BM03 BP32

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 GaAs基板上に、金属電極とのオーミ
ックコンタクトを形成するn型のGaAs結晶からなる
サブコレクタ層と、ベース層から電子を引き抜くn型の
GaAs結晶からなるコレクタ層と、電子の流れを制御
するp型のGaAs結晶か、InGaAs結晶か、ある
いはAlGaAs結晶からなるベース層と、該ベース層
に対してヘテロ接合を形成し、電子を上記ベース層に注
入し、上記ベース層からの正孔の注入を抑止するn型の
AlGaAs結晶からなるエミッタ層と、金属電極とオ
ーミックコンタクトを形成するn型のInGaAs結晶
からなるエミッタコンタクト層とが順次形成された半導
体装置において、上記サブコレクタ層と上記コレクタ層
との間にAlAs層を設けたことを特徴とする半導体装
置。
1. A sub-collector layer made of an n-type GaAs crystal for forming an ohmic contact with a metal electrode on a GaAs substrate, a collector layer made of an n-type GaAs crystal for extracting electrons from a base layer, A base layer made of p-type GaAs crystal, InGaAs crystal, or AlGaAs crystal for controlling flow, and a heterojunction formed with the base layer, electrons are injected into the base layer, and electrons from the base layer are removed. In the semiconductor device, an emitter layer made of an n-type AlGaAs crystal for suppressing injection of holes and an emitter contact layer made of an n-type InGaAs crystal for forming an ohmic contact with a metal electrode are sequentially formed. A semiconductor device comprising an AlAs layer provided between the semiconductor device and the collector layer.
【請求項2】 GaAs基板上に、金属電極とのオーミ
ックコンタクトを形成するn型のGaAs結晶からなる
サブコレクタ層と、ベース層から電子を引き抜くn型の
GaAs結晶からなるコレクタ層と、電子の流れを制御
するp型の伝導を示すGaAs結晶か、InGaAs結
晶か、あるいはAlGaAs結晶からなるベース層と、
該ベース層に対してヘテロ接合を形成し、電子を上記ベ
ース層に注入し、上記ベース層からの正孔の注入を抑止
するn型のInGaP結晶からなるエミッタ層と、金属
電極とオーミックコンタクトを形成するn型のInGa
As結晶からなるエミッタコンタクト層とが順次形成さ
れた半導体装置において、上記サブコレクタ層と上記コ
レクタ層との間にAlAs層を設けたことを特徴とする
半導体装置。
2. A method according to claim 1, further comprising: forming a sub-collector layer made of n-type GaAs crystal for forming an ohmic contact with the metal electrode on the GaAs substrate; a collector layer made of n-type GaAs crystal for extracting electrons from the base layer; A base layer made of GaAs crystal, InGaAs crystal, or AlGaAs crystal exhibiting p-type conduction for controlling flow,
A heterojunction is formed with respect to the base layer, electrons are injected into the base layer, an emitter layer made of n-type InGaP crystal for suppressing injection of holes from the base layer, and a metal electrode and an ohmic contact are formed. N-type InGa to be formed
A semiconductor device in which an emitter contact layer made of an As crystal is sequentially formed, wherein an AlAs layer is provided between the sub-collector layer and the collector layer.
【請求項3】 上記AlAs層の厚さが少なくとも1n
mである請求項1または2に記載の半導体装置。
3. The AlAs layer has a thickness of at least 1 n.
3. The semiconductor device according to claim 1, wherein m is m.
【請求項4】 上記基板上の各層がMOVPE法又はM
BE法によって成長した請求項1から3のいずれかに記
載の半導体装置。
4. Each of the layers on the substrate is formed by MOVPE or M
4. The semiconductor device according to claim 1, wherein the semiconductor device is grown by a BE method.
JP2000014198A 2000-01-20 2000-01-20 Semiconductor device Expired - Fee Related JP4019590B2 (en)

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6914274B2 (en) 2002-04-19 2005-07-05 Sumitomo Chemical Company, Limited Thin-film semiconductor epitaxial substrate having boron containing interface layer between a collector layer and a sub-collector layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6914274B2 (en) 2002-04-19 2005-07-05 Sumitomo Chemical Company, Limited Thin-film semiconductor epitaxial substrate having boron containing interface layer between a collector layer and a sub-collector layer

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