JP2001202054A - Matrix type image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost and power consumption of a matrix type image display device, which supplies image data selectively to matrix-arrayed pixels through scanning lines GLj (j=1, 2... n) and data signal lines and makes them hold the data, by eliminating the need for additional constitution such as an interface circuit by absorbing the difference between the input signal level from an external circuit such as a control circuit and an image signal processing circuit and the actual drive signal level of each pixel. SOLUTION: Sampling pulses of 0V and 5V outputted from a logic circuit LOGj have their high-potential side shifted to 10V and their low-potential sides to-8V respectively by two series-connected stages of level shifts LS1j and LS2j. Thus, the need for an interface circuit etc., between the external circuit and scanning signal line driving circuit GD is eliminated to reduce the cost and power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type image display device in which pixels are arranged in a matrix on a substrate, and more particularly to an improvement in a driving circuit for driving each pixel for display.

[0002]

2. Description of the Related Art Conventionally, liquid crystal elements, EL (electroluminescence) elements and LEDs (light emitting diodes)
An image display device in which elements and the like are arranged in a matrix is used. A liquid crystal display device will be described below as an example of such a matrix type image display device. FIG. 11 is a front view showing a schematic configuration of a general liquid crystal display device 1. This liquid crystal display device 1 generally includes
A pixel array ARY in which a large number of pixels PIX are formed, a scanning signal line driving circuit gd and a data signal line driving circuit sd for displaying and driving the pixels PIX, and drive control of these signal line driving circuits gd and sd. Control circuit 2 for
It is comprised including.

On the pixel array ARY, a large number of scanning signal lines GL _j (j = 1, 2,..., N) and data signal lines SL _i (i = 1, 2,. Are formed, and two adjacent scanning signal lines GL _j , GL
The pixels PIX are to be formed in an area surrounded by _{j + 1} and the data signal lines SL _i and SL _{i + 1,} and the pixels PIX are arranged in a matrix.

The data signal line driving circuit sd samples the input image signal DAT in synchronization with a timing signal such as a clock signal CKS from the control circuit 2, and amplifies the image signal DAT as necessary. Data signal line SL
Output to _i . The scanning signal line drive circuit gd a clock signal CKG from the control circuit 2, in synchronization with the timing signals such as GPS, sequentially selects the scanning signal lines GL _j, to be described later are provided in the pixel PIX Controls opening and closing of switching elements. Thus, the data signal line SL
_i , the image signal (data) DAT output to each pixel PI
X, the image data DAT is held until the next scanning timing, and display output is performed.

The data signal line driving circuit sd has an image
Data DAT is transferred to each data signal line SL _iOutput to
At first, the scanning signal line GL_jLine selected by
Point order in which image data DAT is sequentially output to pixels of
Next driving method and image data D
A line-sequential driving method for outputting an AT is known.
As a data signal of a dot sequential driving method with a simple circuit configuration
The line drive circuit will be described with reference to FIG.

FIG. 12 is a block diagram showing an electrical configuration of a typical conventional data signal line drive circuit sd.
Above the respective data signal lines SL _i, analog switches as
w _i is interposed, and this analog switch asw _i
There When turned on, the image data DAT is output is sampled to the data signal line SL _i. To control these analog switches asw _i, scanning circuit srs _i corresponding individually to the respective analog switches asw _i
(I = the 1, 2, ..., m) and is provided with a buffer bufs _i.

The scanning circuits srs _i are cascaded with each other, and a clock signal CKS is commonly input to each scanning circuit srs _i . Also, the scanning circuit sr at the start end
The s _1, is given a start pulse SPS created based on such a horizontal synchronizing signal. Therefore, from each scanning circuit srs _i , a sampling pulse is sequentially output from the scanning circuit srs ₁ on the starting end side, and this sampling pulse is held and amplified in the buffer bufs _{i and} , if necessary, It is inverted, given the respective analog switches asw _i.

As shown in FIG. 13, for example, the scanning signal line driving circuit gd includes a scanning circuit srg _k (k = 1, 2,..., N + 1) similar to the scanning circuit srs _i and each scanning signal line. each GL _j corresponding to that two logical product circuits and1 _j, and2 _j and buffer BUFG _j
It is comprised including. Each of the scanning circuits srg _k is cascade-connected to each other similarly to the above-described scanning circuit srs _i. A start pulse SPG generated based on a vertical synchronizing signal or the like is input to the scanning circuit srg ₁ at the start end. The SPGs are sequentially output to the subsequent scanning circuits srg ₂ , srg ₃ ,... In response to a clock signal CKG generated based on a horizontal synchronization signal or the like.

Each scanning circuit srg _j , sr adjacent to each other
The output from the g _{j + 1,} after being calculated in the AND circuit and1 _j, is further input to the AND circuit and2 are computed and the clock signal GPS in _j buffer BUFG _j. Each of the scanning circuits srg _k outputs the start pulse SPG with a delay of a half cycle in response to the clock signal CKG. That is, the scanning circuit srg _j
Are rising at the rising timing of the clock signal CKG and are held for one cycle until the next rising timing, and the next stage scanning circuit sr
g _{j + 1} outputs a pulse for one period from the falling timing of the clock signal CKG. That is, the adjacent scanning circuit srg _j, srg _{j +} pulses shifted by a half period between ₁ is to be inputted to the AND circuit and1 _j, the logical product circuit and1 from _j clock signal CK
The length of the pulse of the half cycle of G is output to the AND circuit and2 _j.

The clock signal GPS is, for example,
It is twice as fast as the clock signal CKG,
Is a logical product circuit and2_jThe pulse output from
Cycle of the clock signal CKG is shorter than 1/2,
Adjacent AND circuit and2 _j, And2_{j + 1}Between, this
Pulses do not create periods that overlap with each other. Up
AND circuit and2_jOutput from buffer buf
g_jAmplified and inverted as necessary
The scanning signal lines GL_jOutput to
You.

Here, the drive voltage of each signal line drive circuit gd, sd will be considered. In the data signal line drive circuit sd, a VGA (Video Graphi) is used when the scanning circuit srs _i is not subjected to a desired frequency, for example, when the scanning signal line drive circuit gd is not parallelized or simultaneously sampled.
cal Array) display, about 25.2 MH
z can be driven, and the analog switch as
w _i data signal lines image data DAT of positive and negative polarities in S
It is determined from the request, such that it is capable of outputting the L _i, generally is determined by the request from the analog switch asw _i than requests from the scanning circuit srs _i. For example, when the liquid crystal driving voltage is ± 5 V and the voltage of the counter electrode is 0 V,
Level of the image signal in the data signal line SL _i is -5 to +5
V, and the driving voltage of the data signal line driving circuit sd is also −
It becomes about 5 to + 5V.

On the other hand, in the scanning signal line driving circuit gd, the switching element in the pixel PIX determines the driving voltage on the positive side so that the positive image data can be written to the pixel capacitance. The driving voltage on the negative polarity side is determined so that the negative polarity image data can be held for one frame period. For example, in order to satisfy these conditions, when the threshold voltage of the switching element is +3 V, the driving signal level of the scanning signal line driving circuit gd is set to +3 V on the positive polarity side, and the level of the image signal +5 V on the positive polarity side. And the margin + 2V are added, and on the negative polarity side, the voltage is about -8V obtained by adding -5V which is the level of the image data DAT to the above + 3V and the margin -6V. Here, the drive signal level is a level of an output signal in each signal line drive circuit gd · sd, and can be the same as a drive voltage of these signal line drive circuits gd · sd.

The above-described drive voltages and drive signal levels are merely examples, and their optimum values vary depending on the drive method, drive circuit configuration, transistor characteristics, type of liquid crystal, and the like.

[0014]

As described above, in the liquid crystal display device, in order to display and drive the liquid crystal as described above,
It is necessary to apply a positive and negative 5V the voltage across, and whereas the analog switch asw _i of the data signal line driving circuit sd is a CMOS configuration for handling the image data DAT of positive and negative polarities, the scanning signal lines The switching element in the pixel PIX controlled by the drive circuit gd is N
Due to the single-channel configuration such as MOS, the driving voltage of the data signal line driving circuit sd and the scanning signal line driving circuit gd is generally a voltage used in a general integrated circuit, for example, 3.3 V. Or greater than 5V,
In addition, the voltage levels are often different from each other.

For this reason, the clock signals CKS; CKG, GP to be input to the respective signal line driving circuits sd, gd.
It is necessary to increase the amplitude of S and the start pulses SPS, SPG, etc., and to a desired level. Therefore, the control circuit 2 for controlling the signal line drive circuits sd and gd and an interface circuit for converting the output of an external circuit such as an image signal processing circuit to a desired voltage level are required. There is a problem that power consumption is increased.

Another conventional technique for solving such a problem is disclosed in Japanese Patent Application Laid-Open No. Hei 6-95073. In this prior art, the input amplitude to the data signal line driving circuit and the scanning signal line driving circuit is adjusted to 5V (0V-5V), and a desired output amplitude level is set by a level shift circuit provided inside each driving circuit. 15V
(0V-15V). Thereby, the amplitude of the input signal is reduced, and the load on the external interface circuit is reduced.

However, in this prior art, one voltage level of an input signal, in this example, only the high potential side is shifted, and the input signal levels of both the data signal line driving circuit and the scanning signal line driving circuit are made the same. Is raised to the level of the drive signal. Therefore, there is a problem that the method cannot be applied when the optimum values of the driving signal levels of the data signal line driving circuit and the scanning signal line driving circuit are different from each other as described above.

An object of the present invention is to provide a data signal line driving circuit and a scanning signal line driving circuit, each of which has an optimized driving signal level. It is an object of the present invention to provide a matrix-type image display device which can simplify the configuration and reduce power consumption by making the same and lower.

[0019]

According to the present invention, there is provided a matrix type image display device in which pixels provided with switching elements are arranged in a matrix in an area divided by scanning signal lines and data signal lines. And a scanning signal line driving circuit for driving the scanning signal line; and a data signal line driving circuit for driving the data signal line. And a first and a second level shift circuit for shifting the voltage level of the scan signal line. The first and the second level shift circuit are provided in at least one of the scan signal line drive circuit and the data signal line drive circuit. The voltage level shifted by the level shift circuit is further shifted by the other level shift circuit.

In the matrix type image display device according to the present invention, in the matrix type image display device described above, further, the first level shift circuit shifts a voltage level on a high potential side of a signal line to be driven. It is preferable that the two-level shift circuit shifts the voltage level on the low potential side of the signal line to be driven.

In the matrix type image display device according to the present invention, in the above matrix type image display device, the voltage level shifted by the first level shift circuit is further shifted by the second level shift circuit. Preferably.

A matrix type image display device according to the present invention comprises a substrate on which pixels for displaying an image are arranged in a matrix, and a scanning signal line driving circuit for selectively supplying image data to each of the pixels. And a data signal line driving circuit, at least one of the scanning signal line driving circuit and the data signal line driving circuit is provided at an output stage to the scanning signal line or the data signal line. There is provided a two-stage level shift circuit, wherein the voltage level shifted by one level shift circuit is further shifted by the other level shift circuit.

In the matrix type image display device according to the present invention, in the matrix type image display device described above, the two-stage level shift circuit may further comprise a first level shift circuit for shifting a high potential side voltage level, And a second level shift circuit for shifting the voltage level on the low potential side.

According to the matrix type image display device of the present invention, in the matrix type image display device described above, the voltage level shifted by the first level shift circuit is further changed by the second level shift circuit. Preferably, it is shifted.

According to the above configuration, even if an input signal having a low voltage, for example, an amplitude of 5 V from an external circuit such as a control circuit or an image signal processing circuit is directly input to each signal line driving circuit, the signal is not affected. The line drive circuit is provided in the output stage.
The level shift circuit of the stage can shift the voltage level of the output signal to the optimum level on both the low potential side and the high potential side.

Therefore, the load on the external circuit can be reduced, the structure can be simplified and the power consumption can be reduced, and an optimum drive signal level suitable for the drive circuit configuration and the display medium can be obtained. Display quality can be improved.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
The following is a description based on FIGS. 1 to 7.

FIG. 1 is a block diagram showing an electrical configuration of a scanning signal line driving circuit GD according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the scanning signal line driving circuit GD. FIG. 3 is a block diagram showing an electrical configuration of the data signal line drive circuit SD according to one embodiment of the present invention. These signal line drive circuits GD and SD can be used in place of the conventional signal line drive circuits gd and sd in the general liquid crystal display device 1 described above.

The scanning signal line driving circuit GD includes a scanning circuit SRG _j (j = 1, 2,..., N) corresponding to each of the scanning signal lines GL _j , a logic circuit LOG _j , a level shifter LS1 _j , Level shifter LS2 _j and buffer BU
F _j .

The scanning circuit SRG _j is realized by a shift register, connected in cascade to each other. These scan circuits SRG _j, in common, from the control circuit 2, is created based on such a horizontal synchronizing signal, a clock signal CKG as shown in FIG. 2 (a) is input. In addition, the start of the scanning circuit SRG _1, from the control circuit 2, are created on the basis of such a vertical synchronizing signal, a start pulse SPG as shown in FIG. 2 (b) is input, the residual of the scanning circuit SRG Outputs from the preceding scanning circuits SRG _{1 to} SRG _n−1 are given to _{2 to} SRG _n , respectively. Therefore, the start pulse SPG is sequentially transmitted to the subsequent scanning circuit in response to the clock signal CKG.

[0031] The output from each of the scanning circuits SRG _j, is input to the corresponding logic circuit LOG _j. These logic circuits LOG _j Further, as shown in FIG. 2 (c), the example is a clock signal GPS twice the frequency of the clock signal CKG, is input from the control circuit 2. Logic circuit LOG _j, as shown in FIG. 2 (d), the only output and the period clock signal GPS is at a high level both from the scanning circuit SRG _j, derives a high-level output. Therefore, this logic circuit LOG _j
Is at a high level almost for a period of 1/4 of the clock signal CKG, and the logic circuit LOG
_The high-level periods of _j-1 and LOG _{j + 1} do not overlap each other.

The above scanning circuit SRG_jAnd logic circuit LO
G_jCorresponds to the control circuit 2 and an image signal processing circuit (not shown).
Like the road, the driving voltage is 5 V, and therefore
Logic circuit LOG_jOutput voltage level is 0V / 5V
Become. This logic circuit LOG_jOutput from the first level
Lucifer LS1_jIn FIG. 2, as shown in FIG.
The voltage level is converted to 0V / 10V,
Level shifter LS2 _jIn FIG. 2 (f),
Thus, it is converted to -8V / 10V. Level shifter LS
2_jOutput from the buffer BUF_jAmplified in
And, if necessary, inverting the scanning signals
Line GL_jOutput to Scan signal line GL _jVoltage level
Is as shown in FIG. 2 (g).

The data signal line driving circuit SD
Data signal line SL_iScanning circuit SR provided individually for each
S_i(I = 1, 2,..., M), the logic circuit LOS_i,
Level shifter LS3_iAnd sampling circuit SMP_i
It is provided with. Scan circuit SRS_iRun above
Inspection circuit SRG_jAre connected in cascade as in
These scanning circuits SRS_iThe control circuit 2
Clock signal CKS is input from the
Road SRS₁Is created based on the horizontal sync signal, etc.
The input start pulse SPS is input, and the remaining scanning circuit S
RS_Two~ SRS _mHas a scanning circuit SRS₁~ S
RS_m-1Are input.

The output from the scanning circuit SRS _i via a logic circuit LOS _i which is realized by a latch circuit, is input to the level shifter LS3 _i. Level shifter LS3 _i
It is to level-shift the low potential side of 0V / 5V signals from said logic circuit LOS _i, is converted to -5V / 5V,
And outputs it to the sampling circuit SMP _i. by this,
Image data DAT from the control circuit 2 is sampled and output to the data signal lines SL _i.

FIG. 4 shows the level shifters LS1 _j and LS.
It is an electric circuit diagram showing a specific configuration of the 2 _j. Logic circuit L
The output stage of the OG _j is constituted by a CMOS inverter consisting of transistors Q01, Q02, from the output stage, each of the two lines L01, L02, mutually signals antiphase 0V / 5V output Is done.

The input signals of 0 V / 5 V input from the lines L01 and L02 are input to the gates of the transistors Q11 and Q12 of the level shifter LS1 _j , respectively. The transistors Q11 and Q12 are formed of NMOSs, and their sources are commonly connected to a low-potential 0V power supply line PL1. The drain of the transistor Q11 is connected to the drain of the transistor Q13 and the gate of the transistor Q14. The drain of the transistor Q12 is connected to the drain of the transistor Q14 and the gate of the transistor Q13. The transistors Q13 and Q14 are formed of PMOS, and their sources are commonly connected to a high-potential 10V power line PL2. Outputs are led out from the drains of the transistors Q11 and Q12 to lines L11 and L12, respectively.

Therefore, the voltage of the line L01 is 5V.
When the line L02 is at 0 V, the transistor
Q11 and Q14 become conductive, and transistors Q12 and Q13
Is cut off, the line L11 becomes 0 V, and the line L12
Becomes 10V. On the other hand, when the line L01 is at 0V,
And when the line L02 is at 5V, the transistor
Transistors Q11 and Q14 shut off, and transistors Q12 and Q1
3 conducts, the line L11 becomes 10 V, and the line L
12 becomes 0V. Thus, the logic circuit LOG _jfrom
The voltage level on the high potential side of the input signal level 0V / 5V is
This level shifter LS1_jIs shifted to 10V by
You.

[0038] the line L11, L12 are respectively connected to the gates of the transistors Q21, Q22 of the level shifter LS2 _j. Transistors Q21, Q22
Is composed of a PMOS, and the source is commonly connected to the power supply line PL2 of 10V. Transistor Q21
Is connected to the drain of the transistor Q23 and the gate of the transistor Q24, and the drain of the transistor Q22 is connected to the drain of the transistor Q24 and the gate of the transistor Q23. The transistors Q23 and Q24 are composed of NMOSs, and have a common low potential -8V power supply line P.
L3. The drains of the transistors Q21, Q23, the output line L2 of the buffer BUF _j are connected.

Therefore, when the line L11 is at 10 V and the line L12 is at 0 V, the transistors Q22 and Q23 conduct, and the transistors Q21 and Q24
Is cut off, and the output line L2 becomes -8V. On the other hand, the line L11 is at 0V and the line L12 is at 10V.
When the voltage is V, the transistors Q21 and Q24 conduct, the transistors Q22 and Q23 shut off, and the output line L2 becomes 10V.

[0040] Thus, by the level shifter LS2 _j, the voltage level of the low potential side is outputted is shifted from 0V to -8 V.

The level shifter LS3 _i in the data signal line drive circuit SD shifts the voltage level on the low potential side of the input signal level 0V / 5V from the logic circuit LOS _i to -5V, and therefore, the scan signal line drive Circuit G
It is configured similarly to the level shifter LS2 _j in D.

The signal line driving circuit G configured as described above
The element structure of the transistors constituting D and SD is shown, for example, in FIG. FIG. 5 shows the signal line driving circuit GD,
FIG. 3 is a cross-sectional view schematically showing an element structure of a transistor constituting SD. In FIG. 5, reference numerals TG, TS,
TD is a gate electrode, a source region, and a drain region, respectively, reference numeral CNL is a channel region, and reference numeral RAY is a gate insulating film.

FIG. 5A shows a scanning circuit SRG._j, SRS
_iAnd logic circuit LOG_j, LOS _iTo configure
It is a transistor and is called a single drain structure.
Is a transistor having a simple structure. This tran
In the case of a transistor, an ion
The source region TS and the drain region in a self-aligned manner.
A TD is formed.

On the other hand, the level shifters LS1 _j , L
S2 _j ; LS3 _i , the transistors used in the buffer BUF _j and the sampling circuit SMP _i are high breakdown voltage transistors. This transistor is shown in FIG.
The structure is as shown in FIGS.

The transistor shown in FIG. 5B has a longer channel length than the transistor shown in FIG. 5A, as indicated by reference numeral CNLa.

In general, when the channel length is increased, the electric field between the source and the drain is reduced, and the breakdown voltage of the element (source / drain) is reduced.
It is known that the drain-to-drain withstand voltage and the applied voltage at which the transistor does not deteriorate during long-term operation) are improved.
Further, as the channel length increases, the performance (driving ability) of the transistor decreases. If a transistor having an excessively long channel length is used, as a result, the signal line driving circuit GD · S
This impairs the characteristics of D or the characteristics of the entire display device. Therefore, the upper limit of the channel length of the transistor shown in FIG. 5B is determined so that the characteristics of the signal line driving circuits GD and SD or the characteristics of the entire display device can be sufficiently obtained.

The active layer of the transistor shown in FIG. 5B can be manufactured by polycrystallizing an amorphous silicon thin film. There are a plurality of methods for polycrystallizing the amorphous silicon thin film. The methods are roughly classified into a method of polycrystallizing by heat treatment, a method of polycrystallizing by laser irradiation, and a method of combining these two methods. Further, there is also a method of combining these methods with a method of promoting crystallization using a metal catalyst. In the formation of the active layer by the above method, the correlation between the channel length of the transistor to be formed and the element withstand voltage differs depending on conditions such as the temperature and time of the heat treatment and the output of the laser.

For example, in a polycrystalline silicon thin film transistor manufactured by polycrystallization of an amorphous silicon thin film under a certain method and condition and capable of obtaining a device withstand voltage of 5 to 7 V with a channel length of 3 μm, an element of 10 V or more In order to ensure a withstand voltage, the channel length is required to be 4.5 μm or more, and in order to ensure an element withstand voltage of 15 V or more, the channel length is required to be 6 μm or more. In addition, the length of the channel length of this transistor that does not impair the characteristics of the signal line driver circuits GD / SD or the characteristics of the entire display device is preferably 10 μm or less, more preferably 8 μm or less.

A channel length of 2 μm manufactured by changing the method and conditions for polycrystallization of the amorphous silicon thin film.
In a transistor capable of obtaining an element withstand voltage of 5 to 7 V, a channel length of 3 μm or more is required to secure an element withstand voltage of 10 V or more, and a channel length is required to secure an element withstand voltage of 15 V or more. 4.5 μm or more is required. The upper limit of the channel length in this transistor is preferably 8 μm, and more preferably 6 μm.
m.

Further, in a transistor obtained by further changing the method and conditions for polycrystallization of the amorphous silicon thin film and obtaining a device withstand voltage of 5 to 7 V with a channel length of 4 μm, 1
The channel length is required to be 6 μm or more in order to secure the element withstand voltage of 0 V or more, and the channel length is required to be 8 μm or more in order to secure the element withstand voltage of 15 V or more. The upper limit of the channel length in this transistor is preferably 12 μm, and more preferably 10 μm.

[0051] For example, in the configuration of the scanning signal line drive circuit GD in FIG. 1, the scanning circuit SRG _j and a logic circuit L
The transistor used for OG _j has a channel length of 3 μm.
5A is driven at a driving voltage of 5 V and the level shifter LS1 _j · L is used.
As transistor used in S2 _j, and a buffer BUF _j, channel length with transistor shown in FIG. 5 (b) of 7 [mu] m, to no voltage 10V is driven at 18V. With such a configuration, a high-speed and highly reliable scanning signal line driving circuit GD can be realized.

As described above, the correlation between the channel length and the improvement in the withstand voltage of the element differs depending on the method of manufacturing the transistor (particularly the active layer) and the structure (size and the like) of the transistor. When used for GD / SD, if the channel length of the transistor shown in FIG. 5B is 1.5 to 3 times the channel length of the transistor shown in FIG. Regardless of the method and conditions of polycrystallization of the amorphous silicon thin film for forming the layer, and the structure (size, etc.) of the transistor,
A favorable element withstand voltage can be obtained. If the ratio of the channel length of the transistors used for the level shifters LS1 _j , LS2 _j and LS3 _i in the signal line drive circuit GD / SD to the transistor used in the circuit at the preceding stage is within this range, the signal line drive circuit GD · SD Works most efficiently.

In the transistor shown in FIG. 5C, as indicated by reference numeral RAYa, the gate insulating film is formed to be thicker than the transistor shown in FIG. 5A.

In general, as the thickness of the gate insulating film increases, the device breakdown voltage increases in proportion to the thickness. However,
It is also known that, depending on the film formation method, the breakdown voltage rapidly decreases below a certain film thickness due to defects or the like. Also,
As the thickness of the gate insulating film increases, the performance (driving ability) of the transistor decreases. When a transistor having an excessively thick gate insulating film is used, as a result, the signal line driving circuit GD · S
This impairs the characteristics of D or the characteristics of the entire display device. Therefore, the upper limit of the thickness of the gate insulating film of the transistor shown in FIG. 5C is determined so that the characteristics of the signal line driving circuits GD and SD or the characteristics of the entire display device can be sufficiently obtained.

The gate insulating film of the transistor as shown in FIG. 5C is formed by a CVD (Chemical Va) method.
por deposition method). As the CVD method, there are methods such as a thermal CVD method and a plasma CVD method, and the film quality of a gate insulating film to be formed differs depending on conditions such as a kind of gas used and a reaction temperature. Therefore, the correlation between the film thickness of the gate insulating film of the transistor to be formed and the element withstand voltage differs depending on each condition.

For example, CVD under a certain method and condition
In a polycrystalline silicon thin-film transistor in which a gate insulating film is formed by a method and has a gate insulating film thickness of 80 nm and an element withstand voltage of about 10 V, in order to obtain an element withstand voltage of 15 V or more, the thickness of the gate insulating film is required. Is 100n
m or more, and a gate insulating film thickness of 120 nm or more is required in order to secure an element breakdown voltage of 20 V or more. In this transistor, the thickness of the gate insulating film that does not impair the characteristics of the signal line driving circuits GD / SD or the characteristics of the entire display device is preferably 20.
0 nm or less, more preferably 150 nm or less.

In order to obtain an element withstand voltage of 15 V or more in a polycrystalline silicon thin film transistor having a gate insulating film thickness of 90 nm and an element withstand voltage of about 10 V by changing the method and conditions of the CVD method described above. The thickness of the gate insulating film must be 110 nm or more, and the gate insulating film must have a thickness of 130 nm or more in order to ensure an element breakdown voltage of 20 V or more. The upper limit of the thickness of the gate insulating film in this transistor is preferably 220 n
m, more preferably 180 nm.

In order to obtain an element breakdown voltage of 15 V or more in a polycrystalline silicon thin film transistor having a gate insulation film thickness of 100 nm and an element breakdown voltage of about 10 V, the method and conditions of the CVD method are further changed. Means that the thickness of the gate insulating film needs to be 125 nm or more,
In order to secure the above element breakdown voltage, the gate insulating film needs to have a thickness of 150 nm or more. The upper limit of the thickness of the gate insulating film in this transistor is preferably 250 nm, and more preferably 220 nm.

[0059] For example, in the configuration of the scanning signal line drive circuit GD in FIG. 1, the scanning circuit SRG _j and a logic circuit L
As transistor used in OG _j, the film thickness of the gate insulating film using the transistor shown is a diagram of 80nm 5 (a), together with the driving by the driving voltage 5V, level shifter L
As transistor used in S1 _j · LS2 _j and buffer BUF _j, the film thickness of the gate insulating film by using the transistor shown in FIG. 5 (c) of 120 nm, to no voltage 10V is driven at 18V. With such a configuration, a high-speed and highly reliable scanning signal line driving circuit GD can be realized.

As described above, the correlation between the degree of the film thickness and the improvement of the element withstand voltage varies depending on the method of forming the gate insulating film, the heat treatment conditions, the structure (size, etc.) of the transistor, etc. When used for the circuit GD / SD,
If the thickness of the gate insulating film of the transistor shown in FIG. 5C is 1.25 to 2.5 times the thickness of the gate insulating film of the transistor shown in FIG. 5A, the gate insulating film is formed. A preferable element withstand voltage can be obtained irrespective of the conditions of the CVD method or the structure (size, etc.) of the transistor. If the ratio of the thickness of the gate insulating film between the transistor used for the level shifters LS1 _j , LS2 _j and LS3 _i in the signal line drive circuit GD / SD and the transistor used for the circuit on the preceding stage is within this range, the signal line drive is performed. The circuit GD / SD operates most efficiently.

On the other hand, the transistor shown in FIG.
This is a transistor called an LDD structure. The transistor includes a channel region CNL and a source region TS
A region having a low impurity concentration indicated by the reference numeral LDD, that is, a region having a relatively low impurity doping amount per area, and a region (LDD region, Lig).
htly Doped Drain region).

What affects the characteristics of the transistor is
Actually, it is an impurity concentration per volume, but here, as a condition of the manufacturing process, an impurity doping amount per area is a characteristic of the LDD region. In a normal transistor manufacturing process, since most of the implanted impurities are set to enter the active layer, the value obtained by dividing the impurity doping amount per area by the film thickness of the active layer is the impurity concentration per volume. Become. The impurity doping amount per area in the source region TS and the drain region TD is 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² , whereas the impurity doping amount per area in the region LDD is preferably 1 × 10 ¹⁵ / cm ^2. 10 ¹² -1 × 10 ¹⁴ / cm ²
And more preferably 5 × 10 ^{12 to} 5 × 10 ¹³ / c.
m ² .

As described above, it is known that the device withstand voltage can be improved by relaxing the electric field between the source and the drain. As one method of realizing this electric field relaxation, an LDD structure (Lightly Doped Dra
in structure). This is a structure in which a junction region of a transistor (a pn junction region between a source and a drain) is an LDD region having a low impurity doping amount per area, and a depletion layer width in this region is widened, thereby relaxing the electric field. is there.

The junction region of the transistor shown in FIG. 5D can be formed by self-alignment injection. The correlation between the impurity doping amount per area of the junction region and the relaxation of the electric field between the source and the drain in this transistor differs depending on the method of manufacturing the transistor (particularly, the junction region). In the case of a transistor having a region,
In a transistor having a channel length of 5 μm and not having the LDD structure, the element withstand voltage is about 5 to 7 V. On the other hand, 2 ×
L of about 10 ¹³ / cm ² , that is, an impurity doping amount per area of 5 × 10 ^{12 to} 5 × 10 ¹³ / cm ²
In a transistor having a DD region, the channel length is 5 μm
Thus, a device withstand voltage of 15 V or more can be secured.

The impurity doping amount per area of the LDD region in this transistor is determined so that the resistance of this region is substantially equal to the on-resistance of the channel. The impurity doping amount per area of this region is 1 × 10 ¹⁴
If it exceeds / cm ² , the resistance of this region becomes too small, and most of the applied voltage is applied to the channel region of the transistor. Therefore, the electric field between the source and the drain cannot be reduced. When the impurity doping amount per area of this region is 1 × 10 ¹² / cm ² or less, the reliability of the transistor is improved, but the resistance of this region becomes too large, and the driving capability of the transistor is increased. Will be reduced. Therefore, the impurity doping amount per area of the region LDD in the transistor shown in FIG. 5D is preferably 1 × 10 ¹² to 1 × 10 ¹⁴ / cm ² when used for the signal line driving circuit GD / SD. And more preferably 5 × 10 ^{12 to} 5 × 10 ¹³ / cm ²
It is.

In the formation of the LDD region of the transistor by the self-aligned implantation, the film quality of the active layer, the interface state between the gate insulating film and the active layer, the width of the LDD region, the type of the implanted impurity, the implantation energy, and the The correlation between the impurity doping amount per area of the LDD region and the device withstand voltage differs depending on the activation conditions and the like. However, if the impurity doping amount per area is within the above range, a preferable device withstand voltage can be obtained.

[0067] For example, in the configuration of the scanning signal line drive circuit GD in FIG. 1, the scanning circuit SRG _j and a logic circuit L
As transistor used in OG _j, using the transistors shown in FIG. 5 of the single drain structure (structure without an LDD region) (a), together with the driving by the driving voltage 5V, level shifters LS1 _j · LS2 _j and buffer B
As transistor used in UF _j, impurity doping amount per area using the transistor shown in FIG. 5 (d) having a LDD region of ² × 10 ¹³ / cm 2, voltage 1
Drive at 0V to 18V. With such a configuration, a high-speed and highly reliable scanning signal line driving circuit G
D can be realized.

The transistor shown in FIG.
This transistor is called an offset structure, and has a region (offset region) between the channel region CNL and the source region TS and the drain region TD, which is not doped with an impurity indicated by reference numeral OFF. Further, the transistor shown in FIG. 5F is a transistor called a multi-gate structure, and is denoted by CNL.
1, a plurality of channels are connected in series as shown by CNL2.

The transistors having the structures shown in FIGS. 5 (d) to 5 (f) have the same channel length and the same gate film thickness, all having the structure shown in FIG. 5 (a). The breakdown voltage between the source and the drain can be made larger than that. Therefore, with such a structure, the withstand voltage of the transistor can be increased. The structure shown in FIG. 5 (b) and FIGS. 5 (d) to 5 (f) particularly
This is very effective because it can be formed in the same step as the structure shown in FIG. Further, by applying at least one of the structures shown in FIGS. 5B and 5C to the transistors having the structures shown in FIGS. 5D to 5F, the breakdown voltage can be further reduced. Can be enhanced.
Thus, a desired breakdown voltage can be obtained for each transistor in the signal line drive circuits GD and SD, and reliability can be improved.

The scanning circuits SRG _j , SRS
_i is realized by a configuration as shown in FIG. 6, for example. Each of the scanning circuits SRG _j and SRS _i includes two clocked inverters INV1 and INV2 having a CMOS structure and an inverter INV3. The input terminal of the inverter INV1 has the start pulse SPG,
The output of the SPS or the preceding scanning circuit is input. In FIG. 6, the clock signals CKG and CKS are input to a clock input terminal indicated by reference numeral CK, and the clock signals CKG and CKS are obtained by inverting the clock signals CKG and CKS to a clock input terminal indicated by reference numeral / CK. Clock signal is input.

The output of the inverter INV1 is inverted by the inverter INV3 and output to the logic circuits LOG _j and LOS _{i and} to the next scanning circuit. This output is fed back to the input side of the inverter INV3 by the inverter INV2. Thus,
Each of the scanning circuits SRG _j and SRS _i receives the clock signal CK.
G, CKS, and sequentially start pulse S
PG and SPS can be held for a period of one cycle of the clock signals CKG and CKS.

The pixel PIX driven by the signal line driving circuits GD and SD configured as described above is configured, for example, as shown in FIG. FIG. 7 is an electric circuit diagram schematically showing an electric configuration of each pixel PIX. Each pixel PIX includes a generally-are the switching element, a field effect transistor SW which is selected taking the signal level of the data signal line SL _i when the scanning signal line GL _j becomes high level, the The signal level taken in by the field effect transistor SW is provided with a pixel capacitance applied to one electrode. The pixel capacitance is composed of a liquid crystal capacitance CL and an auxiliary capacitance CS added as necessary.

[0073] When the scanning signal line GL _j becomes high level, the drain of the field effect transistor SW - conducting between the source and the one electrode of the data signal line SL _i and the liquid crystal capacitance CL and the auxiliary capacitor CS is connected You. Liquid crystal capacity CL
Is connected to a common electrode VP common to all pixels. In the case of the so-called CS-on-common structure shown in FIG. 7, the other electrode of the auxiliary capacitance CS is connected to the counter electrode VP, similarly to the liquid crystal capacitance CL.
Thus, captured from the data signal line SL _i, the voltage applied to the liquid crystal capacitor CL, the liquid crystal of the transmittance or reflectance is modulated, it is possible to perform image display.

[0074] CS Onkomon structure shown in FIG. 7, the capacitance of the scanning signal line GL _j can be reduced, the burden of the scanning signal line drive circuit GD is lighter, is suitably carried out in the pixel array of a relatively large area.

As described above, the scanning signal line driving circuit GD and the data signal line driving circuit SD according to the present invention are provided with the input from the external circuits such as the control circuit 2 for generating the clock signals CKG and CKS and the image signal processing circuit. As long as the signal level is within a range in which the signal line drive circuits GD and SD operate normally, each pixel PIX has an element structure of the field-effect transistor SW and an image signal level regardless of the voltage level. Level shifters LS1 _j , LS2 _j ; LS3 _i so that the corresponding optimum drive signal level is obtained.
Convert and give. Therefore, it is not necessary to add an interface circuit or the like to the external circuit, so that the configuration can be simplified and the power consumption can be reduced, and the pixel PIX can be driven at an optimal driving signal level to achieve high display quality. Can be obtained.

The level shifter LS1_j, LS2_j;
LS3_iAnd the buffer BUF at the subsequent stage_jAnd sa
Sampling circuit SMP_iAnd the level shifter LS1_j,
LS2_jLS3_iScanning circuit SRG before_j, S
RS_iAnd logic circuit LOG _j, LOS_iElement structure with
Are configured differently from each other,
High withstand voltage and high reliability
it can.

Furthermore, in general, the output stage of the data signal line drive circuit SD (in the example of FIG. 3, the sampling circuit SMP
_i ) has a CMOS configuration, whereas the field effect transistor SW of the pixel PIX has one channel (N in the example of FIG. 7).
Channel) configuration. Therefore, the high-potential-side voltage required when outputting a high-potential level is higher in the scanning signal line driving circuit GD than in the data signal line driving circuit SD.
Further, the period during which the field effect transistor SW should hold the image data DAT is longer than that of the output stage (the field effect transistor SW is one field, and the output stage of the data signal line driving circuit SD is one horizontal scanning cycle). On the other hand, the low-potential-side voltage required for holding the low voltage level is lower in the scanning signal line driving circuit GD than in the data signal line driving circuit SD.

Therefore, as in the present invention, one drive voltage (5 V in the example of FIG. 3) of the data signal line drive circuit SD is fixed, and the other drive voltage (0 V) of the data signal line drive circuit SD and Shifting the driving voltage of the scanning signal line driving circuit GD is more effective than shifting one of the three driving voltages while fixing one driving voltage of the scanning signal line driving circuit GD, and the level shifters LS1 _j , LS2 _j ; LS3. The maximum shift amount at _i can be reduced.

For example, in the case of the scanning signal line driving circuit GD shown in FIGS. 1 and 4, while the shift amount in the level shifter LS2 _j is −8 V, one driving of the scanning signal line driving circuit GD is performed. Voltage, for example 5 on the high potential side
When V is fixed, the shift amount of the level shifter LS2 _j needs to be −13V. As described above, when the shift amount in the level shifters LS1 _j , LS2 _j ; LS3 _i increases, the operation may become unstable or the signal delay may increase, whereas the scanning signal line driving circuit GD of the present invention may be used. , SD, such a problem can be solved by fixing one potential of the data signal line drive circuit SD.

Another embodiment of the present invention will be described with reference to FIGS.
The following is a description based on FIG.

FIG. 8 is a front view showing a schematic configuration of a liquid crystal display device 11 according to another embodiment of the present invention. In the liquid crystal display device 11, the signal line drive circuits GD and SD are:
It is formed integrally on the common substrate 12 together with the pixel array ARY. In the liquid crystal display device 1 shown in FIG.
The field effect transistor SW of the pixel PIX is made of amorphous silicon, and the signal line driving circuits GD and SD are formed of an integrated circuit external to the pixel array ARY.

On the other hand, due to demands for improving the driving force of the field effect transistor SW accompanying the recent increase in screen size, reducing the mounting cost of the signal line driving circuits GD and SD, and further improving the reliability of mounting. The pixel array ARY is monolithically formed using a polycrystalline silicon thin film on a quartz substrate.
And a signal line driving circuit GD, SD. Furthermore, with the aim of achieving a larger screen and lower cost, an attempt was made to form a field-effect transistor SW from a polycrystalline silicon thin film at a process temperature of about 600 ° C. or less, which is the strain point of the glass, using a glass substrate. Have been. Therefore, in the liquid crystal display device 11, the pixel array ARY and the signal line driving circuits GD and SD are integrally formed on the substrate 12 made of glass as described above.
To the control circuit 2 and the power supply voltage generating circuit 13.

The power supply voltage generating circuit 13 outputs a high-level voltage 5 V from the terminal VSH to the data signal line driving circuit SD, and outputs a low-level voltage − from the terminal VSL.
Outputs 5V. 0V from the terminal COM is applied to the substrate 12.
And a voltage of 0 V / 5 V of the counter electrode VP is applied from the terminal VP.

On the other hand, a high-level voltage of 10 V is output from the terminal VGH to the scanning signal line driving circuit GD,
The terminal VGL outputs a low-level voltage, -8V or -3V. This voltage level of the counter electrode VP is for corresponding to performing the AC driving by changing the above 0V / 5V, although the voltage level of the high potential side of the scanning signal line GL _j remains 10V, This is because the voltage level on the low potential side is -8 V when the voltage level of the counter electrode VP is 0 V, and is -3 V when the voltage level of the counter electrode VP is 5 V. Of course, in addition to this, the scanning circuits SRG _j and SRS _i and the logic circuit L
Power supply for driving OG _j , LOS _i, etc. (0 V / 5
V) is supplied to the signal line drive circuits GD and SD.

The pixel PIX in the liquid crystal display device 11
Is shown, for example, in FIG. Each pixel PIX
Generally comprises a field effect transistor SW and a pixel capacitance including a liquid crystal capacitance CL and an auxiliary capacitance CS. Gate of the field effect transistor SW is connected to the scanning signal line GL _j, the drain is the data signal line S
Is connected to L _i, the source is connected to one electrode of the liquid crystal capacitance CL and the auxiliary capacitor CS. Liquid crystal capacity CL
A drive voltage of 5 V / 0 V is applied from the power supply voltage generation circuit 13 to the opposite electrode VP, which is the other electrode of the above. The other electrode of the auxiliary capacitance CS is connected to the adjacent scanning signal line GLj _-1 .

The so-called CS-on thus configured
In the pixel PIX having the gate structure, the AC driving of the counter electrode VP is performed.
The scanning signal line which is the other electrode of the storage capacitor CS
GL _jAlso need to be AC driven with the same period and the same amplitude.
You. Therefore, the scanning signal line driving circuit GD is turned off.
Corresponding voltage, in the example of FIG. 9, a field effect transistor
Since SW has an NMOS configuration, the driving voltage on the low potential side
Must be varied in the above cycle.

For example, when the AC cycle is a two-field period, the drive signal level on the lower potential side of the odd field is lower than that of the even field, and when the AC cycle is the two horizontal scanning periods, the odd lines are even-numbered. The drive signal level on the lower potential side than the line is lowered. Thus, in order to change the drive signal level on the low potential side,
As described above, the power supply voltage generation circuit 13 supplies the level shifter L
By varying the power supply voltage input to the S2 _j, may be changed to shift amount in the level shifter LS2 _j.

[0088] By thus AC-driving the counter electrodes VP, the amplitude of the image data DAT to be output to the data signal line SL _i is reduced, the data signal line drive circuit SD
Power consumption can be reduced.

FIG. 10 shows a liquid crystal display device 11 as described above.
FIG. 6 is a waveform diagram for explaining the operation of FIG. The power supply voltage generation circuit 13 of the liquid crystal display device 11 switches the output voltage from the terminal VGL to the power supply line PL3 between -8V and -3V as described above, for example, in an odd field and an even field. Therefore, in an odd field set to -8 V, the operation is the same as that in FIG. 2 described above, whereas in an even field set to -3 V, the operation is as shown in FIG. FIGS. 10A to 10G respectively correspond to FIGS. 2A to 2G described above. In the even field, in response to the voltage VP of the counter electrode becomes 5V, the low potential side is -3V next output voltage from the level shifter LS2 _j, whereby the driving voltage of the scanning signal line GL _j is, -3V / It becomes 10V.

In this way, by connecting the other terminal of the storage capacitor CS to the adjacent scanning signal line GLj _-1 as shown in FIG. 9, the routing of the common electrode is reduced, and the aperture ratio is increased. Pixel with a CS-on-gate structure
When AC is driven by X, the field effect transistor S
The off-level of W can be adapted, and high-quality display can be performed.

[0091] The present invention is not limited to the liquid crystal display device 1, 11, the pixel PIX is formed in a matrix array regions are partitioned by the scanning signal line GL _j and the data signal line SL _i, and the pixel The present invention can be suitably applied to a matrix type display device including a switching element in PIX. The above-described drive voltage and drive signal level are merely examples, and the device structure and image data DAT
It is needless to say that an appropriate value is selected according to the amplitude level of.

[0092] In the first and second embodiments, the scanning signal line drive circuit GD is first and second level shifter, comprising a level shifter LS1 _j · LS2 _j, the data signal line drive circuit SD is a third LS which is a level shifter
3 _i is provided, but is not limited to this. In the present invention, the data signal line driving circuit SD may include the level shifters LS1 and LS2, and the scanning signal line driving circuit GD may include the level shifter LS3. That is, the data signal line driving circuit SD may include the level shifters LS1 _i and LS2 _i instead of LS3 _i , and the scanning signal line driving circuit GD may include LS3 _j instead of LS1 _j and LS2 _j . Further, the data signal line drive circuit SD is provided with a level shifter LS1 _i · LS instead of LS3 _i.
2 _i, and each of the signal line driving circuits GD and SD may include the level shifters LS1 and LS2. However, when the data signal line drive circuit SD is configured to include the level shifters LS1 _i and LS2 _i as described above, the difference in drive signal level between the data signal line drive circuit SD and the scan signal line drive circuit GD is determined. Must be taken into account. That is, it is necessary to adjust the amount of shift of the signal level by the level shifters LS1 _i and LS2 _i so that an optimal drive signal level for driving the data signal line is obtained. Similarly, the scanning signal line drive circuit GD is also in the case of a configuration including a level shifter LS3 _j, for optimum levels of the drive signal for driving the scanning signal lines is obtained, the signal level of the shift by the level shifter LS3 _j It is necessary to adjust the amount.

Further, in the matrix type image display device of the present invention, the scanning signal line driving circuit GD includes the above-described two-stage level shifters LS1 _j and LS2 _j to provide both the high potential side and the low potential side of the input signal level. The data signal line drive circuit SD that shifts the voltage level may have a configuration including a level shifter LS3 _i that shifts the voltage level of either the high potential side or the low potential side of the input signal level. This configuration can also be suitably applied to the liquid crystal display devices 1 and 11 described above.

Further, in the matrix type image display device of the present invention, when the pixel PIX is selected by the scanning signal, the switching element SW takes in the image data and supplies it to one electrode of the pixel capacitance, thereby forming the pixel capacitance. the other electrode of the storage capacitor CS that is connected to the adjacent scanning signal lines GL _J, image display by driving the display media by applying a voltage between the one electrode and the other opposing electrode of the pixel capacitor The above-mentioned counter electrode is AC-driven at a cycle whose voltage level is predetermined, and the scanning signal line driving circuit GD
A configuration may be adopted in which two level shifters LS1 _j and LS2 _j are provided, and the voltage shift amount of one of the level shifters changes in each cycle.

As described above, the matrix-type image display device according to the present invention comprises a substrate on which pixels for displaying an image are arranged in a matrix, and a substrate for selectively supplying image data to each of the pixels. In a matrix image display device including a scanning signal line driving circuit and a data signal line driving circuit, at least one of the scanning signal line driving circuit and the data signal line driving circuit includes a scanning signal line or a data signal line. It is preferable that the output stage to the signal line includes a two-stage level shift circuit connected in series to each other.

According to the above configuration, even if an input signal having a low voltage, for example, an amplitude of 5 V, from an external circuit such as a control circuit or an image signal processing circuit is directly input to each signal line driving circuit, The line drive circuit is provided in the output stage.
The level shift circuit of the stage can shift the voltage level of the output signal to the optimum level on both the low potential side and the high potential side.

Therefore, the load on the external circuit can be reduced, the structure can be simplified and the power consumption can be reduced, and an optimum drive signal level suitable for the drive circuit structure and the display medium can be obtained. Display quality can be improved.

Further, in the matrix type image display device according to the present invention, the driving signal levels of the scanning signal line driving circuit and the data signal line driving circuit are different from each other, and the scanning signal line driving circuit and the data signal line driving circuit are different from each other. Preferably, the input signal levels to the circuit are equal to each other.

According to the above arrangement, the driving signal levels of the scanning signal line driving circuit for opening and closing the switching element formed in each pixel and the data signal line driving circuit for inputting image data to the switching element are as follows. In contrast, the levels of the input signals to the data signal line driving circuit and the scanning signal line driving circuit, for example, the clock signal and the start pulse are aligned with each other. ing.

Therefore, even if the output voltage of the external circuit and the driving signal levels of the scanning signal line and the data signal line are optimized, the output voltage of the external circuit, the data signal line driving circuit and the scanning signal There is no need to add a level conversion circuit or the like for matching the input voltage of the line drive circuit, and the burden on the external circuit can be reduced.

Further, in the matrix type image display device according to the present invention, the scanning signal line driving circuit includes the two-stage level shift circuit, and is provided on the high potential side and the low potential side of the scanning signal line driving circuit. It is preferable that both the voltage levels are shifted, and the data signal line drive circuit includes a level shift circuit that shifts one of the voltage levels on the high potential side or the low potential side of the data signal line drive circuit.

According to the above configuration, usually, the data signal line driving circuit for outputting image data to the data signal line is a CMO
In contrast to the S configuration, the switching element provided for each pixel and for writing image data has an NMOS configuration, and the driving signal level of the scanning signal line driving circuit is equal to the driving signal level of the data signal line driving circuit. A voltage amplitude larger than the level is required. That is, the voltage level on the high potential side of the scanning signal line driving circuit is higher than the voltage level on the high potential side of the data signal line driving circuit, and the voltage level on the low potential side of the scanning signal line driving circuit is set to the data signal line driving circuit. It is required to be lower than the voltage level on the low potential side of the circuit.

In this case, using the other voltage level not shifted in the data signal line driving circuit as a reference is more effective than using either one of the scanning signal line driving circuits as a reference. The amount can be reduced, and the load on the circuit can be reduced.

Further, in the matrix type image display device according to the present invention, each of the pixels includes a switching element and a pixel capacitance including a liquid crystal capacitance and an auxiliary capacitance.
When the pixel is selected by the scanning signal, the switching element takes in the image data and supplies the image data to one of the electrodes of the liquid crystal capacitor and the auxiliary capacitor, whereby the one electrode of the liquid crystal capacitor and the counter electrode which is the other electrode are provided. A voltage is applied to the display medium interposed between the storage capacitor and the display medium, and the display medium is driven to realize image display, the other electrode of the auxiliary capacitance is connected to an adjacent scanning signal line, and the counter electrode is It is preferable that the voltage level is AC-driven at a predetermined cycle, and the scanning signal line drive circuit includes the two-stage level shift circuit, and the voltage shift amount of any one of the level shift circuits changes every cycle. .

According to the above configuration, a so-called CS-on-gate pixel configuration is used in which the other electrode of the auxiliary capacitance forming the pixel capacitance is connected to the adjacent scanning signal line. One of the driving voltage levels of the scanning signal line driving circuit is changed in the driving cycle.

Therefore, in the above-mentioned CS on-gate structure, the off-voltage level of the scanning signal line needs to be changed with the same amplitude in synchronization with the AC drive of the common electrode such as the liquid crystal capacitor. By changing the one voltage level, which is the off level, the level of the scanning signal line can be driven as a desired waveform.

Further, in the matrix type image display device according to the present invention, in the signal line driving circuit including the above-mentioned level shift circuit, the transistor constituting the level shift circuit provided in the output stage is a circuit of the preceding stage. It is preferable that the transistor and the element structure are different from each other and have a high breakdown voltage.

According to the above configuration, the element structure of the transistor constituting the level shift circuit and the transistor constituting the preceding circuit are changed in accordance with the withstand voltage required for the element. For example, an offset structure is adopted. When responding by changing the channel length,
In a transistor of a level shift circuit that requires a high withstand voltage, the channel length is increased. In this case, it is preferable that the channel length of this transistor is 1.5 to 3 times the channel length of the transistor constituting the circuit on the preceding stage.

When the thickness of the gate insulating film is used, the thickness of the transistor of the level shift circuit is increased. In this case, the thickness of the gate insulating film of this transistor is preferably 1.25 to 2.5 times the film thickness of the gate insulating film of the transistor constituting the preceding circuit.

A transistor constituting a level shift circuit requiring a high withstand voltage may have a so-called LDD structure having a region with a low impurity concentration between a channel region, a source region, and a drain region. In this case, in a region where the impurity concentration of the transistor is low, the impurity doping amount per area is 1 × 10 ¹² to 1 × 10 ^12.
It is preferably × 10 ¹⁴ / cm ² .

As described above, if the breakdown voltage of the level shift circuit is increased, high reliability can be obtained for both the level shift circuit and the circuit on the subsequent stage.

Further, in the matrix type image display device according to the present invention, the transistor forming at least one of the scanning signal line driving circuit and the data signal line driving circuit is a polycrystalline transistor together with the transistor forming the pixel. It is preferable to be formed monolithically with a silicon thin film.

According to the above configuration, at least one of the scanning signal line driving circuit and the data signal line driving circuit is formed integrally on the insulating substrate on which the pixels are formed.

Therefore, the pixel and the driving circuit can be formed by the same process, and the manufacturing cost can be reduced.

[0115]

According to the matrix type image display device of the present invention, the area divided by the scanning signal line and the data signal line
A substrate in which pixels having switching elements are arranged in a matrix, a scanning signal line driving circuit for driving the scanning signal lines, and a data signal line driving circuit for driving the data signal lines , Further comprising first and second level shift circuits for shifting a voltage level of a signal line to be driven, wherein the first and second level shift circuits are each provided with a scanning signal line driving circuit. Alternatively, a voltage level provided in at least one of the data signal line driving circuits and shifted by one level shift circuit is further shifted by the other level shift circuit.

In the matrix type image display device according to the present invention, in the matrix type image display device described above, further, the first level shift circuit shifts a voltage level on a high potential side of a signal line to be driven, and It is preferable that the two-level shift circuit shifts the voltage level on the low potential side of the signal line to be driven.

In the matrix type image display device according to the present invention, in the matrix type image display device described above, the voltage level shifted by the first level shift circuit is further shifted by the second level shift circuit. Preferably.

A matrix type image display device according to the present invention comprises a substrate on which pixels for displaying an image are arranged in a matrix, and a scanning signal line driving circuit for selectively supplying image data to each of the pixels. And a data signal line driving circuit, at least one of the scanning signal line driving circuit and the data signal line driving circuit is provided at an output stage to the scanning signal line or the data signal line. There is provided a two-stage level shift circuit, wherein the voltage level shifted by one level shift circuit is further shifted by the other level shift circuit.

In the matrix type image display device according to the present invention, in the matrix type image display device described above, the two-stage level shift circuit further comprises a first level shift circuit for shifting the voltage level on the high potential side, And a second level shift circuit for shifting the voltage level on the low potential side.

The matrix type image display device according to the present invention is the same as the above matrix type image display device, wherein the voltage level shifted by the first level shift circuit is further changed by the second level shift circuit. Preferably, it is shifted.

According to the above configuration, even if an input signal having a low voltage, for example, an amplitude of 5 V from an external circuit such as a control circuit or an image signal processing circuit is directly input to each signal line driving circuit, the signal is not affected. The line drive circuit is provided in the output stage.
The level shift circuit of the stage can shift the voltage level of the output signal to the optimum level on both the low potential side and the high potential side.

Therefore, the load on the external circuit can be reduced, the configuration can be simplified and the power consumption can be reduced, and an optimum drive signal level suitable for the drive circuit configuration and the display medium can be obtained. Display quality can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of a scanning signal line driving circuit according to an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining an operation of the scanning signal line driving circuit shown in FIG.

FIG. 3 is a block diagram showing an electrical configuration of a data signal line driving circuit according to one embodiment of the present invention.

4 is an electric circuit diagram showing a specific configuration of a level shifter in the scanning signal line driving circuit shown in FIG.

FIG. 5 is a cross-sectional view schematically showing an element structure for realizing the level shifter as shown in FIG.

6 is an electric circuit diagram showing one configuration example of a scanning circuit in the scanning signal line driving circuit shown in FIG. 1 and the data signal line driving circuit shown in FIG.

FIG. 7 is an electric circuit diagram schematically showing an electric configuration of a pixel in the liquid crystal display device according to the embodiment of the present invention.

FIG. 8 is a front view illustrating a schematic configuration of a liquid crystal display device according to another embodiment of the present invention.

9 is an electric circuit diagram schematically showing an electric configuration of a pixel in the liquid crystal display device shown in FIG.

FIG. 10 is a waveform chart for explaining the operation of the scanning signal line driving circuit in the liquid crystal display device shown in FIG.

FIG. 11 is a front view showing a schematic configuration of a general liquid crystal display device.

FIG. 12 is a block diagram showing an electrical configuration of a data signal line driving circuit in a typical prior art liquid crystal display device.

FIG. 13 is a block diagram showing an electrical configuration of a scanning signal line driving circuit in a typical conventional liquid crystal display device.

[Explanation of symbols]

Reference Signs List 1 liquid crystal display device (matrix type image display device) 2 control circuit 11 liquid crystal display device (matrix type image display device) 12 substrate 13 power supply voltage generating circuit ARY pixel array BUF _j buffer CL liquid crystal capacitance CS auxiliary capacitance GD scanning signal line driving circuit GL _j scanning signal line LS1 _j level shifters (level shift circuit) LS2 _j level shifters (level shift circuit) LS3 _i shifter (level shift circuit) SD data signal line drive circuit SL _i data signal lines SMP _i sampling circuit SRG _j scanning circuit SRS _i Scan circuit SW Field effect transistor

Claims (6)

[Claims] 1. A substrate in which pixels having switching elements are arranged in a matrix in an area divided by a scanning signal line and a data signal line, and a scanning signal line drive for driving the scanning signal line In a matrix type image display device including a circuit and a data signal line driving circuit for driving the data signal line, a first and a second level shift circuit for shifting a voltage level of a signal line to be driven are provided. The first and second level shift circuits are provided in at least one of the scan signal line drive circuit and the data signal line drive circuit, and the voltage level shifted by one of the level shift circuits is further reduced by the other. A matrix-type image display device, wherein a shift is performed in a level shift circuit. 2. The first level shift circuit shifts a voltage level on a high potential side of a signal line to be driven, and the second level shift circuit shifts a voltage level on a low potential side of a signal line to be driven. The matrix-type image display device according to claim 1, wherein: 3. The matrix type image display device according to claim 2, wherein the voltage level shifted by said first level shift circuit is further shifted by said second level shift circuit. 4. A semiconductor device comprising: a substrate on which pixels for displaying an image are arranged in a matrix; and a scanning signal line driving circuit and a data signal line driving circuit for selectively supplying image data to each of the pixels. Wherein at least one of the scanning signal line driving circuit or the data signal line driving circuit includes a two-stage level shift circuit at an output stage to the scanning signal line or the data signal line; A matrix type image display device, wherein a voltage level shifted by one level shift circuit is further shifted by another level shift circuit. 5. The matrix type image display device according to claim 4, wherein said two-stage level shift circuit comprises: a first level shift circuit for shifting a voltage level on a high potential side; and a voltage level on a low potential side. A matrix type image display device, which is a second level shift circuit that shifts a pixel. 6. The matrix type image display device according to claim 5, wherein the voltage level shifted by said first level shift circuit is further shifted by said second level shift circuit. Matrix type image display device.