JP2001196941A - Interleaver and interleaving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To continuously conduct interleave processing at a prescribed speed by using an interleave pattern that is generated at an optional generating speed and an optional size. SOLUTION: An interleave pattern generating section 102 generates an interleave pattern on the basis of a size calculated by a size calculation section 111. An address selection section 112 selects only a valid address among addresses of the interleave pattern and stores the selected address to an address storage section 103. A data processing discrimination section 113 calculates a parallel processing value resulting from dividing a product between a data size and an interleave generating speed by a data processing speed, and informs a data control section 114 about processing start information when number of addresses stored in the address storage section 103 is a value resulting from subtracting the parallel processing value from the size of the generated interleave pattern or over. The data control section 114 receiving the information uses the address stored in the address storage section 103 to conduct interleave processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an interleave device and an interleave method used in a signal processing device such as a turbo encoding / decoding device.

[0002]

2. Description of the Related Art In radio communication, interleave communication using a bit interleave system is proposed in order to reduce the deterioration of the error correction capability of a signal due to the occurrence of a burst error in which an error occurs locally locally in the signal. Have been.

Hereinafter, a conventional interleaving apparatus will be described with reference to FIG. FIG. 5 is a block diagram showing a configuration of a conventional interleave device.

[0005] In FIG. 5, a control unit 11 determines the size of an interleave pattern by an interleave pattern generation unit 12.
Output to Further, the control unit 11 writes data input from the outside into the data storage unit 13, and after the data writing is completed, reads the data from the data storage unit 13 and outputs the data to the outside. Interleave pattern generator 12
Generates an interleave pattern based on the size information and outputs the interleaved pattern to the control unit 11. The data storage unit 13 stores data and outputs the data to the control unit 11 according to a request.

Next, the operation procedure of the interleave device shown in FIG. 5 will be described. First, based on data size information input from the outside, the control unit 11 determines the size of the interleave pattern to be generated by the interleave pattern generation unit 1.
Output to 2. The interleave pattern generation unit 12 generates an interleave pattern based on the interleave pattern size, and outputs the generated interleave pattern to the control unit 11. Control unit 11
Writes data input from the outside into a predetermined address position of the data storage unit 13 using the interleave pattern as an address. Then, after the data writing process is completely completed, the control unit 11 reads from the data storage unit 13
Data is read out in a predetermined order and output to the outside.

Next, regarding the above-described signal rearranging (interleaving) operation, the order of seven data is changed to (D1, D
2, D3, D4, D5, D6, D7) to (D5, D
2, D6, D3, D4, D1, D7).

FIG. 6A is a diagram showing a data flow in the interleaving operation. Data input to the interleaver (D1, D2, D3, D4, D5, D6,
D7) is an address (A1, A2, A3, A4, A5)
A6, A7) are written in the data storage unit 13 in a sequence. Then, when reading data from the data storage unit 13, the control unit 11 uses an interleave pattern as an address. In this case, the addresses based on the interleave pattern (A5, A2, A6, A3, A4, A1, A
Data is sequentially read from the storage unit in the order of 7). As a result, the data is (D5, D2, D6, D3, D4, D
1, D7).

FIG. 6B shows a data flow in another interleaving operation. The data (D1, D2, D3, D4, D5, D
6, D7) are written in the data storage unit 13 in a sequence of addresses (A6, A2, A4, A5, A1, A3, A7) based on the interleave pattern. Then, the control unit 11 stores the addresses (A1, A2, A3, A4, A5, A
The data is read from the data storage unit 13 in the order of (6, A7). As a result, the data becomes (D5, D2, D6, D
3, D4, D1, D7).

The interleave pattern used in the above two methods is used as an address when writing data to the data storage unit 13 or when reading data from the data storage unit 13, so that the interleave pattern may have the same size as the data. In this case, if the generation speed of the interleave pattern is the same as the data processing speed, the interleave processing can be performed continuously at a constant speed.

[0010] However, the interleave pattern may be limited to a specific size depending on the generation method.
In this case, the interleave pattern is generated with a size equal to or larger than the size of the data. For example, an interleaver using prime numbers (Akira Shibuya, Hiroto Suda, "Turbo code interleaver for W-CDMA using prime numbers," B-
5-78, IEICE Communications Society Conference, 1999)
Is the prime number 67-2 when the data size is 1280 bits.
An interleave pattern having a size of 1340 bits which is 0 times is generated. In this case, among the addresses of the generated interleave pattern, an address larger than the data size is invalidated, and an address equal to or smaller than the data size is used for the interleave processing.

[0011]

However, the conventional interleaving apparatus has a problem that when an invalid address is generated,
There is a problem that the operation of writing or reading data to the storage unit must be stopped until a valid address is generated.

If the generation speed of the interleave pattern is lower than the data processing speed, the operation of writing or reading data after one of the addresses is generated and processed, and then until the next address is generated. There is also a problem that must be stopped.

The present invention has been made in view of such a point, and it is possible to continuously perform an interleave process at a constant speed using an interleave pattern generated at an arbitrary generation speed and an arbitrary size. An object of the present invention is to provide an interleaving apparatus and an interleaving method.

[0014]

According to the present invention, there is provided an interleaving apparatus, comprising: generating means for generating an interleave pattern; address storage means for storing an address corresponding to the generated interleave pattern; and data storage means for storing data. A data processing speed, a data size, an interleave pattern generation speed, and a determination unit that determines whether or not data processing can be started based on the number of addresses stored in the address storage unit. When it is determined that the data processing can be started by the data storage means, control means for controlling storage and retrieval of data to and from the data storage means based on the address of the address storage means is adopted.

In the interleave device of the present invention, the control means stores the data in the data storage means in the order of the addresses stored in the address storage means, and after storing the data in a predetermined unit, the control means stores A configuration is adopted in which data is taken out sequentially from the address.

In the interleave device of the present invention, the control means stores the data in the data storage means in order from the head address, stores the data in a predetermined unit, and then stores the data in the order of the addresses stored in the address storage means. A configuration for taking out data from the data storage means is adopted.

According to these configurations, the interleave pattern and the data can be continuously transmitted at the same timing, so that the interleave processing can be continuously performed at a constant speed.

In the interleaving apparatus according to the present invention, the judging means determines that the number of addresses stored in the address storage means is a value obtained by dividing a value obtained by subtracting the interleave pattern generation speed from the data processing speed by the data processing speed. A configuration is adopted in which it is determined that data processing can be started when the value is equal to or larger than the value obtained by multiplying the data size.

According to this configuration, even when the data processing speed and the interleave pattern generation speed are different, the more time-consuming processing of the data processing and the interleave generation processing is performed by the difference between the two processings. And the two processes can be performed in parallel, so that the interleaving process can be performed in the minimum necessary time.

The interleave device of the present invention comprises a selection means for selecting an address used for data processing from an interleave pattern, the address storage means stores the address selected by the selection means, and the determination means A configuration for determining whether data processing can be started based on the size of the interleave pattern in addition to the data processing speed, the data size, the interleave pattern generation speed, and the number of addresses stored in the address storage means. Take.

The interleave device of the present invention employs a configuration in which the selection means selects an address smaller than the data size from the generated interleave patterns and outputs the selected address to the address storage means.

According to these configurations, a necessary address can be selected from the interleave pattern by comparing the size of the data to be processed with the size of the interleave pattern that can be generated. Interleave processing can be performed continuously at a constant speed even when the size is different

The interleave device of the present invention comprises a calculating means for calculating the smallest size that is the same or larger than the data size among the interleaving patterns that can be generated. A configuration for generating an interleave pattern of the calculated size is adopted.

According to this configuration, it is possible to generate an interleave pattern of a required minimum size, so that it is possible to shorten the time for performing the interleave processing.

In the interleave device of the present invention, the judging means calculates a parallel processing value by dividing a value obtained by multiplying the data size by the interleave pattern generation speed of the generating means by a data processing speed, and stores the parallel processing value in the address storage means. When the number of addresses is equal to or greater than the value obtained by subtracting the parallel processing value from the size of the generated interleave pattern, it is determined that data processing can be started.

According to this configuration, even when the size of the interleave pattern is different from the size of the data, of the data processing and the interleave creation processing, the more time-consuming processing is replaced by the time difference between the two processings. By executing the processing first, the two processings can be performed in parallel, so that the interleaving processing can be performed in a minimum necessary time.

In the interleave device of the present invention, when the size of the interleave pattern to be generated is equal to the size of the immediately preceding interleave pattern, the generation unit notifies this information to the judgment unit. A configuration is adopted in which it is determined that data processing can be started, and the start of data processing is notified to the control means.

According to this configuration, when interleaving a plurality of data, one interleave pattern is reused, so that it is not necessary to perform a process of creating an interleave pattern in the second and subsequent interleave processes. Since the time for minutes is shortened, the time for performing the interleave processing can be shortened.

The interleave device of the present invention employs a configuration in which the address storage means performs data first-in first-out processing.

According to this configuration, an interleave pattern generated at a non-constant speed or an interleave pattern generated at a speed different from the data processing speed is output at a constant speed through the storage means. You can do it.

The signal processing device of the present invention employs a configuration having any one of the above-mentioned interleaving devices.

According to this configuration, the signal processing device continuously processes data at a constant speed in the interleave device, thereby eliminating the need for complicated control such as temporary suspension of signal processing, and reducing the circuit scale for that. A signal processing device that can be reduced can be realized.

A communication terminal device according to the present invention employs a configuration having the signal processing device.

According to this configuration, the communication terminal device does not need complicated control such as temporary suspension of signal processing in the signal processing device, and reduces the circuit scale by that amount.
A smaller communication terminal device having a smaller circuit scale can be realized.

The base station apparatus according to the present invention employs a configuration having the signal processing device.

[0036] According to this configuration, the base station apparatus does not need complicated control such as temporary suspension of signal processing in the signal processing apparatus, and reduces the circuit scale by that amount. A small base station device can be realized.

According to the interleave method of the present invention, an interleave pattern is generated in advance, the address of the interleave pattern is stored, and a value obtained by subtracting the interleave pattern generation speed from the data processing speed is divided by the data processing speed. A start condition value multiplied by a data size is calculated, and when the number of the stored addresses is equal to or greater than the start condition value, the addresses are continuously output at a constant speed in accordance with the speed of the interleave processing, The interleave processing is performed continuously at a constant speed.

According to the interleave method of the present invention, an interleave pattern is generated in advance, an address used for data processing is selected and stored from the interleave pattern, and a value obtained by multiplying the data size by the interleave generation speed is used as a data processing speed. At the time when the number of the stored addresses is equal to or greater than the value obtained by subtracting the parallel processing value from the size of the interleave pattern, the address of the interleave pattern is calculated according to the speed of the interleave processing. Are continuously output at a constant speed, and the interleave processing is continuously performed at a constant speed.

According to these methods, the interleave pattern and the data can be continuously transmitted at the same timing, so that the interleave processing can be continuously performed at a constant speed.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The gist of the present invention is that an effective address is selected and stored from an interleave pattern generated at an arbitrary timing, and is continuously output at a constant speed and used for data processing. It is to interleave continuously at a speed. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment) FIG. 1 is a block diagram showing a configuration of an interleaver according to an embodiment of the present invention. In FIG. 1, control section 101 calculates the size of the interleave pattern based on the size of the input data, and outputs the calculated size to interleave pattern generation section 102. Further, control section 101 selects an effective address based on the interleave pattern generated by interleave pattern generation section 102 and outputs it to address storage section 103. Further, the control unit 101 controls the address storage unit 10
Based on the effective address obtained from Step 3, the input data is written to the data storage unit 104. After the writing is completed, the data is sequentially extracted from the top address and output to the outside.

[0042] Interleave pattern generation section 102 generates an interleave pattern based on the interleave pattern size, and outputs it to control section 101. The method of generating the interleave pattern is described in the document “W using prime numbers.
-Turbo code interleaver for CDMA, "Akira Shibuya,
Hiroto Suda, B-5-78, IEICE Communication Society Conference, 1999 ". Address storage unit 10
Reference numeral 3 sequentially stores the effective addresses, and outputs the effective addresses to the control unit 101 at a constant speed in ascending order. The data storage unit 104 stores data, and the control unit 101
Output to

Next, the internal configuration of the control unit 101 will be described.

The control unit 101 includes a size calculation unit 111,
An address selection unit 112, a data processing determination unit 113,
And a data control unit 114.

The size calculation unit 111 selects a size of the interleave pattern that can be generated, which is equal to or larger than the data size. Then, the size calculation unit 1
11 selects the smallest one of the selected sizes, and outputs information indicating the selected size to the interleave pattern generation unit 102.

The address selection unit 112 selects an interleave pattern having a data size larger than the data size input from the outside as an invalid address, and selects the same or smaller one as a valid address, and outputs the selected address to the address storage unit 103. Further, the address selection unit 112 outputs the number of output valid addresses to the data processing determination unit 113.

The data processing determination unit 113 determines the data size based on the data size, the interleave pattern size, the number of output effective addresses, the interleave pattern generation speed of the interleave pattern generation unit 102, and the data processing speed of the data storage unit 104. Determine whether the sorting process can be started. Then, the data processing determining unit 1
13 determines that the data rearrangement process can be started, and outputs a process start signal to the data control unit 114.
The detailed operation of the data processing determination unit 113 will be described later.

When the data control unit 114 receives the processing start signal, it writes the externally input data to the address of the data storage unit 104 corresponding to the address output from the address storage unit 103. Then, after the data writing is completed, the data control unit 114 reads the data from the head address of the data storage unit 104 and outputs the data to the outside.

Next, the detailed operation of the data processing judgment section 113 will be described. In the interleave device, the generation speed of the interleave pattern is V _ilp (bit / s), the data processing speed is V _data (bit / s), the interleave pattern size is L _ilp (bit), the data size is L _data (bit), and the address. It is assumed that the number of addresses stored in the storage unit 104 is N _add .

The time required to generate all the interleave patterns is _Lilp / _Vilp (s). Also, the time required to process all data is L _data / V
_data (s).

Here, in order to generate all the interleave patterns before all the data are processed, the time L required to generate all the interleave patterns is obtained.
_ilp / V _ilp and (s), the difference between the time required to process all data _{L data / V data (s)} L ilp / V ilp -L data /
What is necessary is just to start generating an interleave pattern before V _data (s). Then, the number of interleave pattern generated in this _{time, V il p × (L ilp} / V ilp -L data / V
_data ).

That is, if the address storage unit 103 starts the process after storing an integer N _add addresses satisfying the following equation (1), the interleave is continuously performed at a constant speed in a minimum necessary time. Processing can be performed.

[0053]

(Equation 1)

When an interleave pattern having the same size as the data size can be generated, the following equation (2) holds.

(Equation 2)

The following equation (3) is derived from the equation (1) using the equation (2).

(Equation 3)

That is, if an interleave pattern of the same size as the data can be generated, the address storage unit 1
If the process is started after 03 stores the integer N _add addresses satisfying the expression (3), the interleave process can be continuously performed at a constant speed in a minimum necessary time.

Next, the operation procedure of the interleave apparatus of FIG. 1 will be described. First, information on the data size input from the outside is input to the size calculation unit 111. Size calculating section 111 calculates the size of the interleaved pattern that can be generated based on the data size, and outputs the size to interleaved pattern generating section 102.

The interleave pattern generator 102 starts generating an interleave pattern based on the information on the data size. The generated interleave pattern is output to address selection section 112.

The address selection unit 112 outputs an interleave pattern having the same or smaller data size as an effective address to the address storage unit 103 based on information on the data size input from the outside. In addition, the address selection unit 112 outputs the number of valid addresses output to the address storage unit 103 to the data processing determination unit 113.

Address storage section 103 stores the input effective address and outputs the effective address to data control section 114 continuously at a constant speed in response to a request from data control section 114.

The data processing determination unit 113 determines conditions for starting the above-described data processing based on the data size, the interleave pattern size, the interleave pattern generation speed of the interleave pattern generation unit 102, and the data processing speed of the data storage unit 104. derive. Then, when the number of valid addresses satisfies this condition, data processing determination section 113 outputs a data processing start signal to data control section 114.

When the data control section 114 receives the data processing start signal, it starts the data processing. Specifically, the data control unit 114 writes externally input data to the data storage unit 104 based on the address input from the address storage unit 103. After the data control unit 114 finishes writing data in the data storage unit 104, the data control unit 114 sequentially reads the data from the head address and outputs the data to the outside. Thereby, the rearrangement of data is realized.

As described above, according to the present invention, an interleave pattern is generated in advance and stored as an effective address in the address storage unit 103, and the necessary number of addresses for continuous processing at a constant speed are stored in the address storage unit 103. After that, by starting data processing, interleave processing can be performed continuously at a constant speed.

Next, a specific example of an operation of selecting an effective address from the interleave pattern and a data write operation will be described with reference to FIGS. 2, 3, and 4. FIGS. 2, 3 and 4 show seven data (D1, D2, D
3, D4, D5, D6, D7) into an interleave pattern (A6, A2, A4, A5,
A1, A8, A3, A7) will be described.

The numbers attached to the data indicate the input order, and the numbers attached to the addresses correspond to the address storage unit 1.
03 shows an address at which data is written. Since seven addresses are necessary to rearrange seven data,
A8 indicating the largest address among the eight generated addresses is an invalid address. In this case, since the data size is 7 and the interleave pattern size is 8,
When the data processing speed and the interleave pattern generation speed are the same, the address storage unit 103 stores 1
If the data processing is started when the addresses are stored, the interleave processing can be performed continuously at a constant speed.

FIG. 2 shows the operations of the first, second, and third steps. First, the operation of the first step will be described. Address A6 is output from interleave pattern generation section 102 to address selection section 112.
A6 has a data size of 7 or less, and the address selection unit 1
At 12, the address is determined to be a valid address, and is stored in the address storage unit 103. Here, the address storage unit 103
Since the number of addresses stored in the memory cell has become 1 and the condition for starting the data processing has been satisfied, the data processing is started from the next step.

Next, the operation of the second step will be described. Address A2 is output from interleave pattern generation section 102 to address selection section 112. A2 has a data size of 7 or less, is determined to be a valid address by the address selection unit 112, and is stored in the address storage unit 103. The address A6 stored in the address storage unit 103 in the first step is output to the data control unit 114, and the data D1 input to the data control unit 114 is stored in the address A6 of the data storage unit 104.

Next, the operation of the third step will be described. Address A4 is output from interleave pattern generation section 102 to address selection section 112. A4 has a data size of 7 or less, is determined to be a valid address by the address selection unit 112, and is stored in the address storage unit 103. The address A2 stored in the address storage unit 103 in the second step is output to the data control unit 114, and the data D2 input to the data control unit 114 is stored in the address A2 of the data storage unit 104.

FIG. 3 shows the operations of the fourth, fifth and sixth steps. First, the operation of the fourth step will be described. Address A5 is output from interleave pattern generation section 102 to address selection section 112. A
Reference numeral 5 denotes a data size of 7 or less, and the address selection unit 11
2 is determined to be a valid address, and is stored in the address storage unit 103. The address A4 stored in the address storage unit 103 in the third step is the data control unit 11
The data D3 output to the data control unit 114 and input to the data control unit 114 is stored at the address A4 of the data storage unit 104.

Next, the operation of the fifth step will be described. Address A1 is output from interleave pattern generation section 102 to address selection section 112. A1 has a data size of 7 or less, is determined by the address selection unit 112 to be a valid address, and is stored in the address storage unit 103. The address A5 stored in the address storage unit 103 in the fourth step is output to the data control unit 114, and the data D4 input to the data control unit 114 is stored in the address A5 of the data storage unit 104.

Next, the operation of the sixth step will be described. Address A8 is output from interleave pattern generation section 102 to address selection section 112. Since A8 is larger than the data size 7, A8 is determined as an invalid address by the address selection unit 112 and is not stored in the address storage unit 103. The address A1 stored in the address storage unit 103 in the fifth step is output to the data control unit 114, and the data D5 input to the data control unit 114 is stored in the address A1 of the data storage unit 104.

FIG. 4 shows the operations of the seventh and eighth steps. First, the operation of the seventh step will be described. Address A3 is output from interleave pattern generation section 102 to address selection section 112. A3 has a data size of 7 or less, is determined to be a valid address by the address selection unit 112, and is stored in the address storage unit 103. Since there is no stored address, address storage section 103 outputs A3 to data control section 114, and data D6 input to data control section 114 is stored at address A3 of storage section 103.

Finally, the operation of the eighth step will be described.
Address A7 is output from interleave pattern generation section 102 to address selection section 112. A7 has a data size of 7 or less, is determined by the address selection unit 112 to be a valid address, and is stored in the address storage unit 103. Since there is no stored address, address storage section 103 outputs A7 to data control section 114, and data D7 input to data control section 114 stores data D7 in storage section 103.
At address A7.

After all the seven data are stored in the storage unit, the data control unit 114 sets the address (A1, A2, A
3, A4, A5, A6, A7), the data is read from the storage unit and output to the outside. As a result, the data
(D5, D2, D6, D3, D4, D1, D7).

As described above, it can be seen that the provision of the address storage unit 103 for storing addresses enables continuous interleave processing at a constant speed.

In the present embodiment, the case where one data process is performed using one generated interleave pattern is described. However, the present invention is not limited to this, and one generated interleave pattern is used. Can be used repeatedly to interleave a plurality of data of the same size.

In this case, the interleave pattern generation unit 1
No. 02 notifies the data processing determination unit 113 of this information when the size of the interleave pattern to be generated is equal to the size of the immediately preceding interleave pattern. Upon receiving the notification, the data processing determination unit 113 determines that the data processing can be started, and instructs the data control unit 11 to start the data processing.
Notify 4. Then, the data control unit 114 receiving the notification of the start of the data processing starts the data processing.

As described above, according to the present embodiment, when interleaving a plurality of data, one interleave pattern is reused, so that the interleave pattern is created in the second and subsequent interleave processes. This eliminates the necessity, and the time required for the interleaving process can be shortened.

In this embodiment, the data storage unit 1
When data is written in the data storage unit 104, the interleave pattern is used as an address.
Alternatively, an interleave pattern may be used for an address when data is read from the memory.

The address storage unit 10 according to the present embodiment
Reference numeral 3 denotes a FIFO (Fas
(t in fast out) section. Accordingly, an interleave pattern generated at a non-constant speed or an interleave pattern generated at a speed different from the data processing speed is output at a constant speed through the address storage unit 103, so that the interleave process is continuously performed at a constant speed. Can be.

The interleave device described in the present embodiment can be incorporated in a signal processing device such as a turbo encoding / decoding device. Furthermore, this signal processing device
It can be incorporated in an error correction unit of a communication terminal device and a base station device that perform wireless communication. This eliminates the need for complicated control such as temporary suspension of signal processing, so that the circuit scale can be reduced accordingly, and a small-sized device with a small circuit scale can be realized.

[0082]

As described above, according to the present invention,
By using an interleave pattern generated at an arbitrary generation speed and an arbitrary size, interleave processing can be continuously performed at a constant speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an interleave device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a data flow for explaining an operation of the interleaving apparatus according to the embodiment.

FIG. 3 is a diagram showing a data flow for explaining an operation of the interleaving apparatus according to the embodiment.

FIG. 4 is a diagram showing a data flow for explaining an operation of the interleaving apparatus according to the embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional interleave device.

FIG. 6 is a diagram showing data processing for explaining a conventional interleaving operation;

[Explanation of symbols]

 Reference Signs List 101 control unit 102 interleave pattern generation unit 103 address storage unit 104 data storage unit 111 size calculation unit 112 address selection unit 113 data processing determination unit 114 data control unit

Claims (15)

[Claims] 1. An interleave pattern generation unit, an address storage unit for storing an address corresponding to the generated interleave pattern, a data storage unit for storing data, a data processing speed, a data size, and an interleave. Determining means for determining whether or not data processing can be started based on a pattern generation speed and the number of addresses stored in the address storage means; and when the determining means determines that data processing can be started. ,
Control means for controlling storage and retrieval of data to and from the data storage means based on the address of the address storage means. 2. The control means stores data in the data storage means in the order of the addresses stored in the address storage means,
2. The interleave apparatus according to claim 1, wherein after storing a predetermined unit of data, the data is taken out from the data storage means in order from a head address. 3. The control means stores data in the data storage means in order from the start address, and after storing data in a predetermined unit, retrieves the data from the data storage means in the order of the addresses stored in the address storage means. The interleaving device according to claim 1, wherein: 4. The determination means multiplies the number of addresses stored in the address storage means by a value obtained by subtracting a value obtained by subtracting an interleave pattern generation speed from a data processing speed by a data processing speed by a data size. 4. The interleave device according to claim 1, wherein it is determined that data processing can be started when the value is equal to or more than the value. 5. An image processing apparatus comprising: selecting means for selecting an address to be used for data processing from an interleave pattern; address storing means storing the address selected by said selecting means; Determining whether data processing can be started based on the size of the interleave pattern in addition to the size of the data, the generation speed of the interleave pattern, and the number of addresses stored in the address storage means. The interleave device according to any one of claims 1 to 3. 6. The interleave apparatus according to claim 5, wherein the selection means selects an address smaller than the data size from the generated interleave patterns and outputs the selected address to the address storage means. 7. A calculating means for calculating a smallest size which is equal to or larger than the data size among interleaved patterns which can be generated, wherein the generating means calculates a size of the size calculated by the calculating means. The interleave device according to claim 5, wherein an interleave pattern is generated. 8. The judging means calculates a parallel processing value obtained by dividing a value obtained by multiplying the data size by an interleave pattern generation speed of the generating means by a data processing speed, and determines that the number of addresses stored in the address storage means is 8. The interleaving apparatus according to claim 5, wherein it is determined that data processing can be started when the value is equal to or greater than a value obtained by subtracting the parallel processing value from the size of the generated interleave pattern. 9. When the size of an interleave pattern to be generated is equal to the size of an immediately preceding interleave pattern, the generation unit notifies this information to the determination unit, and the determination unit can start data processing based on the information. 9. The interleave apparatus according to claim 5, wherein the control unit notifies the control unit of the start of data processing. 10. The interleave apparatus according to claim 1, wherein the address storage means performs first-in first-out processing of data. 11. A signal processing device comprising the interleaving device according to claim 1. Description: 12. A communication terminal device comprising the signal processing device according to claim 11. 13. A base station apparatus comprising the signal processing apparatus according to claim 11. 14. An interleave pattern is generated in advance, and an address of the interleave pattern is stored.
Calculate the start condition value by multiplying the value obtained by subtracting the interleave pattern generation speed from the data processing speed by the data processing speed by the data size, and store the number of the addresses, the number of the addresses being greater than or equal to the start condition value. An interleaving method, wherein the address is continuously output at a constant speed in accordance with the speed of the interleaving process, and the interleaving process is continuously performed at a constant speed. 15. A parallel processing in which an interleave pattern is generated in advance, an address used for data processing is selected from the interleave pattern and stored, and a value obtained by multiplying a data size by an interleave generation speed is divided by a data processing speed. At the time when the number of the stored addresses is equal to or greater than the value obtained by subtracting the parallel processing value from the size of the interleave pattern, the addresses of the interleave pattern are continuously transferred at a constant speed in accordance with the speed of the interleave processing. An interleaving method characterized in that interleaving processing is performed continuously at a constant speed.