JP2001196420A - Semiconductor device manufacturing method and device - Google Patents

Semiconductor device manufacturing method and device

Info

Publication number
JP2001196420A
JP2001196420A JP2000009949A JP2000009949A JP2001196420A JP 2001196420 A JP2001196420 A JP 2001196420A JP 2000009949 A JP2000009949 A JP 2000009949A JP 2000009949 A JP2000009949 A JP 2000009949A JP 2001196420 A JP2001196420 A JP 2001196420A
Authority
JP
Japan
Prior art keywords
semiconductor device
conductive adhesive
electrode terminal
electrode
plasma processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000009949A
Other languages
Japanese (ja)
Inventor
Masaaki Sato
正昭 佐藤
Junichi Saeki
準一 佐伯
Kenji Yoshimi
健二 吉見
Masakazu Sakagami
雅一 坂上
Yasuhiro Narukawa
泰弘 成川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000009949A priority Critical patent/JP2001196420A/en
Publication of JP2001196420A publication Critical patent/JP2001196420A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method and an equipment for a semiconductor device in which electrode terminals can be markedly lessened in connection resistance between them even if the conventional Al is used as electrode material when the electrode terminals of the semiconductor device are connected together with conductive adhesive agent. SOLUTION: A semiconductor chip 34 serving as a specimen is installed on a cathode electrode 35 in a plasma processing chamber 32. An oxide 39 on the surface of the electrode terminal 38 of the specimen 34 is removed by plasma 37 generated between the cathode electrode 35 and an anode electrode 36. The specimen is transferred into an application chamber 33 via an intermediate chamber 44 in which an inert gas is fed, and conductive adhesive agent paste 43 is applied on the surface of the electrode terminal 38 in an inert gas of an atmospheric pressure, being fed from a dispenser 42. The oxide 39 of the electrode terminal 38 is removed, then the conductive adhesive paste layer 43 can be formed on the surface of the electrode terminal 38 without coming into contact with oxygen contained in the air, so that a semiconductor device of small connection resistance can be manufactured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の電極端
子間接続に導電性接着剤を用いた半導体製造方法及び製
造装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method and apparatus using a conductive adhesive for connection between electrode terminals of a semiconductor device.

【0002】[0002]

【従来の技術】従来の導電性接着剤を用いた半導体装置
の電極端子間接続は、例えば特開平6−224259号
公報、特開平8−227913号公報にみられるよう
に、金もしくは金メッキ電極端子に直接導電性接着剤を
塗布し、硬化して電気的、機械的に接続している。この
導電性接着剤による端子間接続は、はんだ接続などに比
べ低温で接続でき、またフラックスを使わないため、洗
浄工程が不要となり、低コストの製造方法となると言っ
た利点があった。
2. Description of the Related Art A conventional connection between electrode terminals of a semiconductor device using a conductive adhesive is disclosed in, for example, JP-A-6-224259 and JP-A-8-227913. A conductive adhesive is applied directly to the resin and cured to make electrical and mechanical connections. The connection between the terminals using the conductive adhesive has an advantage that it can be connected at a lower temperature than a solder connection and does not use a flux, so that a cleaning step is not required and a low-cost manufacturing method can be obtained.

【0003】[0003]

【発明が解決しようとする課題】しかし、電極端子に用
いる金属の種類によって導電性接着剤で接続された端子
間の電気的抵抗値が大きくなり電気的な性能を満足でき
ないという問題がある。
However, there is a problem that the electrical resistance between the terminals connected by the conductive adhesive increases depending on the type of metal used for the electrode terminals, and the electrical performance cannot be satisfied.

【0004】特に銅やアルミニウムと云った通常の安価
な電極材料の場合に抵抗値が大きく、また、接続抵抗値
に大きなバラツキが生じ半導体装置の信頼性を著しく低
下させていた。
[0004] In particular, in the case of ordinary inexpensive electrode materials such as copper and aluminum, the resistance value is large, and the connection resistance value is greatly varied, thereby significantly reducing the reliability of the semiconductor device.

【0005】半導体素子が高密度化されるにしたがいこ
の抵抗値の増大とバラツキは実用化を阻む決定的な問題
である。そのため、従来は電極端子金属に金もしくは金
メッキを用い導電性接着剤で接続する方法が行われてい
る。これにより、電極端子接続部の抵抗値の増大はなく
なるが、半導体装置が高価になるという課題が残る。
[0005] As the density of the semiconductor elements increases, the increase and the variation in the resistance value are decisive problems that hinder practical use. For this reason, conventionally, a method of connecting with a conductive adhesive using gold or gold plating for the electrode terminal metal has been used. This eliminates an increase in the resistance value of the electrode terminal connection portion, but leaves a problem that the semiconductor device becomes expensive.

【0006】したがって、本発明の目的は、上記従来の
問題点を解消することにあり、金以外の例えば銅やアル
ミニウム等の在来の安価な金属をも電極材料として使用
可能な、導電性接着剤を用いる半導体装置の製造方法及
び製造装置を提供することにある。これにより、電極端
子接続間の抵抗値特性を向上させた低コストの半導体装
置を容易に得ることができる。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned conventional problems, and it is possible to use a conventional inexpensive metal other than gold, such as copper or aluminum, as an electrode material. An object of the present invention is to provide a method and an apparatus for manufacturing a semiconductor device using an agent. Thus, a low-cost semiconductor device with improved resistance value characteristics between electrode terminal connections can be easily obtained.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に本発明者等は、導電性接着剤を用いて銅やアルミニウ
ム等の在来の安価な金属を電極端子とした場合の接続抵
抗値について種々実験検討した。
Means for Solving the Problems To achieve the above object, the present inventors have determined the connection resistance when a conventional inexpensive metal such as copper or aluminum is used as an electrode terminal by using a conductive adhesive. About various experiments.

【0008】その結果、導電性接着剤で接続された電極
端子間の電気的抵抗値が大きくなる原因としては、導電
性接着剤の硬化物の体積抵抗率が大きいことと電極端子
表面に汚れ及び表面酸化物が存在することにあると云う
ことがわかった。
As a result, the electrical resistance between the electrode terminals connected by the conductive adhesive is increased because the volume resistivity of the cured product of the conductive adhesive is large, and the surface of the electrode terminal is contaminated and stained. It was found that the presence of surface oxides was due.

【0009】その中でも特に電極端子表面に形成された
酸化物が最も大きな抵抗値増加を起こし、金属表面は大
気中では数秒間で表面酸化物を生成することが判明し
た。
Among them, it has been found that an oxide formed on the surface of the electrode terminal causes the largest increase in the resistance value, and that a metal surface forms a surface oxide within a few seconds in the air.

【0010】本発明はこれらの知見に基づいてなされた
ものであり、本発明の半導体装置の製造方法の特徴を以
下に述べる。
The present invention has been made based on these findings, and the features of the semiconductor device manufacturing method of the present invention will be described below.

【0011】製造方法上の特徴は、半導体装置の電極端
子に導電性接着剤を塗布する工程において、電極端子を
構成する金属の表面から酸化物を除去することにある。
酸化物の除去方法には、二つの方法があり、その一つは
例えばArやAr+H2,Xe等の希ガスもしくは窒素
ガスを用いたプラズマ処理方法であり、他の一つは機械
的に削り取る方法である。
A feature of the manufacturing method is that, in the step of applying a conductive adhesive to the electrode terminals of the semiconductor device, the oxide is removed from the surface of the metal constituting the electrode terminals.
There are two methods for removing oxides, one of which is a plasma treatment method using a rare gas such as Ar, Ar + H 2 , or Xe or a nitrogen gas, and the other is a mechanical treatment. Is the way.

【0012】プラズマ処理方法の場合には、イオンエッ
チングによって電極端子表面から酸化物を除去して金属
面を露出させることができる。この露出した金属表面に
導電性接着剤を塗布するに際しては、金属表面が再度酸
化されないように酸素を排除した非酸化性ガス雰囲気中
にて塗布することが重要となる。
In the case of the plasma processing method, the metal surface can be exposed by removing the oxide from the electrode terminal surface by ion etching. When applying the conductive adhesive to the exposed metal surface, it is important to apply the conductive adhesive in a non-oxidizing gas atmosphere excluding oxygen so that the metal surface is not oxidized again.

【0013】塗布する雰囲気のガス圧力は大気圧でよ
く、また、非酸化性ガス雰囲気としては、窒素、周期律
表ゼロ族元素(希ガス)等の不活性ガス、もしくは例え
ば水素等の還元ガス雰囲気中で行うことが望ましい。
The gas pressure of the coating atmosphere may be atmospheric pressure, and the non-oxidizing gas atmosphere may be an inert gas such as nitrogen or a zero-group element (rare gas) in the periodic table, or a reducing gas such as hydrogen. It is desirable to perform in an atmosphere.

【0014】また、電極端子表面から酸化物を機械的に
削り取る方法の場合には、予め電極端子表面に接続に必
要な分量の導電性接着剤を塗布しておき、この導電性接
着剤によって外気から電極端子表面を遮断した状態で、
鋭利な先端構造を有する金属、セラミックス等の治具を
電極端子表面に当てて機械的に削り取る。
In the case of the method of mechanically removing oxide from the electrode terminal surface, an amount of conductive adhesive necessary for connection is previously applied to the electrode terminal surface, and the conductive adhesive is used to open air. With the electrode terminal surface cut off from
A jig made of metal, ceramics, or the like having a sharp tip structure is applied to the electrode terminal surface to mechanically scrape it.

【0015】この方法の場合には、予め電極端子表面に
導電性接着剤を塗布した状態で酸化物を機械的に削り取
るので、酸化物の除去中及び除去後においても電極端子
表面は導電性接着剤で覆われているため再度酸化される
ことはない。したがって、塗布する雰囲気も大気中でよ
く、必ずしも非酸化性ガス雰囲気とする必要はない。
In this method, the oxide is mechanically scraped off with the conductive adhesive applied to the surface of the electrode terminal in advance, so that the surface of the electrode terminal remains conductive even during and after the removal of the oxide. It is not oxidized again because it is covered with the agent. Therefore, the application atmosphere may be the air, and it is not always necessary to use a non-oxidizing gas atmosphere.

【0016】要するに電極端子表面に導電性接着剤を塗
布する工程においては、プラズマ処理方法においては酸
化物を除去した後、もしくは機械的に削り取る方法にお
いては除去中に、電極端子表面を酸素に接触させずに導
電性接着剤を塗布することが重要である。
In short, in the step of applying the conductive adhesive to the surface of the electrode terminal, the surface of the electrode terminal is brought into contact with oxygen after removing the oxide in the plasma treatment method or during the removal in the method of mechanically scraping. It is important to apply the conductive adhesive without doing so.

【0017】本発明の製造方法においては、導電性接着
剤が塗布された電極端子を実装基板上の電極端子に位置
合わせし、両電極間に導電性接着剤層を形成して電気的
接続を行う工程においても特徴がある。一般にこの種の
導電性接着剤を用いた接続工程は、大気中で接着剤の樹
脂成分を熱硬化して行われているが、本発明では窒素ガ
スや希ガス等の不活性ガス雰囲気中で硬化することが望
ましい。
In the manufacturing method of the present invention, the electrode terminals coated with the conductive adhesive are aligned with the electrode terminals on the mounting substrate, and a conductive adhesive layer is formed between the two electrodes to establish electrical connection. There is also a characteristic in the process to be performed. Generally, the connection step using this kind of conductive adhesive is performed by thermally curing the resin component of the adhesive in the air, but in the present invention, the connection is performed in an inert gas atmosphere such as nitrogen gas or a rare gas. It is desirable to cure.

【0018】また、上記本発明の目的を達成することの
できる半導体装置の製造装置の特徴は、半導体装置の
電極端子表面を所定の減圧下でプラズマ処理するプラズ
マ発生手段とガス供給口と排気口とを有するプラズマ処
理室と、前記プラズマ処理室でプラズマ処理された半
導体装置を減圧された非酸化性ガス雰囲気中で中継する
中間室と、前記中間室を中継した半導体装置の電極端
子表面に、常圧下の非酸化性ガス雰囲気中で導電性接着
剤を塗布する手段を有する塗布室と、前記プラズマ処
理室から塗布室まで半導体装置を順次搬送する搬送手段
とを備えている点にある。
The semiconductor device manufacturing apparatus capable of achieving the above object of the present invention is characterized by plasma generating means for performing plasma processing on the electrode terminal surfaces of the semiconductor device under a predetermined reduced pressure, a gas supply port and an exhaust port. A plasma processing chamber having: a semiconductor device plasma-processed in the plasma processing chamber; an intermediate chamber that relays the semiconductor device in a reduced-pressure non-oxidizing gas atmosphere; and an electrode terminal surface of the semiconductor device that relays the intermediate chamber. It comprises a coating chamber having means for applying a conductive adhesive in a non-oxidizing gas atmosphere under normal pressure, and a transfer means for sequentially transferring semiconductor devices from the plasma processing chamber to the coating chamber.

【0019】[0019]

【発明の実施の形態】本発明が対象とする半導体装置と
しては、ICチップ,コンデンサーチップ、BGA(Ball Gri
d Array),実装基板などがあり、電極端子としてはチッ
プ、チップ搭載用基板(実装用配線基板)の電極、電極
に後から形成したはんだボールをも含む。また、電極端
子の金属としてはCu,Al,Ag,Sn,Pb,SnPb,AgPt,SnAg,SnBi
などがある。
The semiconductor device DETAILED DESCRIPTION OF THE INVENTION The present invention is directed, IC chips, capacitors chip, BGA (B all G ri
d A rray), include mounting substrate, the electrode terminal including a chip, the electrode of the chip mounting substrate (mounting wiring board), the solder balls formed later in the electrode. The metal of the electrode terminal is Cu, Al, Ag, Sn, Pb, SnPb, AgPt, SnAg, SnBi.
and so on.

【0020】電極端子表面の金属酸化物を除去する方法
の一つとして先に説明したプラズマ処理方法は、例えば
並行平板型の電極を備えた高周波プラズマ処理装置、マ
イクロ波放電プラズマ処理装置等の周知のプラズマ処理
装置によって実施できる。
The plasma processing method described above as one of the methods for removing the metal oxide on the surface of the electrode terminal is a known method such as a high-frequency plasma processing apparatus having a parallel plate type electrode, a microwave discharge plasma processing apparatus, or the like. Can be performed by the plasma processing apparatus.

【0021】導電性接着剤の塗布方法としてはディスペ
ンサー法、印刷法、転写法などがある。塗布した後、大
気中に取り出し、加熱硬化する。ペーストが硬化するま
での高温中での酸素の金属表面への接触を防止するた
め、加熱硬化も不活性ガス雰囲気中で行うことが好まし
い。
Examples of the method of applying the conductive adhesive include a dispenser method, a printing method, and a transfer method. After application, it is taken out into the atmosphere and cured by heating. In order to prevent oxygen from coming into contact with the metal surface at a high temperature until the paste is hardened, the heat hardening is also preferably performed in an inert gas atmosphere.

【0022】電極端子表面の金属酸化物を機械的に除去
する方法としては、鋭利な先端構造を持つ金属、セラミ
ック等により端子表面を削り取る。また、先端が丸状、
平面上の金属、セラミック等の治具で圧力をかけ端子面
を移動することにより酸化膜が除去される。これは、導
電性接着剤中の例えばAg等の金属粒子が圧力により電極
端子表面の酸化膜を破壊するためである。
As a method for mechanically removing the metal oxide on the surface of the electrode terminal, the terminal surface is scraped off with a metal or ceramic having a sharp tip structure. Also, the tip is round,
The oxide film is removed by moving the terminal surface by applying pressure with a jig such as a metal or ceramic on a flat surface. This is because metal particles such as Ag in the conductive adhesive destroy the oxide film on the electrode terminal surface due to pressure.

【0023】電極端子表面には導電性接着剤が塗布され
ているため、新たにできた金属表面は酸化膜除去後すぐ
に導電性接着剤で被覆されるため、大気中の酸素に接触
することなく酸化は防止される。
Since a conductive adhesive is applied to the surface of the electrode terminals, the newly formed metal surface is covered with the conductive adhesive immediately after removing the oxide film. Oxidation is prevented.

【0024】これらの導電性接着剤の塗布、硬化の工程
は、ICチップの場合、ウェハ上で行ってから個別チップ
に分離してもよい。
In the case of an IC chip, the steps of applying and curing these conductive adhesives may be performed on a wafer and then separated into individual chips.

【0025】また、本発明の代表的な製造装置は、前述
したように半導体装置における電極端子表面の酸化物を
除去するために半導体装置の電極端子表面を所定の減
圧下でプラズマ処理するプラズマ発生手段とガス供給口
と排気口とを有するプラズマ処理室を備えている。ガス
供給口からは、ArやAr+H2,Xe等の希ガスもし
くは窒素ガスをプラズマ処理室内の供給する。排気口か
らは排気ポンプにより排気し、プラズマ処理室内の圧力
を例えば1〜100Paに設定する。
Further, as described above, a typical manufacturing apparatus of the present invention is a plasma generating apparatus for performing a plasma treatment on an electrode terminal surface of a semiconductor device under a predetermined reduced pressure in order to remove an oxide on the electrode terminal surface of the semiconductor device. A plasma processing chamber having means, a gas supply port, and an exhaust port is provided. A rare gas or a nitrogen gas such as Ar, Ar + H 2 , or Xe is supplied from the gas supply port into the plasma processing chamber. Air is exhausted from the exhaust port by an exhaust pump, and the pressure in the plasma processing chamber is set to, for example, 1 to 100 Pa.

【0026】プラズマ発生手段は、例えば高周波電源と
並行平板型の電極を備えた高周波プラズマ処理装置、も
しくはマイクロ波電源と放電室を備えたマイクロ波放電
プラズマ処理装置等の周知のプラズマ処理装置で構成さ
れる。
The plasma generating means is constituted by a well-known plasma processing apparatus such as a high-frequency plasma processing apparatus having a high-frequency power supply and a parallel plate type electrode, or a microwave discharge plasma processing apparatus having a microwave power supply and a discharge chamber. Is done.

【0027】上記の中間室は、プラズマ処理室との
導電性接着剤の塗布室との間に設けた中継室であり、プ
ラズマ処理された半導体装置をプラズマ処理室から大気
圧の塗布室内に搬送する際に、プラズマ処理室の圧力が
急上昇しないように緩衝域として設けている。
The intermediate chamber is a relay chamber provided between the plasma processing chamber and the chamber for applying the conductive adhesive, and transports the semiconductor device subjected to plasma processing from the plasma processing chamber to the atmospheric pressure coating chamber. In this case, the pressure is provided as a buffer region so that the pressure of the plasma processing chamber does not suddenly increase.

【0028】したがって、中間室には半導体装置を搬
入、搬出させる1組のゲートと、プラズマ処理された半
導体装置の電極端子表面を酸化させないように非酸化性
ガスを供給するガス供給口と排気口とが設けられ、プラ
ズマ処理された半導体装置をプラズマ処理室から大気圧
の塗布室内に搬送する際に、室内を非酸化性ガス雰囲気
に保持するように構成されている。
Therefore, a set of gates for loading / unloading the semiconductor device into / from the intermediate chamber, a gas supply port for supplying a non-oxidizing gas so as not to oxidize the electrode terminal surface of the plasma-processed semiconductor device, and an exhaust port. When a semiconductor device subjected to plasma processing is transported from the plasma processing chamber to the coating chamber at atmospheric pressure, the chamber is maintained in a non-oxidizing gas atmosphere.

【0029】ガス供給口からは、非酸化性ガスとして窒
素ガス、希ガス等の不活性ガス、もしくは場合によって
は酸素を含まない例えば水素ガス等の還元ガスが供給さ
れる。ガス圧はプラズマ処理室内の圧力より高く、例え
ば100〜500Pa程度に設定しておけばよい。
From the gas supply port, an inert gas such as a nitrogen gas or a rare gas or a reducing gas such as a hydrogen gas containing no oxygen is supplied as a non-oxidizing gas in some cases. The gas pressure may be set higher than the pressure in the plasma processing chamber, for example, about 100 to 500 Pa.

【0030】上記の塗布室には、中間室を中継した半
導体装置の電極端子表面に、大気圧の非酸化性ガス雰囲
気中で導電性接着剤を塗布する手段が設けられている。
この塗布する手段としては、例えば塗布液タンクに接続
されたディスペンサーから所定量の導電性接着剤を半導
体装置の電極端子表面に供給する機構を備えており、ま
た、ディスペンサーと半導体装置とを相対的に移動させ
てディスペンサーと塗布すべき電極端子との位置合わせ
が行える機構をも有している。
The coating chamber is provided with a means for coating a conductive adhesive in a non-oxidizing gas atmosphere at atmospheric pressure on the surface of the electrode terminal of the semiconductor device connected to the intermediate chamber.
As means for applying, for example, a mechanism for supplying a predetermined amount of conductive adhesive from a dispenser connected to a coating liquid tank to the electrode terminal surface of the semiconductor device is provided, and the dispenser and the semiconductor device are relatively And a mechanism for positioning the dispenser and the electrode terminal to be coated.

【0031】また、中間室と同様に室内を非酸化性ガス
雰囲気とするため、窒素ガス、希ガス等の不活性ガス、
もしくは場合によっては酸素を含まない例えば水素ガス
等の還元ガスを供給するためのガス供給口及び排気口を
有している。
Since the interior of the room is made of a non-oxidizing gas atmosphere as in the case of the intermediate room, an inert gas such as a nitrogen gas or a rare gas is used.
Alternatively, in some cases, it has a gas supply port and an exhaust port for supplying a reducing gas such as hydrogen gas which does not contain oxygen.

【0032】上記の搬送手段は、半導体装置をプラズ
マ処理室から塗布室まで順次搬送するものであり、各々
の室から室へと間歇的にもしくは連続的に半導体装置を
移動できる構成となっている。
The transfer means transfers the semiconductor device sequentially from the plasma processing chamber to the coating chamber, and is configured to intermittently or continuously move the semiconductor device from each chamber to the chamber. .

【0033】以上説明したように、本発明の製造装置
は、プラズマ処理室で電極端子表面の酸化物を除去して
から塗布室で導電性接着剤が塗布されるまで、電極端子
表面が再度酸化されないように、一貫して酸素ガスを除
去した雰囲気(非酸化性雰囲気)で処理する構成にした
点が特徴の一つとなっている。
As described above, in the manufacturing apparatus of the present invention, the electrode terminal surface is oxidized again after the oxide on the electrode terminal surface is removed in the plasma processing chamber until the conductive adhesive is applied in the coating chamber. One of the features is that processing is performed in an atmosphere (a non-oxidizing atmosphere) from which oxygen gas has been removed so as not to be performed.

【0034】[0034]

【実施例】以下、本発明の代表的な実施例を図面にした
がって説明する。 〈実施例1〉図1〜図5は本発明の第1の実施例を示す
図であり、これにより実施例の製造プロセスを説明す
る。図1は半導体チップ1の断面図であり、半導体チッ
プ1は回路面を下にしており、Cuの電極端子2が形成さ
れている。電極端子2の表面にはCuの酸化膜3が生成し
ている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical embodiment of the present invention will be described below with reference to the drawings. <Embodiment 1> FIGS. 1 to 5 show a first embodiment of the present invention, and the manufacturing process of the embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view of a semiconductor chip 1. The semiconductor chip 1 has a circuit surface facing down, and Cu electrode terminals 2 are formed. A Cu oxide film 3 is formed on the surface of the electrode terminal 2.

【0035】図2は、プラズマ処理によりCuの酸化膜3
を除去した断面図である。すなわち、酸化膜3の除去
は、周波数13.56MHz、出力500Wの並行平板
型の高周波プラズマ処理装置(製造装置の詳細は実施例
5で説明する)を用いて、処理圧力10Paの条件のArプ
ラズマで行った。
FIG. 2 shows a Cu oxide film 3 formed by plasma treatment.
FIG. That is, the removal of the oxide film 3 is performed using a parallel plate type high-frequency plasma processing apparatus with a frequency of 13.56 MHz and an output of 500 W (the details of the manufacturing apparatus will be described in Example 5), and Ar plasma under a processing pressure of 10 Pa is used. I went in.

【0036】図3は、上記プラズマ処理により酸化物が
除去された電極端子2の表面に、市販の導電性接着剤ペ
ースト4を塗布して形成した断面図である。導電性接着
剤ペースト4の塗布に際しては、酸化膜3の除去後、Cu
電極端子2の表面を大気に接触させずN2雰囲気中でCu電
極端子2上に導電性接着剤ペースト4を形成した。
FIG. 3 is a cross-sectional view formed by applying a commercially available conductive adhesive paste 4 to the surface of the electrode terminal 2 from which the oxide has been removed by the plasma treatment. When applying the conductive adhesive paste 4, after removing the oxide film 3,
A conductive adhesive paste 4 was formed on the Cu electrode terminal 2 in an N 2 atmosphere without bringing the surface of the electrode terminal 2 into contact with the atmosphere.

【0037】市販の導電性接着剤ペースト4はエポキシ
樹脂とAg粒子からなり、等方性の導電性接着剤である。
導電性接着剤ペースト4の形成はディスペンサーで行っ
た。図4は、半導体チップ1を実装基板5に搭載した断
面図である。導電性接着剤ペースト4を形成後、大気中
に取り出し実装基板5に形成されたAuの電極端子6と位
置合わせを行い、実装基板5に半導体チップ1を搭載し
た。これを、N2雰囲気中で150℃1時間の条件で加熱
硬化した。
The commercially available conductive adhesive paste 4 is made of an epoxy resin and Ag particles, and is an isotropic conductive adhesive.
The formation of the conductive adhesive paste 4 was performed with a dispenser. FIG. 4 is a sectional view in which the semiconductor chip 1 is mounted on the mounting board 5. After forming the conductive adhesive paste 4, the semiconductor chip 1 was mounted on the mounting substrate 5 by taking it out into the air and aligning it with the Au electrode terminals 6 formed on the mounting substrate 5. This was cured by heating at 150 ° C. for 1 hour in an N 2 atmosphere.

【0038】図5は、アンダーフィル7を形成した断面
図である。上記加熱硬化により半導体チップ1と実装基
板5の端子間を接続した後、半導体チップ1と実装基板
5の間隙にエポキシ樹脂のアンダーフィル7を注入して
150℃1時間で硬化した。
FIG. 5 is a sectional view in which the underfill 7 is formed. After the terminals of the semiconductor chip 1 and the mounting substrate 5 were connected by the above heat curing, an underfill 7 of an epoxy resin was injected into a gap between the semiconductor chip 1 and the mounting substrate 5 and cured at 150 ° C. for one hour.

【0039】このようにして製造した本実施例の半導体
装置の電極端子2−6間の比抵抗を、プラズマ処理を行
わなかった比較例と対比した。その結果、本実施例の比
抵抗は10-3〜10-4Ωcmであるが、比較例の場合
は、10-2〜10+4Ωcmと高く、本発明によって接続
抵抗は著しく低減された。これによって、半導体チップ
の電極端子に金の代わりに銅を使用することが可能とな
った。
The specific resistance between the electrode terminals 2-6 of the semiconductor device of this embodiment manufactured in this way was compared with a comparative example in which no plasma treatment was performed. As a result, the specific resistance of the present example was 10 −3 to 10 −4 Ωcm, while that of the comparative example was as high as 10 −2 to 10 +4 Ωcm, and the connection resistance was significantly reduced by the present invention. This has made it possible to use copper instead of gold for the electrode terminals of the semiconductor chip.

【0040】〈実施例2〉第2の実施例を図6〜図11
で説明する。図6は半導体チップ8を搭載したボールグ
リッドアレイ基板9の断面図である。基板9の電極10
にPbSnのはんだボール11が形成されおり、その表面に
PbSnの酸化物12が生成されている。
<Embodiment 2> FIGS. 6 to 11 show the second embodiment.
Will be described. FIG. 6 is a sectional view of a ball grid array substrate 9 on which a semiconductor chip 8 is mounted. Electrode 10 of substrate 9
PbSn solder balls 11 are formed on the
An oxide 12 of PbSn is generated.

【0041】図7は、はんだボール11表面の酸化物1
2を除去した断面図である。酸化膜12の除去は、実施
例1と同様にプラズマ処理により行った。すなわち、周
波数13.56MHz、出力400Wの並行平板型の高
周波プラズマ処理装置(製造装置の詳細は実施例5で説
明する)を用いて、処理圧力8Paの条件のArプラズマで
行った。
FIG. 7 shows the oxide 1 on the surface of the solder ball 11.
FIG. 2 is a cross-sectional view from which No. 2 has been removed. The removal of the oxide film 12 was performed by a plasma treatment as in the first embodiment. That is, using a parallel plate type high-frequency plasma processing apparatus with a frequency of 13.56 MHz and an output of 400 W (the details of the manufacturing apparatus will be described in Example 5), Ar plasma at a processing pressure of 8 Pa was used.

【0042】図8は、市販のAg充填エポキシ樹脂の等方
性導電性接着剤ペースト13を形成した断面図である。
導電性接着剤ペースト4の形成は、一定の厚さのペース
ト4にはんだボール11を押しつけて付着させる転写法
で行った。
FIG. 8 is a sectional view of a commercially available isotropic conductive adhesive paste 13 of Ag-filled epoxy resin.
The conductive adhesive paste 4 was formed by a transfer method in which the solder balls 11 were pressed and adhered to the paste 4 having a constant thickness.

【0043】図9は、上記半導体チップ8を搭載した基
板9(第1の実装基板となる)を搭載する第2の実装基
板14の断面図である。実装基板14のPbSnの電極15
の表面にPbSnの酸化物16が形成されている。
FIG. 9 is a sectional view of a second mounting board 14 on which the board 9 (which will be a first mounting board) on which the semiconductor chip 8 is mounted is mounted. PbSn electrode 15 on mounting substrate 14
Is formed on the surface of PbSn.

【0044】図10は、電極15上の酸化物16を除去
した断面図である。上記図7の条件と同様にしてArプラ
ズマで酸化膜16を除去し、その後は再度酸化されない
ようにN2雰囲気中に保持した。
FIG. 10 is a cross-sectional view in which the oxide 16 on the electrode 15 has been removed. The oxide film 16 was removed by Ar plasma in the same manner as in the condition of FIG. 7, and then kept in an N 2 atmosphere so as not to be oxidized again.

【0045】図11はボールグリッドアレイ基板9を搭
載した実装基板14の断面図である。位置合わせ、搭載
後、N2雰囲気中で140℃1時間で加熱硬化した。これ
によって接続された第1の実装基板と第2の実装基板の
接続は、実施例1と同様に抵抗値が著しく低減された。
FIG. 11 is a sectional view of the mounting board 14 on which the ball grid array board 9 is mounted. After alignment and mounting, the substrate was cured by heating at 140 ° C. for 1 hour in an N 2 atmosphere. In the connection between the first mounting board and the second mounting board thus connected, the resistance value was significantly reduced as in the first embodiment.

【0046】〈実施例3〉第3の実施例を図12〜図1
7で説明する。図12は半導体素子が多数個形成された
ウェハ17の断面図であり、各々の半導体素子にはCuの
電極端子2が形成されており、その表面にはCuの酸化膜
3が生成している。
<Embodiment 3> The third embodiment is shown in FIGS.
7 will be described. FIG. 12 is a sectional view of a wafer 17 on which a large number of semiconductor elements are formed. Each semiconductor element has a Cu electrode terminal 2 formed thereon, and a Cu oxide film 3 is formed on the surface thereof. .

【0047】図13はCuの酸化膜3を除去した断面図で
ある。酸化膜3の除去は、実施例1と同様に高周波出力
500W,処理圧力10Paの条件のArプラズマで行った。
FIG. 13 is a cross-sectional view in which the Cu oxide film 3 has been removed. The removal of the oxide film 3 was performed using Ar plasma under the conditions of a high-frequency output of 500 W and a processing pressure of 10 Pa, as in Example 1.

【0048】図14は酸化物を除去した電極端子表面に
導電性接着剤ペースト4を形成した断面図である。この
酸化膜3の除去後はCu電極端子2を大気に接触させずN2
雰囲気中でCu電極端子18上に導電性接着剤ペースト2
0を印刷で形成し、150℃1時間でN2中で硬化した。
FIG. 14 is a sectional view in which the conductive adhesive paste 4 is formed on the surface of the electrode terminal from which the oxide has been removed. After the removal of the oxide film 3, the Cu electrode terminal 2 is not brought into contact with the atmosphere and N 2
Conductive adhesive paste 2 on Cu electrode terminal 18 in atmosphere
0 was formed by printing and cured in N 2 at 150 ° C. for 1 hour.

【0049】図15は、図14のウェハ17を切断して
得られた半導体チップ1の断面図である。図16は実装
基板5の断面図である。Auの電極端子6の上に導電性接
着剤ペースト24が印刷で形成されている。
FIG. 15 is a sectional view of the semiconductor chip 1 obtained by cutting the wafer 17 of FIG. FIG. 16 is a sectional view of the mounting board 5. A conductive adhesive paste 24 is formed on the Au electrode terminals 6 by printing.

【0050】図17半導体チップ1を実装基板5に搭載
してN2中で導電性接着剤24を硬化して、アンダーフィ
ル7を注入して、150℃1時間で加熱硬化した。この
ようにして得られた半導体チップ1と実装基板5の電極
端子2−6間の接続抵抗は実施例1及び2とほぼ同等で
あった。
FIG. 17 The semiconductor chip 1 was mounted on the mounting substrate 5, the conductive adhesive 24 was cured in N 2 , the underfill 7 was injected, and the mixture was heated and cured at 150 ° C. for 1 hour. The connection resistance between the semiconductor chip 1 thus obtained and the electrode terminals 2-6 of the mounting substrate 5 was substantially equal to those of Examples 1 and 2.

【0051】以上の実施例では、いずれも酸化物除去に
Arガスによるプラズマ処理を行ったが、ガス種をその
他の希ガスもしくはN2ガスに置き換えても同様の効果
が得られる。
In each of the above embodiments, the plasma treatment using Ar gas was performed to remove the oxide, but the same effect can be obtained by replacing the gas species with another rare gas or N 2 gas.

【0052】〈実施例4〉第4の実施例を図18の断面
工程図で説明する。図18(a)は、半導体チップ1上
のCu電極2の表面に酸化物3が生成している。この酸化
物28の上に流動性はあるが比較的粘性の高い導電性接
着剤ペースト4が塗布形成されている。
<Embodiment 4> A fourth embodiment will be described with reference to a sectional process diagram of FIG. FIG. 18A shows that the oxide 3 is generated on the surface of the Cu electrode 2 on the semiconductor chip 1. The conductive adhesive paste 4 having fluidity but relatively high viscosity is applied and formed on the oxide 28.

【0053】図18(b)に示したように、金属治具3
0でペースト4に接している酸化物3を機械的に削り取
る。電極2の表面が常にペースト4で覆われた状態で酸
化物を削り取るので、酸化物が除去されても露出した金
属面はペースト4で遮断され、大気と接触することはな
い。
As shown in FIG. 18B, the metal jig 3
At 0, the oxide 3 in contact with the paste 4 is mechanically scraped off. Since the oxide is scraped off while the surface of the electrode 2 is always covered with the paste 4, even if the oxide is removed, the exposed metal surface is cut off by the paste 4 and does not come into contact with the atmosphere.

【0054】このようにして図18(c)に示したよう
に、酸化物が除去された電極2のCu金属面とペースト4
が接触する。これらのプロセスは全て大気中で行われ
る。この後、実施例1〜3に示した工程と同様にして、
実装基板との接続を行った。
As shown in FIG. 18C, the Cu metal surface of the electrode 2 from which the oxide has been removed and the paste 4
Contact. All of these processes take place in the atmosphere. Thereafter, in the same manner as in the steps shown in Examples 1 to 3,
Connection with the mounting board was made.

【0055】〈実施例5〉第5の実施例を図19で説明
する。図19は導電性接着剤接続で抵抗値の小さい半導
体装置を製造するための装置31の概略断面図を示して
いる。
<Embodiment 5> A fifth embodiment will be described with reference to FIG. FIG. 19 is a schematic cross-sectional view of an apparatus 31 for manufacturing a semiconductor device having a small resistance value by a conductive adhesive connection.

【0056】先ず、この製造装置の構成から説明する
と、図示のようにこの製造装置31は、プラズマ処理室
32と、導電性接着剤の塗布室33と、これら二つの処
理室を連結する中間室44と、半導体装置及び実装基板
の少なくとも一方をこれら3室内に間歇的にもしくは連
続的に順次搬送する搬送機構45とを備えている。
First, the structure of this manufacturing apparatus will be described. As shown, the manufacturing apparatus 31 includes a plasma processing chamber 32, a conductive adhesive application chamber 33, and an intermediate chamber connecting these two processing chambers. 44, and a transport mechanism 45 for transporting at least one of the semiconductor device and the mounting substrate intermittently or continuously sequentially into these three chambers.

【0057】プラズマ処理室32には、プラズマ発生手
段が設けられており、この例では並行平板型の高周波放
電プラズマ発生装置の例を示している。すなわち、この
プラズマ発生手段は、高周波電源50、アノード電極3
6、カソード電極35、プラズマ発生用ガスを室内に供
給するガス供給口46a、図示されていない排気ポンプ
に接続された排気口47b、及び被処理試料となる例え
ば半導体チップ34が載置される試料台を兼ねた搬送治
具34を備えている。なお、48aは試料を室内に搬入
する第1のゲートを示している。
The plasma processing chamber 32 is provided with a plasma generating means. In this example, a parallel plate type high frequency discharge plasma generating apparatus is shown. That is, the plasma generating means includes the high frequency power supply 50, the anode electrode 3
6, a cathode electrode 35, a gas supply port 46a for supplying a plasma generating gas into the chamber, an exhaust port 47b connected to an exhaust pump (not shown), and a sample on which, for example, the semiconductor chip 34 to be processed is mounted. A transport jig 34 also serving as a table is provided. Reference numeral 48a denotes a first gate for carrying a sample into a room.

【0058】プラズマ発生手段としては、この高周波放
電プラズマ発生装置に限らず、その他周知の例えば、マ
グネトロンを発振源とするマイクロ波を導波管を通し放
電管内で放電させるマイクロ波放電プラズマ発生装置に
置き換えることもできる。
The plasma generating means is not limited to this high-frequency discharge plasma generator, but may be any other well-known microwave discharge plasma generator which discharges a microwave having an oscillation source from a magnetron through a waveguide in the discharge tube. It can be replaced.

【0059】中間室44は、プラズマ処理室32と塗布
室33の壁面を隔壁として仕切られた空間であり、これ
ら二つの隔壁は可動仕切板40a、40bで形成されて
いる。46bは、ガス供給口であり、非酸化性ガス(窒
素ガスや希ガス等の不活性ガス、もしくは水素等の還元
ガス)を室内に供給して既にプラズマ処理された試料3
4の電極端子38の再酸化を防止する。
The intermediate chamber 44 is a space partitioned by the wall surfaces of the plasma processing chamber 32 and the coating chamber 33 as partition walls, and these two partition walls are formed by movable partition plates 40a and 40b. Reference numeral 46b denotes a gas supply port, which supplies a non-oxidizing gas (an inert gas such as a nitrogen gas or a rare gas, or a reducing gas such as hydrogen) into a room, and performs a plasma treatment on the sample 3.
4 prevents re-oxidation of the electrode terminal 38.

【0060】この中間室44は、放電条件を満たすため
に減圧されたプラズマ処理室32の圧力と大気圧で処理
する塗布室33との圧力差が大きいため、直接次の塗布
室33に搬入せず、緩衝域となる中間室44を中継して
段階的に圧力を上昇させるために設けるものである。
Since the intermediate chamber 44 has a large pressure difference between the pressure of the plasma processing chamber 32 reduced to satisfy the discharge condition and the coating chamber 33 for processing at atmospheric pressure, the intermediate chamber 44 is directly carried into the next coating chamber 33. Instead, it is provided to increase the pressure stepwise by relaying the intermediate chamber 44 serving as a buffer area.

【0061】したがって、試料34をプラズマ処理室3
2から塗布室33に搬送する際には、予め可動仕切板4
0a、40bを閉じ中間室44内を所定圧力に減圧して
非酸化性ガス雰囲気に保持した状態で可動仕切板40a
を開いて試料34を中間室44内に搬入し、可動仕切板
40aを閉じてから可動仕切板40bをを開いて塗布室
33に搬送する。
Therefore, the sample 34 is transferred to the plasma processing chamber 3
2 to the coating chamber 33 beforehand.
0a, 40b are closed and the inside of the intermediate chamber 44 is depressurized to a predetermined pressure to maintain a non-oxidizing gas atmosphere, and the movable partition plate 40a
Is opened, the sample 34 is carried into the intermediate chamber 44, the movable partition plate 40 a is closed, and then the movable partition plate 40 b is opened to transport the sample 34 to the coating chamber 33.

【0062】塗布室33には、導電性接着剤の供給手
段、ガス供給口46c、排気口47c、及び試料取り出
しゲート48bが設けられている。導電性接着剤の供給
手段は、ディスペンサー装置42と導電性接着剤のタン
ク49と位置合わせ手段51とを備えている。この位置
合わせ手段51によって、試料電極端子38とディスペ
ンサー装置42とを位置合わせし、ディスペンサー装置
42から接続に必要とされる導電性接着剤ペースト43
を電極端子38上に供給する。
The coating chamber 33 is provided with means for supplying a conductive adhesive, a gas supply port 46c, an exhaust port 47c, and a sample removal gate 48b. The conductive adhesive supply means includes a dispenser device 42, a conductive adhesive tank 49, and a positioning means 51. The alignment means 51 aligns the sample electrode terminal 38 with the dispenser device 42, and the conductive adhesive paste 43 required for connection from the dispenser device 42.
Is supplied on the electrode terminal 38.

【0063】なお、位置合わせ手段51は、導電性接着
剤の供給手段に設ける代わりに、搬送手段45側に設け
てもよく、ディスペンサー装置42と電極端子38とが
相対的に位置合わせできるものであればいずれを選択し
てもよい。ガス供給口46cからは、中間室44と同様
に非酸化性ガスを供給し、大気圧のガス雰囲気とする。
ガス種としては、安価で取り扱いが容易な窒素ガスが実
用的である。
The positioning means 51 may be provided on the conveying means 45 side instead of the conductive adhesive supply means, and the dispenser device 42 and the electrode terminal 38 can be relatively positioned. If so, any may be selected. A non-oxidizing gas is supplied from the gas supply port 46c as in the case of the intermediate chamber 44, and the gas atmosphere is set to an atmospheric pressure.
As a gas type, nitrogen gas which is inexpensive and easy to handle is practical.

【0064】この装置によれば、試料34の電極端子3
8に形成された酸化物39の除去工程から導電性接着剤
ペースト43の塗布工程まで、非酸化性ガス雰囲気中で
実施するので、プラズマ処理された電極端子表面を再酸
化することなしに導電性接着剤ペースト43を塗布する
ことができ、それによって電極端子間の接続抵抗を確実
に低減することができる。
According to this apparatus, the electrode terminal 3 of the sample 34
Since the steps from the step of removing the oxide 39 formed in Step 8 to the step of applying the conductive adhesive paste 43 are carried out in a non-oxidizing gas atmosphere, the electrode terminals which have been subjected to the plasma treatment can be electrically conductive without being reoxidized. The adhesive paste 43 can be applied, so that the connection resistance between the electrode terminals can be reliably reduced.

【0065】次に、この装置を使用した半導体装置の製
造方法の一例を説明する。先ず、半導体チップ34をプ
ラズマ処理室32のゲート48aから搬入し、カソード
電極35の上に設置する。プラズマ処理室32は、不図
示の排気ポンプにより排気口47aから排気すると共
に、ガス供給口46aからAr等の希ガスを供給し、室
内雰囲気を例えば1〜100Paの減圧下に保持する。
Next, an example of a method for manufacturing a semiconductor device using this device will be described. First, the semiconductor chip 34 is loaded from the gate 48 a of the plasma processing chamber 32 and is set on the cathode electrode 35. The plasma processing chamber 32 is evacuated from an exhaust port 47a by an exhaust pump (not shown) and supplies a rare gas such as Ar from a gas supply port 46a to maintain the indoor atmosphere at a reduced pressure of, for example, 1 to 100 Pa.

【0066】高周波電源50からカソード電極35とア
ノード電極36間に例えば周波数1〜30MHz、40
0〜500Wの電力を供給し、それにより高周波放電を
生じさせプラズマ37を発生させて、半導体チップ34
の電極端子38表面の酸化物39を除去する。
For example, a frequency of 1 to 30 MHz, 40
A power of 0 to 500 W is supplied to generate a high frequency discharge to generate a plasma 37, and the semiconductor chip 34
The oxide 39 on the surface of the electrode terminal 38 is removed.

【0067】次に中間室44とプラズマ処理室32間の
隔壁を形成する可動仕切板40aを開き、搬送手段45
により試料34を中間室44に搬入し、搬送後、可動仕
切板40aを閉じる。中間室44は、予め排気口47b
から不図示の排気ポンプにより排気されると共に、ガス
供給口46bから例えばAr、N2等の不活性ガスが供
給され、室内雰囲気をプラズマ処理室32の圧力よりも
多少高めの例えば100〜500Pa程度に設定してお
く。
Next, the movable partition plate 40 a forming a partition between the intermediate chamber 44 and the plasma processing chamber 32 is opened, and
Thus, the sample 34 is carried into the intermediate chamber 44, and after being transported, the movable partition plate 40a is closed. The intermediate chamber 44 has an exhaust port 47b in advance.
From together is exhausted by an exhaust pump (not shown), for example, from a gas supply port 46b Ar, inert gas such as N 2 is supplied, some example 100~500Pa about higher than the pressure of the plasma processing chamber 32 to room atmosphere Set to.

【0068】次に中間室44にAr、N2等の不活性ガ
スを導入して圧力が常圧になってから、可動仕切り板4
0bを開き、試料34を搬送治具41で、予めAr、N
2等の不活性ガスがガス供給口46cから充填された塗
布室33に搬入する。塗布室33では、位置合わせ手段
51によりディスペンサー装置42と試料34の電極端
子38とを位置合わせし、ディスペンサー装置42から
接続に必要な所定量の導電性接着剤ペースト43を供給
し電極端子38上に塗布する。
Next, an inert gas such as Ar or N 2 is introduced into the intermediate chamber 44 so that the pressure becomes normal pressure.
0b is opened, and the sample 34 is transported in advance with Ar and N
An inert gas such as 2 is carried into the coating chamber 33 filled from the gas supply port 46c. In the coating chamber 33, the dispenser device 42 and the electrode terminal 38 of the sample 34 are aligned by the alignment means 51, and a predetermined amount of conductive adhesive paste 43 necessary for connection is supplied from the dispenser device 42 and Apply to.

【0069】この装置31により電極端子38の酸化物
39を除去した後、大気中の酸素に接することなく導電
性接着剤ペースト43の形成が可能になり、接続抵抗値
が小さい半導体装置の製造が行われる。
After the oxide 39 of the electrode terminal 38 is removed by the device 31, the conductive adhesive paste 43 can be formed without contacting oxygen in the atmosphere, and the manufacture of a semiconductor device having a small connection resistance value can be achieved. Done.

【0070】[0070]

【発明の効果】以上詳述したように本発明により、導電
性接着剤を用いた電極間の接続において、接続抵抗値を
低減すると云う所期の目的を達成することができた。す
なわち、導電性接着剤の接続において電極端子の金属表
面と導電性接着剤が直接接触するため接続抵抗値の小さ
な半導体装置が得られる。
As described in detail above, according to the present invention, the desired object of reducing the connection resistance in connection between electrodes using a conductive adhesive was achieved. That is, a semiconductor device having a small connection resistance value can be obtained since the conductive adhesive is in direct contact with the metal surface of the electrode terminal when the conductive adhesive is connected.

【0071】これにより、電極端子に高価なAuもしく
はAuメッキ電極を使用しなくても、在来の安価なC
u、Al等の電極材が使用でき、産業上貢献するところ
多大なものがある。
Thus, even if expensive Au or Au-plated electrodes are not used for the electrode terminals, the conventional inexpensive C
Electrode materials such as u, Al and the like can be used, and there are many materials that contribute to industry.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例の半導体チップの断面
図。
FIG. 1 is a sectional view of a semiconductor chip according to a first embodiment of the present invention.

【図2】図1の電極端子の酸化膜を除去した断面図。2 is a sectional view of the electrode terminal of FIG. 1 from which an oxide film has been removed;

【図3】図2の電極端子上に導電性接着剤を形成した断
面図。
FIG. 3 is a sectional view in which a conductive adhesive is formed on the electrode terminals of FIG. 2;

【図4】図3の半導体チップを実装基板に搭載した断面
図。
FIG. 4 is a sectional view in which the semiconductor chip of FIG. 3 is mounted on a mounting board;

【図5】図4にアンダーフィルを形成した断面図。FIG. 5 is a cross-sectional view in which an underfill is formed in FIG. 4;

【図6】第2の実施例のボールグリッドアレイ基板の断
面図。
FIG. 6 is a sectional view of a ball grid array substrate according to a second embodiment.

【図7】図6の電極端子の酸化膜を除去した断面図。FIG. 7 is a sectional view of the electrode terminal of FIG. 6 from which an oxide film has been removed;

【図8】図7の電極端子上に導電性接着剤を形成した断
面図。
FIG. 8 is a cross-sectional view in which a conductive adhesive is formed on the electrode terminals of FIG. 7;

【図9】第2の実施例の実装基板の断面図。FIG. 9 is a cross-sectional view of a mounting board according to a second embodiment.

【図10】図10の電極端子の酸化膜を除去した断面
図。
FIG. 10 is a sectional view of the electrode terminal of FIG. 10 from which an oxide film has been removed;

【図11】図7の半導体チップを図10の実装基板に搭
載した断面図。
11 is a sectional view showing the semiconductor chip of FIG. 7 mounted on the mounting board of FIG. 10;

【図12】第3の実施例のウェハの断面図。FIG. 12 is a sectional view of a wafer according to a third embodiment.

【図13】図12の電極端子の酸化膜を除去した断面
図。
FIG. 13 is a sectional view of the electrode terminal of FIG. 12 from which an oxide film has been removed;

【図14】図13の電極端子上に導電性接着剤を形成し
た断面図。
FIG. 14 is a cross-sectional view in which a conductive adhesive is formed on the electrode terminals of FIG.

【図15】図14のウェハを切断した部分の断面図。FIG. 15 is a sectional view of a portion obtained by cutting the wafer of FIG. 14;

【図16】第3の実施例の実装基板の断面図。FIG. 16 is a sectional view of a mounting board according to a third embodiment.

【図17】図14の半導体チップを図16に搭載しアン
ダーフィルを形成した断面図。
FIG. 17 is a cross-sectional view in which the semiconductor chip of FIG. 14 is mounted on FIG. 16 and an underfill is formed;

【図18】第4の実施例の半導体チップの断面図。FIG. 18 is a sectional view of a semiconductor chip according to a fourth embodiment.

【図19】第5の実施例の半導体製造装置の断面図。FIG. 19 is a sectional view of a semiconductor manufacturing apparatus according to a fifth embodiment.

【符号の説明】[Explanation of symbols]

1、8、21、34……半導体チップ、 2、6、10、15、38……電極端子、 3、12、16、39……表面酸化物、 4、24、43……導電性接着剤(ペースト)、 5、14……実装基板、 7……アンダーフィル、 9……ボールグリッドアレイ基板、 11……はんだボール、 17……ウェハ、 30……酸化膜除去治具、 31……製造装置、 32…プラズマ処理室、 33……塗布室、 35……カソード電極、 36……アノード電極、 37……プラズマ、 40a、40b……可動仕切り板、 41……試料搬送治具、 42……ディスペンサー、 44…中間室、 45…搬送手段、 46…ガス供給口、 47a、47b、47c…排気口、 48a、48b…ゲート、 50…高周波電源、 51…位置合わせ手段。 1, 8, 21, 34 ... semiconductor chip, 2, 6, 10, 15, 38 ... electrode terminal, 3, 12, 16, 39 ... surface oxide, 4, 24, 43 ... conductive adhesive (Paste), 5, 14 mounting board, 7 underfill, 9 ball grid array board, 11 solder balls, 17 wafer, 30 jig for removing oxide film, 31 manufacturing 32, plasma processing chamber, 33, coating chamber, 35, cathode electrode, 36, anode electrode, 37, plasma, 40a, 40b, movable partition plate, 41, sample transport jig, 42 ... Dispenser, 44 ... Intermediate chamber, 45 ... Conveying means, 46 ... Gas supply port, 47a, 47b, 47c ... Exhaust port, 48a, 48b ... Gate, 50 ... High frequency power supply, 51 ... Positioning means.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉見 健二 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 坂上 雅一 神奈川県海老名市下今泉810番地 株式会 社日立製作所PC事業部内 (72)発明者 成川 泰弘 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 Fターム(参考) 5F044 KK19 QQ04 RR19  ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kenji Yoshimi 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Production Technology Laboratory (72) Inventor Masakazu Sakagami 810, Shimo-Imaizumi, Ebina-shi, Kanagawa Prefecture Hitachi, Ltd. PC Division (72) Inventor Yasuhiro Narukawa 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in Hitachi, Ltd. Production Technology Research Laboratories 5F044 KK19 QQ04 RR19

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】半導体装置の電極端子に導電性接着剤を塗
布する工程と、前記導電性接着剤が塗布された電極端子
を実装基板上の電極端子上に位置合わせする工程と、前
記導電性接着剤を硬化することにより前記位置合わせし
た両電極端子間に導電性接着剤層を形成して電気的接続
を行う工程とを有する半導体装置の製造方法であって、
前記半導体装置の電極端子に導電性接着剤を塗布する
工程は、前記半導体装置の電極端子表面をプラズマ処理
することにより、表面に形成されている酸化物を除去す
る工程と、前記プラズマ処理された電極表面を酸素に接
触させることなく非酸化性ガス雰囲気中で、その表面に
導電性接着剤を塗布する工程とを含むことを特徴とする
半導体装置の製造方法。
A step of applying a conductive adhesive to an electrode terminal of the semiconductor device; a step of positioning the electrode terminal coated with the conductive adhesive on an electrode terminal on a mounting substrate; Forming a conductive adhesive layer between the aligned electrode terminals by curing the adhesive, and making an electrical connection, the method for manufacturing a semiconductor device,
The step of applying a conductive adhesive to the electrode terminals of the semiconductor device includes a step of performing a plasma treatment on the surface of the electrode terminals of the semiconductor device to remove oxides formed on the surface, and the step of performing the plasma treatment. Applying a conductive adhesive to the electrode surface in a non-oxidizing gas atmosphere without bringing the electrode surface into contact with oxygen.
【請求項2】前記電極端子表面をプラズマ処理するに際
しては、ガス種として窒素もしくは周期律表ゼロ族元素
のガスを用いることを特徴とする請求項1記載の半導体
装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein, when the surface of the electrode terminal is subjected to plasma treatment, nitrogen or a gas of an element belonging to Group 0 of the periodic table is used as a gas species.
【請求項3】前記導電性接着剤を塗布する工程における
非酸化性ガス雰囲気は、窒素ガス雰囲気、周期律表ゼロ
族元素のガス雰囲気、もしくは還元性元素を含み酸素を
含まないガス雰囲気であることを特徴とする請求項1記
載の半導体装置の製造方法。
3. The non-oxidizing gas atmosphere in the step of applying the conductive adhesive is a nitrogen gas atmosphere, a gas atmosphere of a Group X element of the periodic table, or a gas atmosphere containing a reducing element and containing no oxygen. 2. The method for manufacturing a semiconductor device according to claim 1, wherein:
【請求項4】前記導電性接着剤を硬化することにより前
記両電極端子間に導電性接着剤層を形成して電気的接続
を行う工程においては、前記導電性接着剤の硬化を不活
性ガス雰囲気中で行うことを特徴とする請求項1記載の
半導体装置の製造方法。
4. A step of forming a conductive adhesive layer between the two electrode terminals by curing the conductive adhesive to perform electrical connection, wherein the conductive adhesive is cured by an inert gas. 2. The method according to claim 1, wherein the method is performed in an atmosphere.
【請求項5】半導体装置の電極端子に導電性接着剤を塗
布する工程と、前記導電性接着剤が塗布された電極端子
を実装基板上の電極端子上に位置合わせする工程と、前
記導電性接着剤を硬化することにより前記位置合わせさ
れた両電極端子間に導電性接着剤層を形成して電気的接
続を行う工程とを有する半導体装置の製造方法であっ
て、 前記半導体装置の電極端子に導電性接着剤を塗布する工
程は、大気中で半導体装置の電極端子に導電性接着剤を
塗布する工程と、前記導電性接着剤が電極端子上を被覆
し、それによって外気を遮断した状態下で電極端子の表
面から酸化物を機械的に除去する工程とを含むことを特
徴とする半導体装置の製造方法。
5. A step of applying a conductive adhesive to an electrode terminal of a semiconductor device, a step of aligning the electrode terminal coated with the conductive adhesive on an electrode terminal on a mounting board, and Forming a conductive adhesive layer between the aligned electrode terminals by curing an adhesive to make an electrical connection, wherein the electrode terminal of the semiconductor device is provided. Applying the conductive adhesive to the electrode terminals of the semiconductor device in the air, and covering the electrode terminals with the conductive adhesive, thereby shutting off the outside air. Mechanically removing an oxide from the surface of the electrode terminal below.
【請求項6】前記半導体装置がウェハから分離された半
導体チップであり、前記実装基板が半導体チップを搭載
する第1の基板と、前記半導体チップが搭載された前記
第1の基板を搭載する第2の基板とを有していることを
特徴とする請求項1乃至5のいずれか一つに記載の半導
体装置の製造方法。
6. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor chip separated from a wafer, and the mounting substrate has a first substrate on which the semiconductor chip is mounted, and a second substrate on which the first substrate on which the semiconductor chip is mounted is mounted. 6. The method for manufacturing a semiconductor device according to claim 1, comprising two substrates.
【請求項7】半導体装置の電極端子表面を所定の減圧下
でプラズマ処理するプラズマ発生手段とガス供給口と排
気口とを有するプラズマ処理室と、 前記プラズマ処理室でプラズマ処理された半導体装置を
減圧された非酸化性ガス雰囲気中で中継する中間室と、 前記中間室を中継した半導体装置の電極端子表面に、常
圧下の非酸化性ガス雰囲気中で導電性接着剤を塗布する
手段を有する塗布室と、 前記プラズマ処理室から塗布室まで半導体装置を順次搬
送する搬送手段とを備えたことを特徴とする半導体装置
の製造装置。
7. A plasma processing chamber having a plasma generating means for performing plasma processing on a surface of an electrode terminal of a semiconductor device under a predetermined reduced pressure, a plasma processing chamber having a gas supply port and an exhaust port, and a semiconductor device plasma-processed in the plasma processing chamber. An intermediate chamber for relaying in a reduced-pressure non-oxidizing gas atmosphere; and a means for applying a conductive adhesive in a non-oxidizing gas atmosphere under normal pressure to the electrode terminal surface of the semiconductor device relaying the intermediate chamber. An apparatus for manufacturing a semiconductor device, comprising: a coating chamber; and transport means for sequentially transporting a semiconductor device from the plasma processing chamber to the coating chamber.
【請求項8】上記プラズマ発生手段を高周波放電による
プラズマ処理装置で構成したことを特徴とする請求項7
記載の半導体装置の製造装置。
8. The plasma processing apparatus according to claim 7, wherein said plasma generating means is constituted by a plasma processing apparatus using high-frequency discharge.
An apparatus for manufacturing a semiconductor device as described in the above.
【請求項9】上記プラズマ発生手段をマイクロ波放電に
よるプラズマ処理装置で構成したことを特徴とする請求
項7記載の半導体装置の製造装置。
9. An apparatus for manufacturing a semiconductor device according to claim 7, wherein said plasma generating means is constituted by a plasma processing apparatus using microwave discharge.
JP2000009949A 2000-01-13 2000-01-13 Semiconductor device manufacturing method and device Pending JP2001196420A (en)

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Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000009949A JP2001196420A (en) 2000-01-13 2000-01-13 Semiconductor device manufacturing method and device

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Cited By (7)

* Cited by examiner, † Cited by third party
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US7095590B2 (en) 2002-10-18 2006-08-22 Alps Electric Co., Ltd. Head gimbal assembly and method for manufacturing the same
JP2007059441A (en) * 2005-08-22 2007-03-08 Namics Corp Manufacturing method of semiconductor device
JP2007336321A (en) * 2006-06-16 2007-12-27 Epson Toyocom Corp Manufacturing method of surface mounted type piezoelectric oscillator and foreign matter eliminating method of ic component mounting pad
JP2007336320A (en) * 2006-06-16 2007-12-27 Epson Toyocom Corp Method of manufacturing surface-mounting piezoelectric device
JP2010010383A (en) * 2008-06-26 2010-01-14 National Institute Of Advanced Industrial & Technology Method of bonding semiconductor chip electrode
JP2013247124A (en) * 2012-05-23 2013-12-09 Panasonic Corp Mounting device and mounting method for semiconductor element
JP2016129177A (en) * 2015-01-09 2016-07-14 富士通株式会社 Joining method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095590B2 (en) 2002-10-18 2006-08-22 Alps Electric Co., Ltd. Head gimbal assembly and method for manufacturing the same
JP2007059441A (en) * 2005-08-22 2007-03-08 Namics Corp Manufacturing method of semiconductor device
JP4700438B2 (en) * 2005-08-22 2011-06-15 ナミックス株式会社 Manufacturing method of semiconductor device
JP2007336321A (en) * 2006-06-16 2007-12-27 Epson Toyocom Corp Manufacturing method of surface mounted type piezoelectric oscillator and foreign matter eliminating method of ic component mounting pad
JP2007336320A (en) * 2006-06-16 2007-12-27 Epson Toyocom Corp Method of manufacturing surface-mounting piezoelectric device
JP2010010383A (en) * 2008-06-26 2010-01-14 National Institute Of Advanced Industrial & Technology Method of bonding semiconductor chip electrode
JP2013247124A (en) * 2012-05-23 2013-12-09 Panasonic Corp Mounting device and mounting method for semiconductor element
JP2016129177A (en) * 2015-01-09 2016-07-14 富士通株式会社 Joining method

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