JP2001185857A - Multilayer wiring board - Google Patents
Multilayer wiring boardInfo
- Publication number
- JP2001185857A JP2001185857A JP36667499A JP36667499A JP2001185857A JP 2001185857 A JP2001185857 A JP 2001185857A JP 36667499 A JP36667499 A JP 36667499A JP 36667499 A JP36667499 A JP 36667499A JP 2001185857 A JP2001185857 A JP 2001185857A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- connection conductor
- fine particles
- layer
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、複数の配線層を間
に絶縁層を介して積層させてなる多層配線基板に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board having a plurality of wiring layers laminated with an insulating layer interposed therebetween.
【0002】[0002]
【従来の技術】従来より、LEDアレイヘッド等のヘッ
ド基板を構成するのに多層配線基板が用いられている。2. Description of the Related Art Hitherto, a multilayer wiring board has been used for forming a head substrate such as an LED array head.
【0003】かかる従来の多層配線基板は、例えば図3
に示す如く、ガラスやセラミック等から成る基板11の
上面に、第1配線層12及び第2配線層13を、間に絶
縁層14を介して順次積層してなり、第1配線層12及
び第2配線層13間に位置する絶縁層14にスルーホー
ル15を形成し、その内部に接続導体16を充填させて
おくことにより第1配線層12と第2配線層13とを相
互に電気的に接続させるようにしている。[0003] Such a conventional multilayer wiring board is, for example, shown in FIG.
As shown in FIG. 1, a first wiring layer 12 and a second wiring layer 13 are sequentially laminated on an upper surface of a substrate 11 made of glass, ceramic, or the like via an insulating layer 14 therebetween. By forming a through hole 15 in the insulating layer 14 located between the two wiring layers 13 and filling the inside thereof with the connection conductor 16, the first wiring layer 12 and the second wiring layer 13 are electrically connected to each other. I try to connect.
【0004】尚、前記第1配線層12、第2配線層13
及び接続導体16の材質としては銀(Ag)や金(A
u)等の導電材料が、また前記絶縁層14の材質として
はガラス等が使用され、これらの層は導電ペーストやガ
ラスペーストを従来周知の厚膜手法、例えばスクリーン
印刷等を採用することによって基板11の上面に印刷・
塗布し、これを高温で焼き付けることによって形成され
ていた。The first wiring layer 12 and the second wiring layer 13
And silver (Ag) or gold (A
u) or the like, and glass or the like is used as the material of the insulating layer 14. These layers are made of a conductive paste or a glass paste by using a conventionally known thick film method, for example, screen printing. Print on top of 11
It was formed by coating and baking it at a high temperature.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、この従
来の多層配線基板においては、絶縁層14を形成するガ
ラス等の線膨張係数が0.5×10-6/℃〜9×10-6
/℃であるのに対し、接続導体16を形成する銀や金等
の線膨張係数が10×10-6/℃〜35×10-6/℃と
比較的大きいことから、これらを前述の厚膜手法によっ
て形成すると、ペースト焼き付け後の冷却に伴う絶縁層
14と接続導体16との収縮量の相違に起因して接続導
体16に大きな熱応力が印加されるとともに該応力によ
ってスルーホール15内の接続導体16に大きな亀裂が
生じ、その結果、第1配線層12と第2配線層13とを
良好に接続させておくことが不可となる欠点を有してい
た。However, in this conventional multilayer wiring board, the linear expansion coefficient of the glass or the like forming the insulating layer 14 is 0.5 × 10 −6 / ° C. to 9 × 10 −6.
/ ° C, whereas the coefficient of linear expansion of silver, gold, etc. forming the connection conductor 16 is relatively large, from 10 × 10 −6 / ° C to 35 × 10 −6 / ° C. When formed by the film method, a large thermal stress is applied to the connection conductor 16 due to a difference in the amount of shrinkage between the insulating layer 14 and the connection conductor 16 due to the cooling after baking of the paste, and the stress in the through hole 15 is generated by the stress. A large crack was generated in the connection conductor 16, and as a result, there was a disadvantage that it was impossible to connect the first wiring layer 12 and the second wiring layer 13 well.
【0006】[0006]
【課題を解決するための手段】本発明は上記欠点に鑑み
案出されたもので、本発明の多層配線基板は、基板の上
面に、第1配線層及び第2配線層を間に絶縁層を介して
順次積層するとともに、前記第1配線層及び第2配線層
を絶縁層に設けたスルーホール内の接続導体により電気
的に接続した多層配線基板において、前記接続導体中
に、酸化タングステン微粒子を0.1wt%〜7.0w
t%含有させたことを特徴とするものである。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and a multilayer wiring board according to the present invention has a first wiring layer and a second wiring layer interposed on an upper surface of the substrate. A multi-layer wiring board in which the first wiring layer and the second wiring layer are electrically connected by a connection conductor in a through hole provided in an insulating layer, and the connection conductor has tungsten oxide fine particles in the connection conductor. 0.1 wt% to 7.0 w
It is characterized by containing t%.
【0007】また本発明の多層配線基板は、前記酸化タ
ングステン微粒子の粒径が0.05μm〜5.0μmで
あることを特徴とするものである。The multilayer wiring board of the present invention is characterized in that the tungsten oxide fine particles have a particle size of 0.05 μm to 5.0 μm.
【0008】更に本発明の多層配線基板は、前記酸化タ
ングステン微粒子が、接続導体の中央域に比し周辺域に
数多く分布していることを特徴とするものである。Further, the multilayer wiring board of the present invention is characterized in that the tungsten oxide fine particles are distributed more in the peripheral region than in the central region of the connection conductor.
【0009】[0009]
【発明の実施の形態】以下、本発明を添付図面に基づい
て詳細に説明する。図1は本発明の一形態に係る多層配
線基板の断面図、図2は図1の要部を模式的に示す拡大
図であり、1は基板、2は第1配線層、3は第2配線
層、4は絶縁層、5はスルーホール、6は接続導体、7
は酸化タングステン微粒子である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of a multilayer wiring board according to one embodiment of the present invention, and FIG. 2 is an enlarged view schematically showing a main part of FIG. 1, wherein 1 is a substrate, 2 is a first wiring layer, and 3 is a second wiring layer. Wiring layer, 4 is insulating layer, 5 is through hole, 6 is connection conductor, 7
Are tungsten oxide fine particles.
【0010】前記基板1は、アルミナセラミックス、ム
ライト、窒化アルミニウム、ガラスセラミックス、石
英、アルカリガラス、無アルカリガラス等の電気絶縁性
材料から成り、その上面で第1配線層2、絶縁層4、第
2配線層3等を支持するための支持母材として機能す
る。The substrate 1 is made of an electrically insulating material such as alumina ceramics, mullite, aluminum nitride, glass ceramics, quartz, alkali glass, non-alkali glass, etc., and has a first wiring layer 2, an insulating layer 4, It functions as a supporting base material for supporting the two wiring layers 3 and the like.
【0011】尚、前記基板1は、例えばアルミナセラミ
ックスから成る場合、アルミナ、シリカ、マグネシア等
のセラミックス原料粉末に適当な有機溶剤、溶媒を添加
・混合して泥漿状になすとともに、これを従来周知のド
クターブレード法やカレンダーロール法等を採用するこ
とによってセラミックグリーンシート(セラミック生シ
ート)を得、しかる後、該グリーンシートを所定形状に
打ち抜いた上、高温(約1600℃)で焼成することに
より製作される。When the substrate 1 is made of, for example, alumina ceramics, an appropriate organic solvent and a solvent are added to and mixed with a ceramic raw material powder of alumina, silica, magnesia or the like to form a slurry. A ceramic green sheet (ceramic green sheet) is obtained by employing a doctor blade method, a calendar roll method, or the like, and thereafter, the green sheet is punched into a predetermined shape and fired at a high temperature (about 1600 ° C.). Be produced.
【0012】また前記基板1の上面には、複数個の第1
配線層2と、複数個の第2配線層3とが、間に絶縁層4
を介して被着・積層される。On the upper surface of the substrate 1, a plurality of first
The wiring layer 2 and the plurality of second wiring layers 3 have an insulating layer 4 therebetween.
Is applied and laminated.
【0013】前記第1配線層2及び第2配線層3は、銀
や金、或いは、これらの合金等によって各々が所定パタ
ーンをなすように形成されており、両配線層2,3は後
述する接続導体6を介して相互に電気的に接続されるよ
うになっている。The first wiring layer 2 and the second wiring layer 3 are formed of silver, gold, an alloy thereof, or the like so as to form a predetermined pattern, and both wiring layers 2 and 3 will be described later. They are electrically connected to each other via the connection conductor 6.
【0014】前記第1配線層2及び第2配線層4は、従
来周知の厚膜手法を採用することによって基板1の上面
及び絶縁層4の上面にそれぞれ被着・形成される。即
ち、第1配線層2は、例えば銀粉末に適当な有機溶媒・
溶剤を添加・混合して得た導電ペーストを基板1の上面
に従来周知のスクリーン印刷等によって印刷・塗布した
上、高温(350℃〜800℃)で焼き付けることによ
って形成され、また第2配線層3は、第1配線層2の形
成に用いたのと同様の導電ペーストを絶縁層4の上面に
従来周知のスクリーン印刷等によって印刷・塗布した
上、高温(350℃〜800℃)で焼き付けることによ
って形成される。The first wiring layer 2 and the second wiring layer 4 are respectively attached and formed on the upper surface of the substrate 1 and the upper surface of the insulating layer 4 by employing a conventionally known thick film method. That is, the first wiring layer 2 is made of, for example, an organic solvent
A conductive paste obtained by adding and mixing a solvent is formed by printing and applying on the upper surface of the substrate 1 by conventionally known screen printing or the like, and then baking at a high temperature (350 ° C. to 800 ° C.). 3 is to print and apply the same conductive paste as that used for forming the first wiring layer 2 on the upper surface of the insulating layer 4 by a conventionally known screen printing or the like, and then bake it at a high temperature (350 ° C. to 800 ° C.). Formed by
【0015】尚、これら配線層2,3の線膨張係数は、
銀を主成分とする導電材料から成る場合、10×10-6
/℃〜12×10-6/℃となる。The linear expansion coefficients of these wiring layers 2 and 3 are as follows:
10 × 10 -6 when made of a conductive material containing silver as a main component
/ ° C. to 12 × 10 −6 / ° C.
【0016】一方、前記第1配線層2と前記第2配線層
3の間に介在される絶縁層4は、第1配線層2と第2配
線層3とを電気的に絶縁するためのものであり、0.5
×10-6/℃〜9×10-6/℃の線膨張係数をもった珪
酸塩ガラス等によって形成される。On the other hand, the insulating layer 4 interposed between the first wiring layer 2 and the second wiring layer 3 serves to electrically insulate the first wiring layer 2 from the second wiring layer 3. And 0.5
It is formed of a silicate glass or the like having a linear expansion coefficient of × 10 −6 / ° C. to 9 × 10 −6 / ° C.
【0017】また前記絶縁層4には、その所定箇所、具
体的には、電気的に接続される配線層同士2,3が交差
する箇所にスルーホール5を有しており、該各スルーホ
ール5の内部には接続導体6が充填されている。The insulating layer 4 has through-holes 5 at predetermined locations, specifically, at locations where the electrically connected wiring layers 2 and 3 intersect each other. 5 is filled with a connection conductor 6.
【0018】前記スルーホール5は、第1配線層2及び
第2配線層3の線幅が50μmの場合、その1.5倍〜
8倍に相当する75μm〜400μm程度の径を有した
円形状に形成されており、その内部で接続導体6を保持
するようになっている。When the line width of the first wiring layer 2 and the second wiring layer 3 is 50 μm, the through hole 5 is 1.5 times as large as that of the first wiring layer 2 and the second wiring layer 3.
It is formed in a circular shape having a diameter of about 75 μm to 400 μm corresponding to eight times, and holds the connection conductor 6 therein.
【0019】尚、前記絶縁層4は、珪酸塩ガラスから成
る場合、珪酸塩ガラスの粉末に適当な有機溶媒・溶剤を
添加・混合して得たガラスペーストを従来周知の厚膜手
法、例えばスクリーン印刷等によって、スルーホール5
の形成箇所を除く基板1の上面全体にわたって印刷・塗
布し、これを高温で焼き付けることにより形成される。When the insulating layer 4 is made of silicate glass, a glass paste obtained by adding and mixing an appropriate organic solvent / solvent to silicate glass powder is applied to a conventionally known thick film method, for example, a screen. Through-hole 5 by printing etc.
Is formed by printing and applying over the entire upper surface of the substrate 1 excluding the formation location of, and baking it at a high temperature.
【0020】また前記絶縁層4のスルーホール5内に充
填される接続導体6は、先に述べた第1配線層2や第2
配線層3と同様の材質、即ち、銀や金、或いは、これら
の合金等により形成され、その下面側で第1配線層2
と、上面側で第2配線層3と接触することにより両配線
層2,3を電気的に接続するようになっている。The connection conductor 6 filled in the through hole 5 of the insulating layer 4 is formed by the first wiring layer 2 and the second
The first wiring layer 2 is formed of the same material as the wiring layer 3, that is, silver, gold, or an alloy thereof.
Then, both wiring layers 2 and 3 are electrically connected by contacting the second wiring layer 3 on the upper surface side.
【0021】尚、前記接続導体6は、例えば銀粉末に適
当な有機溶媒・溶剤を添加・混合して得た導電ペースト
を絶縁層4のスルーホール5内にスクリーン印刷等によ
って印刷・充填し、これを高温(350℃〜600℃)
で焼き付けることにより形成され、かかる接続導体6の
導体部分の弾性率は6.9×1010Pa〜8.0×10
10Paの大きな値となる。The connection conductor 6 is printed and filled with a conductive paste obtained by, for example, adding and mixing an appropriate organic solvent and solvent to silver powder into the through hole 5 of the insulating layer 4 by screen printing or the like. High temperature (350 ° C to 600 ° C)
The elasticity of the conductor portion of the connection conductor 6 is 6.9 × 10 10 Pa to 8.0 × 10
This is a large value of 10 Pa.
【0022】そして前記接続導体6には、これを形成す
る銀や金等の金属よりも低い弾性率をもった酸化タング
ステン微粒子7が0.1wt%〜7.0wt%だけ含有
される。The connection conductor 6 contains only 0.1 wt% to 7.0 wt% of tungsten oxide fine particles 7 having an elastic modulus lower than that of a metal such as silver or gold forming the connection conductor.
【0023】このように、前記接続導体6中に弾性率の
低い酸化タングステン微粒子7を0.1wt%〜7.0
wt%含有させることにより、絶縁層4や第1配線層
2,第2配線層3,接続導体8等を従来周知の厚膜手法
によって形成する際、ガラスペーストや導電ペーストを
焼き付けた後の冷却に伴って接続導体6と絶縁層4との
収縮量の相違に起因する熱応力が印加されても、該応力
を酸化タングステン微粒子7の変形によって良好に緩和
・吸収することができ、これによって接続導体6の亀裂
を皆無とし、第1配線層2と第2配線層3とを良好な状
態で電気的に接続させておくことが可能となる。As described above, the tungsten oxide fine particles 7 having a low elastic modulus are contained in the connection conductor 6 in an amount of 0.1 wt% to 7.0 wt%.
When the insulating layer 4, the first wiring layer 2, the second wiring layer 3, the connection conductor 8, and the like are formed by a conventionally known thick film method, cooling after baking a glass paste or a conductive paste is performed. Accordingly, even if a thermal stress due to the difference in the amount of contraction between the connection conductor 6 and the insulating layer 4 is applied, the stress can be favorably alleviated and absorbed by the deformation of the tungsten oxide fine particles 7, whereby the connection With no cracks in the conductor 6, the first wiring layer 2 and the second wiring layer 3 can be electrically connected in a good state.
【0024】尚、前記酸化タングステン微粒子7の含有
率が0.1wt%よりも小さいと、絶縁層4や第1配線
層2,第2配線層3等を従来周知の厚膜手法によって形
成する際、接続導体6に印加される熱応力を十分に緩和
することができず、また含有率が7.0wt%よりも大
きいと、接続導体6の導電抵抗が大きくなるので、接続
導体6に通電した際、この部分で失われる電力が極めて
大となる不都合を生じる。If the content of the tungsten oxide fine particles 7 is smaller than 0.1 wt%, the insulating layer 4, the first wiring layer 2, the second wiring layer 3 and the like may be formed by a conventionally known thick film method. When the thermal stress applied to the connection conductor 6 cannot be sufficiently reduced, and when the content is more than 7.0 wt%, the conduction resistance of the connection conductor 6 increases, so that the connection conductor 6 is energized. In this case, there is a disadvantage that the power lost in this portion is extremely large.
【0025】従って前記接続導体6中に存在する酸化タ
ングステン微粒子7の含有率は0.1wt%〜7.0w
t%の範囲内に設定する必要がある。Accordingly, the content of the tungsten oxide fine particles 7 present in the connection conductor 6 is 0.1 wt% to 7.0 w
It must be set within the range of t%.
【0026】また前記酸化タングステン微粒子7を、接
続導体6の中央域に比し周辺域に数多く分布させておけ
ば、熱応力が極大となる絶縁層4と接続導体6との界面
付近に酸化タングステン微粒子7が集中する形となるた
め、応力をより効果的に吸収・緩和することができる利
点がある。If the tungsten oxide fine particles 7 are distributed more in the peripheral region than in the central region of the connection conductor 6, the tungsten oxide particles near the interface between the insulating layer 4 and the connection conductor 6 where the thermal stress becomes maximum will be formed. Since the fine particles 7 are concentrated, there is an advantage that stress can be more effectively absorbed and reduced.
【0027】従って、前記酸化タングステン微粒子7
は、接続導体6の中央域に比し周辺域に数多く分布させ
ておくことが好ましい。Therefore, the tungsten oxide fine particles 7
Is preferably distributed more in the peripheral area than in the central area of the connection conductor 6.
【0028】前記酸化タングステン微粒子7としては、
粒径0.05μm〜5.0μmのものが好適に使用さ
れ、該酸化タングステン微粒子7はタングステン(W)
から成る金属微粒子を約300℃の比較的低い温度で所
定時間加熱し、これを酸化させることにより形成され
る。The tungsten oxide fine particles 7 include:
Particles having a particle size of 0.05 μm to 5.0 μm are preferably used, and the tungsten oxide fine particles 7 are made of tungsten (W).
Are formed by heating the metal fine particles made of at a relatively low temperature of about 300 ° C. for a predetermined time and oxidizing them.
【0029】尚、上述の酸化タングステン微粒子7は、
接続導体6を前述の厚膜手法によって形成する際に同時
に形成することもできる。The above-mentioned tungsten oxide fine particles 7 are
The connection conductor 6 can be formed at the same time when the connection conductor 6 is formed by the above-mentioned thick film method.
【0030】例えば、接続導体6となる導電ペースト中
に、タングステン微粒子(粒径:0.05μm〜5.0
μm)を0.1wt%〜5.0wt%だけ添加・混合さ
せておき、これらタングステン微粒子の一部もしくは全
部を導電ペーストを焼き付ける際に大気中の酸素等と化
学反応させて酸化することにより酸化タングステン微粒
子7が接続導体6中に分散された状態で形成されること
となる また前記酸化タングステン微粒子7を接続導体6の中央
域に比し周辺域に数多く分布させるには、接続導体6を
上述の厚膜手法によって形成する際、タングステン微粒
子の含有率を異ならせた2種類の導電ペーストを準備
し、タングステン微粒子の含有率が低い導電ペーストを
タングステン微粒子の含有率が高い導電ペーストで覆う
ようにして、これらをスルーホール5内に充填させるこ
とにより実現される。For example, tungsten fine particles (particle diameter: 0.05 μm to 5.0 μm) are contained in the conductive paste serving as the connection conductor 6.
μm) is added and mixed in an amount of 0.1 wt% to 5.0 wt%, and a part or all of these tungsten fine particles are chemically reacted with oxygen or the like in the air when the conductive paste is baked to oxidize. The tungsten fine particles 7 are formed in a state of being dispersed in the connection conductor 6. In order to distribute the tungsten oxide fine particles 7 more in the peripheral region than in the central region of the connection conductor 6, the connection conductor 6 is formed as described above. When forming by the thick film method, two kinds of conductive pastes having different contents of tungsten fine particles are prepared, and a conductive paste having a low content of tungsten fine particles is covered with a conductive paste having a high content of tungsten fine particles. Thus, these are realized by filling the inside of the through holes 5.
【0031】尚、本発明は上述の形態に限定されるもの
ではなく、本発明の要旨を逸脱しない範囲において種々
の変更、改良等が可能である。The present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the gist of the present invention.
【0032】例えば上述の形態では配線層を2層積層さ
せた多層配線基板について説明したが、本発明は配線層
を3層以上積層させた多層配線基板にも適用可能であ
る。For example, in the above embodiment, a multilayer wiring board in which two wiring layers are stacked has been described, but the present invention is also applicable to a multilayer wiring board in which three or more wiring layers are stacked.
【0033】[0033]
【実験例】次に本発明の作用効果について実験例に基づ
き説明する。まず、銀を主成分とする径250μm、厚
み30μmの接続導体6中に平均粒径1.0μmの酸化
タングステン微粒子7を所定量ずつ含有させた9種類の
多層配線基板サンプル(サンプルNo.1〜12)を準備し
た。[Experimental Example] Next, the operation and effect of the present invention will be described based on an experimental example. First, nine types of multilayer wiring board samples (sample Nos. 1 to 5) each containing a predetermined amount of tungsten oxide fine particles 7 having an average particle diameter of 1.0 μm in a connection conductor 6 having a diameter of 250 μm and a thickness of 30 μm mainly containing silver. 12) was prepared.
【0034】これらのサンプルNo.1〜12は、銀を主成分
とする第1配線層2、硼珪酸ガラスから成る絶縁層4
(線膨張率:8.2×10-6/℃)、銀を主成分とする
第2配線層3、前述の接続導体6を全て厚膜手法によっ
て形成したものであり、各層の材質、ペースト焼き付け
時の温度条件等は全て同じに揃え、接続導体6中に存在
する酸化タングステン微粒子7の含有率のみを0.01
wt%〜9.00wt%の範囲内で異ならせるようにし
た。These sample Nos. 1 to 12 are composed of a first wiring layer 2 mainly composed of silver and an insulating layer 4 made of borosilicate glass.
(Linear expansion coefficient: 8.2 × 10 −6 / ° C.), the second wiring layer 3 containing silver as a main component, and the above-described connection conductor 6 are all formed by a thick film method, and the material and paste of each layer The temperature conditions at the time of baking were all the same, and only the content of the tungsten oxide fine particles 7 present in the connection conductor 6 was reduced to 0.01.
The weight ratio was varied within the range of wt% to 9.00 wt%.
【0035】前記サンプルNo.1〜12について、接続導体
6における亀裂の発生の有無を確認するとともに接続導
体6の導電抵抗を測定した結果を表1に示す。Table 1 shows the results of confirming the occurrence of cracks in the connection conductors 6 and measuring the conductive resistance of the connection conductors 6 for the samples Nos. 1 to 12.
【0036】[0036]
【表1】 [Table 1]
【0037】この表1によれば、酸化タングステン微粒
子7の含有率が0.10wt%未満であるサンプルNo.
1,No.2では接続導体6に亀裂を生じていることが確認
され、導電抵抗は測定できなかった。According to Table 1, the sample No. in which the content of the tungsten oxide fine particles 7 is less than 0.10 wt%.
In Nos. 1 and 2, it was confirmed that the connection conductor 6 was cracked, and the conductive resistance could not be measured.
【0038】また酸化タングステン微粒子7の含有率が
7.00wt%よりも大きいサンプルNo.11 ,No.12 は
いずれの導電抵抗も3mΩ以上と大きく、この部分で電
力が大きく損失されてしまっている。Samples No. 11 and No. 12 in which the content of the tungsten oxide fine particles 7 is larger than 7.00 wt% have a large conductive resistance of 3 mΩ or more, and the power is largely lost in this portion. .
【0039】これに対し、酸化タングステン微粒子7の
含有率を0.10wt%〜7.00wt%に設定したサ
ンプルNo.3〜No.10 では、接続導体6に亀裂を生じたも
のは一切なく、また導電抵抗についても0.94mΩ〜
2.87mΩと比較的小さく、この部分での電力の損失
は少ない。On the other hand, in the samples No. 3 to No. 10 in which the content of the tungsten oxide fine particles 7 was set to 0.10 wt% to 7.00 wt%, there was no crack in the connection conductor 6 at all. Also, the conductive resistance is 0.94 mΩ or more.
It is relatively small at 2.87 mΩ, and power loss in this portion is small.
【0040】従って、上述した実験結果によれば、スル
ーホール5内の接続導体6に亀裂を生じさせることな
く、その導電抵抗を十分に低く保つためには、接続導体
6中に含有させる酸化タングステン微粒子7の含有率を
0.1wt%〜7.0wt%に設定しなければならない
ことが判る。Therefore, according to the above-described experimental results, in order to keep the conductive resistance sufficiently low without causing cracks in the connection conductor 6 in the through-hole 5, the tungsten oxide contained in the connection conductor 6 should be used. It can be seen that the content of the fine particles 7 must be set at 0.1 wt% to 7.0 wt%.
【0041】[0041]
【発明の効果】本発明の多層配線基板によれば、基板の
上面に、第1配線層及び第2配線層を間に絶縁層を介し
て順次積層するとともに、前記第1配線層及び第2配線
層を絶縁層に設けたスルーホール内の接続導体により電
気的に接続した多層配線基板において、前記接続導体中
に、酸化タングステン微粒子を0.1wt%〜7.0w
t%含有させたことから、絶縁層や接続導体等を従来周
知の厚膜手法によって形成する際、ガラスペーストや導
電ペーストを焼き付けた後の冷却に伴って接続導体と絶
縁層との収縮量の相違に起因する熱応力が印加されて
も、該応力を酸化タングステン微粒子の変形によって良
好に緩和・吸収することができ、接続導体の亀裂を皆無
として第1配線層と第2配線層とを良好な状態で電気的
に接続させておくことが可能となる。According to the multilayer wiring board of the present invention, the first wiring layer and the second wiring layer are sequentially laminated on the upper surface of the substrate with an insulating layer interposed therebetween, and the first wiring layer and the second wiring layer are stacked. In a multilayer wiring board in which a wiring layer is electrically connected by connection conductors in through holes provided in an insulating layer, the connection conductors contain 0.1 wt% to 7.0 w of tungsten oxide fine particles.
When the insulating layer and the connection conductor are formed by a conventionally known thick film method, the amount of shrinkage between the connection conductor and the insulation layer is reduced with cooling after baking the glass paste or the conductive paste. Even if a thermal stress caused by the difference is applied, the stress can be favorably alleviated and absorbed by the deformation of the tungsten oxide fine particles, and the first wiring layer and the second wiring layer can be satisfactorily formed without any cracks in the connection conductor. It is possible to make electrical connection in a proper state.
【0042】また本発明の多層配線基板によれば、前記
酸化タングステン微粒子を接続導体の中央域に比し周辺
域に数多く分布させることにより、上述の熱応力が極大
となる両者の界面付近に前述の酸化タングステン微粒子
を集中させた形となり、応力をより効果的に吸収・緩和
することができる。According to the multilayer wiring board of the present invention, the tungsten oxide fine particles are distributed more in the peripheral area than in the central area of the connecting conductor, so that the above-mentioned interface is provided near the interface between the two where the thermal stress is maximized. Of tungsten oxide particles are concentrated, so that stress can be absorbed and reduced more effectively.
【図1】本発明の一形態に係る多層配線基板の断面図で
ある。FIG. 1 is a cross-sectional view of a multilayer wiring board according to one embodiment of the present invention.
【図2】図1の要部を模式的に示す拡大図である。FIG. 2 is an enlarged view schematically showing a main part of FIG.
【図3】従来の多層配線基板の断面図である。FIG. 3 is a sectional view of a conventional multilayer wiring board.
1・・・基板、2・・・第1配線層、3・・・第2配線
層、4・・・絶縁層、5・・・スルーホール、6・・・
接続導体、7・・・酸化タングステン微粒子DESCRIPTION OF SYMBOLS 1 ... board | substrate, 2 ... 1st wiring layer, 3 ... 2nd wiring layer, 4 ... insulating layer, 5 ... through-hole, 6 ...
Connection conductor, 7 ... Tungsten oxide fine particles
フロントページの続き Fターム(参考) 4E351 AA07 BB01 BB24 BB26 BB31 BB49 CC11 CC22 DD04 DD05 DD06 DD16 DD34 DD52 DD58 EE02 GG03 GG08 5E317 AA24 BB04 BB12 BB13 BB14 BB16 CC22 CC25 CC53 CD32 GG05 GG09 5E346 AA05 AA12 AA15 AA24 AA43 BB01 CC17 CC18 CC32 CC36 CC38 CC39 DD45 FF18 GG06 GG09 HH07 Continued on the front page F-term (reference) 4E351 AA07 BB01 BB24 BB26 BB31 BB49 CC11 CC22 DD04 DD05 DD06 DD16 DD34 DD52 DD58 EE02 GG03 GG08 5E317 AA24 BB04 BB12 BB13 BB14 BB16 CC22 CC25 CC53 CD32 GG05 A05A12 CC CC32 CC36 CC38 CC39 DD45 FF18 GG06 GG09 HH07
Claims (3)
を間に絶縁層を介して順次積層するとともに、前記第1
配線層及び第2配線層を絶縁層に設けたスルーホール内
の接続導体により電気的に接続した多層配線基板におい
て、 前記接続導体中に、酸化タングステン微粒子を0.1w
t%〜7.0wt%含有させたことを特徴とする多層配
線基板。A first wiring layer and a second wiring layer are sequentially laminated on an upper surface of a substrate via an insulating layer between the first wiring layer and the second wiring layer.
In a multilayer wiring board in which a wiring layer and a second wiring layer are electrically connected by a connection conductor in a through hole provided in an insulating layer, 0.1 w of tungsten oxide fine particles are contained in the connection conductor.
A multilayer wiring board characterized by containing t% to 7.0 wt%.
05μm〜5.0μmであることを特徴とする請求項1
に記載の多層配線基板。2. The method according to claim 1, wherein said tungsten oxide fine particles have a particle size of 0.1.
2. The film according to claim 1, wherein the thickness is in the range of 0.05 to 5.0 .mu.m.
2. The multilayer wiring board according to item 1.
の中央域に比し周辺域に数多く分布していることを特徴
とする請求項1に記載の多層配線基板。3. The multilayer wiring board according to claim 1, wherein the tungsten oxide fine particles are distributed more in a peripheral area than in a central area of the connection conductor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP36667499A JP2001185857A (en) | 1999-12-24 | 1999-12-24 | Multilayer wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP36667499A JP2001185857A (en) | 1999-12-24 | 1999-12-24 | Multilayer wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2001185857A true JP2001185857A (en) | 2001-07-06 |
Family
ID=18487371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP36667499A Pending JP2001185857A (en) | 1999-12-24 | 1999-12-24 | Multilayer wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2001185857A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011125874A1 (en) * | 2010-03-31 | 2011-10-13 | 京セラ株式会社 | Mounting board and method for manufacturing a mounting board |
JP2013074169A (en) * | 2011-09-28 | 2013-04-22 | Kyocera Corp | Thin-film wiring board |
-
1999
- 1999-12-24 JP JP36667499A patent/JP2001185857A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011125874A1 (en) * | 2010-03-31 | 2011-10-13 | 京セラ株式会社 | Mounting board and method for manufacturing a mounting board |
JP5436662B2 (en) * | 2010-03-31 | 2014-03-05 | 京セラ株式会社 | Mounting boards and devices |
JP2013074169A (en) * | 2011-09-28 | 2013-04-22 | Kyocera Corp | Thin-film wiring board |
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