JP2001185554A - Semiconductor wafer and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an Si wafer having a denuded-zone layer and a greatly improved mechanical strength as compared with a conventional Si wafer having a denuded-zone layer. SOLUTION: The Si wafer has a DZ layer (denuded zone) of 20 μm in depth on the surface of a substrate and gradually increases in BMD (oxygen precipitation micro-defect) density as depth increases from the deepest portion of the DZ layer toward the inner portion of the substrate. In the case where a BMD density N (cm-3) at a certain depth is assumed to be an average of BMD at the depth ±0.5 μm, and the common logarithm of N (cm-3) log10N is plotted with respect to the depth (μm) from the surface of the Si substrate, a gradient of N (cm-3) does not exceed 0.1(log10[cm-3]/μm).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor wafer and a method for manufacturing the same.

[0002]

2. Description of the Related Art Since a layer having a few μm in the extreme surface of a Si wafer is an important area (element area or active area) in which elements such as transistors and diodes are manufactured, minute defects (such as BMD) caused by oxygen are generated. ) And dislocations are formed in this region, causing problems such as an increase in junction leak and a defective memory retention time, which causes a reduction in device yield. Therefore, it is generally preferable that the amount of oxygen present in this region is small. However, in the CZ method widely used for the production of Si single crystals, mixing of oxygen is inevitable because a quartz crucible is used. Therefore, recently, Si
A hydrogen-annealed wafer (HAI wafer) is widely used in which a wafer is heat-treated in a hydrogen atmosphere to remove oxygen near the wafer surface so that only the surface layer becomes defect-free. By the way, it is easy to imagine that the generation of defects in the active region is not only caused by oxygen existing from the early stage of wafer manufacturing but also caused by impurities mixed in from various processes during device manufacturing. it can. In order to eliminate contamination (gettering) into the element region during the process (gettering), a technique for giving the wafer itself a gettering effect has been studied.
The HAI wafer has a feature that the surface layer is oxygen-free and oxygen is present in the bulk, and the bulk oxygen is converted to BMD, thereby having an internal gettering effect. This is expected to be a very excellent technology. You.

[0003] However, the above-mentioned Si wafer (HAI wafer) is excellent in that it has a low defect in the element region and has a gettering ability, but it has an unheated Si wafer.
Compared to a wafer, the mechanical strength is reduced, so that dislocation multiplication is caused, and as a result, the possibility of lowering the yield of a Si element such as a DRAM using this wafer as a substrate is higher than that of an unheated Si wafer. There was a problem.

[0004]

As described above, in the conventional HAI wafer, the mechanical strength is lower than that of the unheated Si wafer. It is conceivable that the possibility of lowering the yield is higher.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor wafer having a sufficiently high mechanical strength as well as a reduced defect density and gettering ability of a surface layer. And

[0006]

[MEANS FOR SOLVING THE PROBLEMS]
The semiconductor wafer according to claim 1, having a DZ layer on the surface,
The BMD density increases from the DZ layer toward the inside.
At a certain point (depth from the surface)
BMD density N (cm^-3) Before and after that point
Defined as an average value of 0.5 μm depth, the common logarithm of N lo
g₁₀N is the depth from the surface of the semiconductor wafer (μm)
, The slope is 0.1 (log
₁₀[Cm^-3] / Μm).
It is a conductor wafer. In the present invention, representative of semiconductor wafer
As an example, a Si wafer will be described below.
Is not limited to silicon. Specifically,
The structure of the Si wafer is 20 μm deep on the surface of the Si substrate.
It has the following DZ layer (defect-free layer), from the deepest part of the DZ layer
BMD density inside the substrate is gradually increasing
BMD density N (cm^-3) Before the depth of that point
After defining the mean value of ± 0.5 μm, the common logarithm of N
g₁₀N to depth (μm) from semiconductor wafer surface
And plotting, no matter what point the slope takes
0.1 (log ₁₀[Cm^-3] / Μm)
It is characterized by changing to.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor wafer, wherein a plurality of separate semiconductor wafers prepared on a semiconductor wafer are laminated in a layered manner in order of increasing BMD density to form one laminated semiconductor wafer. In the manufacturing method, the BMD density N (c
The m ^-3) defined as the depth of the average values before and after ± 0.5 [mu] m of the point, when plotting the common logarithm log 10 _N of N with respect to depth from the wafer surface ([mu] m), is the slope Each semiconductor wafer is sequentially selected and laminated so as to gradually change within 0.1 (log ₁₀ [cm ⁻³ ] / μm).

According to a third aspect of the invention, there is provided a method of manufacturing a semiconductor wafer.
The method according to claim 2, wherein a step of cutting a surface is added each time the another semiconductor wafer is stacked.

According to the above method, it is possible to provide a Si wafer having not only a low defect density in the surface layer but also a high mechanical strength.

In addition, this inclination is preferably 0.001 or more in consideration of mass production of wafers.

Here, as a process for producing a single crystal ingot for cutting a semiconductor wafer, a pulling method may be used.

The present invention can be applied not only to a Si wafer but also to a group IV semiconductor other than Si, for example, a compound semiconductor such as SiGe or SiC.

[0013]

DETAILED DESCRIPTION OF THE INVENTION The present invention can be better understood with reference to the following illustrative but non-limiting examples. (Embodiment 1) Embodiment 1 will be described with reference to FIG.

First, a boron concentration of 1 × 10
A silicon single crystal ingot 30 of ¹⁹ cm ⁻³ is pulled up and formed, and a (100) plane orientation p-type Si wafer 31 is formed.
Was cut out and produced (FIG. 3A).

After that, the silicon wafer 31 is introduced into a quartz furnace and replaced with hydrogen gas 32 (FIG. 3B), and a heat treatment is performed at normal pressure at 450 ° C. × 3 hours + 1000 ° C. × 16 hours to form the DZ layer 33. It was formed (FIG. 3C).

Then, after replacing the inside of the same furnace with an argon gas atmosphere containing 15% of oxygen, a heat treatment is performed at 1100 ° C. for 2 hours to introduce oxygen into the vicinity of the pole surface. Replace with 100% gas atmosphere and
Heat treatment of 00 ° C. × 3 hours + 1200 ° C. × 5 hours,
Finally, a DZ layer 33 was formed by performing an annealing process at 450 ° C. × 3 hours in a 100% hydrogen atmosphere 32.
(D)).

The wafer thus prepared (wafer N)
The depth distribution of BMD density (N ₀ ) in o.1) was measured by infrared tomography. Using the obtained data, FIG. 1 was prepared in which the horizontal axis represents the depth (μm) from the wafer surface layer and the vertical axis represents the common logarithm log ₁₀ N of the BMD density N (cm ⁻³ ). However, the value of N in the figure, and has a mean value of N ₀ in a range around ± 0.5 [mu] m of notable (depth). As you can see, 7
The outermost surface layer of a μm-thick wafer has so-called D
The BMD density is gradually increasing from the wafer surface toward the inside, which is the Z layer and further below the DZ layer, and the maximum value of the increase rate C (slope in FIG. 1) is approximately 0.07 (log ₁₀ [cm ⁻³ ] / μ)
m)).

Further, two new wafers (wafer No. 2 and wafer No. 3) were prepared in the same manner, and the increase rate C (log) of the BMD density in the depth direction was similarly determined.
₁₀ [cm ⁻³ ] / μm) was obtained.
0.05 and 0.07 were obtained. (Embodiment 2) Embodiment 2 will be described with reference to FIG.

Ten Si wafers on which BMD precipitate nuclei were formed by heat treatment at 780 ° C. were prepared. The densities of BMD precipitate nuclei of these wafers are different from each other, and wafers [1], [2],
Wafer [3], wafer [4],..., Wafer [10]. However, only the wafer [10] had no BMD precipitation nuclei (including the case where the nuclei were below the detection limit).

First, the surface of the wafer [1] 41 and the wafer
[2] The surface of 42 was brought into close contact in a clean state, and was directly bonded at room temperature by so-called “optical contact” (FIG. 4A).

Then, after increasing the adhesive strength by heat treatment at 300 ° C., the surface of the wafer [2] 42 was polished to reduce the thickness of the wafer [2] 42 to 3 μm, and the surface layer was finished to a mirror surface state ( FIG. 4 (b)).

Next, the surface of the wafer [3] 43 was made a normal mirror surface, and the wafer [1] 41 + wafer bonded earlier
[2] The same direct bonding was performed on the wafer 42 side of 42.
Then, after increasing the adhesive strength by a heat treatment at 300 ° C., the surface of the wafer [3] 43 is polished and the wafer [3] 43 is polished.
Was reduced to a thickness of 3 μm, and then the surface layer was mirror-finished. Further, the same operation was repeated for the next wafer [4] 44 (FIG. 4C). Such an operation is repeated, that is, the wafer [n + 1] is directly bonded on the wafer [n], and then the adhesive strength is increased by a heat treatment at 300 ° C., and then the wafer [n + 1] is polished to obtain a wafer [n + 1]. After thinning [n + 1] to a thickness of 3 μm, the surface layer is finished to a mirror state, and finally, the surface of the wafer [10] is polished to reduce the wafer [10] to a thickness of 5 m, and then the surface layer is finished to a mirror state. Was. In this example, the wafer [n + 1] is directly bonded on the wafer [n] and then the wafer [n]
+1], but the wafer [n]
It is needless to say that almost the same wafer can be manufactured by directly bonding a thinned wafer [n + 1] on the wafer. Next, all the ten bonded wafers were heat-treated in an inert gas at 900 ° C. for 16 hours to increase the bonding strength and grow BMD.

The completed wafer (wafer No.
4) The BMD density (N ₀ ) distribution in the depth direction was measured by infrared tomography. Using the obtained data,
The horizontal axis represents the depth (μm) from the wafer surface layer, and the vertical axis represents the BM
FIG. 2 was prepared in which a common logarithm log ₁₀ N of D density N (cm ⁻³ ) was taken. However, in this figure, the value of N means N ₀ in a range of ± 0.5 μm before and after a point (depth) to be noted.
Is the average value.

As can be seen, the BMD density gradually increases from the surface of the wafer to the inside.
The maximum value of the increase rate C (slope in FIG. 1) is about 0.09.
(Log ₁₀ [cm ⁻³ ] / μm).

Further, two new wafers (wafer No. 5 and wafer No. 6) were prepared in the same manner, and the increase rate C (log) of the BMD density in the depth direction was similarly determined.
₁₀ [cm ⁻³ ] / μm) was obtained.
0.08 and 0.1 were obtained.

The wafers obtained in Examples 1 and 2, untreated CZ-Si wafers, ordinary hydrogen-annealed wafers (HAI wafers), and ordinary epitaxial wafers were subjected to a two-step heat treatment (780 ° C. × 3 hours + 10 hours).
(00 ° C. × 16 hours) and subjected to a three-point bending test (100
(0 ° C., 0.1 mm / min) to compare the mechanical strength (yield stress). As a result, values as shown in Table 1 were obtained. As is clear from the table, the mechanical strength of the wafers of Example 1 and Example 2 is greatly improved as compared with a normal hydrogen-annealed wafer or a heat-treated epitaxial wafer.

【table 1】 From Table 1 above, according to the method of Example 1 or Example 2, the BMD density N at a predetermined depth is also taken as the average value of the depth of ± 0.5 μm before and after the point, and the common logarithm of N
When g ₁₀ N is plotted against the depth (μm) from the surface of the semiconductor wafer, the slope is 0.1 (log).
It was found that the mechanical strength could be improved if the density was within ₁₀ [cm ⁻³ ] / μm).

Therefore, according to the first embodiment and the second embodiment, the BM is higher than that of the conventional Si wafer with the defect-free layer.
Since the internal stress caused by the generation of D (oxygen precipitation micro defects) is relaxed and the mechanical strength can be significantly improved, the yield of Si elements can be improved.

[0028]

According to the present invention, the conventional S with defect-free layer
As compared with the i-wafer, the internal stress caused by the generation of BMD (Oxygen Precipitation Micro Defect) can be relaxed and the mechanical strength can be remarkably improved, so that the yield of Si elements can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a BMD depth distribution of a wafer according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a BMD depth direction distribution of a wafer according to a second embodiment of the present invention.

FIG. 3 is an explanatory view in the order of steps for explaining the first embodiment of the present invention.

FIG. 4 is an explanatory view in the order of steps for explaining a second embodiment of the present invention.

[Explanation of symbols]

 30 Single crystal ingot of Si 31 Si wafer 32 Hydrogen gas 41 Si wafer [1] 42 Si wafer [2] 43 Si wafer [3] 44 Si wafer [4]

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Norihiko Tsuchiya 1st address, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Microelectronics Center Co., Ltd. No. 1 Toshiba-cho Toshiba Microelectronics Center F-term (reference) 4G077 AA03 BA04 FE05 FF07 HA06

Claims (3)

[Claims] 1. A semiconductor wafer having a DZ layer on the surface and having a BMD density increasing from the DZ layer toward the inside, the BMD density N (c
m ⁻³ ) is defined as the average value of the depth of ± 0.5 μm before and after the point, and the common logarithm of N log ₁₀ N is plotted against the depth (μm) from the surface. Is within 0.1 (log ₁₀ [cm ⁻³ ] / μm). 2. A method of manufacturing a semiconductor wafer in which a plurality of different semiconductor wafers prepared on a semiconductor wafer are laminated in a layered manner in order of BMD density to form one laminated semiconductor wafer, wherein the BMD density N at a certain point is determined.
(Cm ⁻³ ) is defined as the average value of the depth of ± 0.5 μm before and after the point, and the common logarithm of N log ₁₀ N is plotted against the depth (μm) from the semiconductor wafer surface. Whose inclination is 0.1 (log ₁₀ [cm ⁻³ ] / μ).
m). A method for manufacturing a semiconductor wafer, wherein 3. The method of manufacturing a semiconductor wafer according to claim 2, wherein a step of shaving the surface is added each time said another semiconductor wafer is stacked.