JP2001185448A - Capacitor array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor array wherein a smaller size and a higher capacity allow higher density mounting and height differences due to presence or absence of internal electrodes can be relaxed. SOLUTION: This capacitor array 1 comprises two internal electrodes 3a, 3b to facing with each other between layers of a laminate 2 that is configured to laminate a plurality of dielectric layers 3a, each internal electrode 3a, 3b extending in an end face side of the laminate 2 from mutually different positions, and comprises capacitor units N connected to a pair of external electrodes 5, 6 at each extending part and the end face of the laminate 2 and a capacitor group M wherein a plurality of capacitor units are arranged in a laminating direction of the laminate 2 and is characterized in that the capacitor group M is configured to arrange the capacitor units N in a staggered manner.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor array in which a plurality of capacitors are formed in one dielectric block (laminate) formed by laminating dielectric layers.

[0002]

2. Description of the Related Art With the spread of various electronic devices, the size and weight of these devices have been rapidly reduced. Especially in recent years,
There is an increasing demand for smaller and lighter electronic devices for portable use, such as a camera-integrated VTR, a mobile phone, a notebook personal computer, and a palmtop computer.

[0003] If the size and weight of such electronic devices are reduced, the circuit boards used for the electronic devices must be reduced in size and weight. From the mounting type, in which the pins of the electronic components are inserted into the through holes formed in the printed circuit board and soldered, the electronic components are placed and soldered on the conductive pattern lands provided on the printed circuit board to reduce the size and weight To surface mount technology (SMT).

The electronic components used in the SMT are collectively referred to as surface mount components (SMD). For example, a capacitor array having a plurality of built-in capacitors as disclosed in Japanese Patent No. 2657953 is a typical example. .

FIGS. 4 and 5 are external views of a conventional capacitor array 30. FIG. In FIG. 4, (a) is a side view,
FIG. 5B is a plan view, and FIG. 5 is a principal part explanatory view for explaining a positional relationship between internal electrodes and external electrodes in the plan view. As shown in the figure, the capacitor array 30 includes a plurality of internal electrodes 33 between each layer of a multilayer body 300 in which a plurality of dielectric layers 30a are stacked.
(33a, 33b) are formed facing each other. Each of the internal electrodes 33 extends to a different position on the end face side of the multilayer body 300 and is connected to the external electrodes 35 (35a, 35b) and 36 (36a, 36b) on the end face side of the multilayer body 300. . A capacitor unit 38 is formed by the dielectric layer 3a, the internal electrode 33, and the external electrodes 35 and 36. The number of the capacitor units 38 is, for example, n (n = 1, 2, 3,...) In the stacking direction of the dielectric layers 3a.

By using such a capacitor array 30, the number of capacitors to be used can be reduced as compared with the prior art, the variation in the size and shape of each capacitor can be suppressed, and the work of mounting on a circuit board can be simplified. It can be made.

Further, when a multilayer ceramic capacitor is conventionally mounted on a printed circuit board or the like, it is necessary to provide a land one size larger than the capacitor element on the circuit board, and it is difficult to mount the capacitor at high density. However, the use of the capacitor array 30 enables high-density mounting of small and large-capacity devices, thereby reducing mounting costs.

[0008]

However, according to the conventional capacitor array 30, as shown in FIG. 5, the external electrodes 35a, 35b, 36a,
6b, the external electrodes 35a, 35b,
It is necessary to form a line connecting the centers of 36a and 36b into a square, and arrange the external electrodes 35a, 35b, 36a and 36b such that one side of the square is separated by a distance that can prevent a short circuit. Therefore, the region 3 where no capacitance is generated in the stacking direction
7 is formed, and there is a problem that high-density mounting due to miniaturization and large capacity becomes difficult.

In recent years, the capacitor array 30 has become thinner and more highly laminated. For this reason, in the margin portion (distance from the internal electrode closest to the main surface to the main surface) of the multilayer body 300, A step occurs on the main surface at the upper part of the region 37 where no capacitance is generated. This step becomes more conspicuous as the region 37 is larger, which causes a problem that peeling and poor adhesion between ceramic layers occur during press molding.

The present invention has been achieved in view of the above-mentioned problems, and an object of the present invention is to provide a capacitor array which realizes high-density mounting by increasing the size and capacity and can reduce a step due to the presence or absence of internal electrodes. .

[0011]

In order to solve the above problems, a capacitor array according to the present invention comprises at least two internal electrodes facing each other between layers of a rectangular laminate formed by laminating a plurality of dielectric layers. The internal electrodes extend from different positions to the end face side of the laminate, and each of the extension portions and a capacitor unit connected to an external electrode at the end face of the laminate, and the capacitor unit Is a capacitor array composed of a plurality of capacitor groups arranged in the direction of lamination of the dielectric layers, wherein the capacitor group is configured by arranging the capacitor units in a staggered manner.

According to the structure of the present invention, since the capacitor units are arranged in a zigzag pattern, the capacitor units can be formed in a dead space where no capacitance is generated between the capacitor units. It can be used effectively to realize high-density mounting.

Further, since the dead space in the region where no capacitance is generated between the respective capacitor units is effectively used, the space in the region where no capacitance is generated between the capacitor units is reduced, and thus the space just above the region is reduced. A step is not generated at the portion of the main surface of the laminate, and the main surface of the flat laminate can be formed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. FIGS. 1A and 1B are diagrams illustrating the configuration of a capacitor array 1 according to the present invention, wherein FIG. 1A is an external perspective view of the capacitor array 1 and FIG. 1B is a plan view thereof. FIG. 2 is a cross-sectional view of the capacitor array 1 of the present invention.
FIG. 2B is a partial cross-sectional view taken along a line A, and FIG. FIG. 3 is a diagram for explaining the structure of the internal electrode in the plan view.

The capacitor array 1 of the present invention includes a laminate 2 in which a plurality of dielectric layers 2a are laminated to form a rectangular block, and a plurality of capacitor units N formed therein.
Consists of This capacitor unit N has an internal electrode 3 and
External electrodes 5 and 6 are formed on one end surface of the laminate 2.

The dielectric layer 2a is made of a dielectric material such as barium titanate or strontium titanate. The internal electrode 3 of the capacitor unit N is formed between the stacked dielectric layers 2a, and is made of a noble metal material such as Pd, Ag-Pd alloy, or N
A base metal such as i or Cu is used, and its structure is such that three electrodes 3a, 3b, and 3c are continuously formed as shown in FIG. In the present invention, three electrodes 3
Although a, 3b, and 3c are continuously formed to face each other, the present invention is not limited to this. At least two electrodes may be formed continuously in the capacitor unit N, and the number of the continuously formed electrodes is not limited. Such internal electrodes 3a, 3b facing each other
However, a capacitance component can be formed by the internal electrodes 3b and 3c facing each other. Each of the internal electrodes 3 is shown in FIG.
As shown in (a) and (b), the laminate 2 extends to the end face side.

The extended portion of the internal electrode 3 is formed, for example, by two internal electrodes 3 sandwiching the central internal electrode 3b among three continuously formed internal electrodes 3a, 3b, 3c.
Both a and 3c are connected to external electrodes 5 (5a, 5b, 5c) formed on one end surface of the multilayer body 2 so as to become common electrodes. Further, the central internal electrode 3b is drawn out to a position different from the external electrode 5 and is connected to the external electrodes 6 (6a, 6b, 6c) similarly formed on one end surface of the multilayer body 2.

In the embodiment of the present invention, the laminate 2
The external electrodes 5 and 6 are formed on one end surface of the multilayer body 2. However, the present invention is not limited to this. The external electrodes 5 and 6 are formed on both end surfaces of the laminate 2 and the internal electrode 3 is extended toward both end surfaces. Alternatively, the internal electrode 3 and the external electrodes 5 and 6 may be connected.

The capacitor unit N is composed of the dielectric layer 2
A capacitor group M is arranged in a staggered manner facing the internal electrodes 3 in the laminating direction a. The plurality of capacitor groups M are formed in a direction perpendicular to the laminating direction of the laminated body 2 on which the dielectric layers 2a are laminated, and are adjacent to each other along the end surface of the laminated body 2. Further, it is preferable that the capacitor groups M are arranged such that the capacitor units N are arranged in a matrix in the laminate 2.

As shown in FIG. 1, the external electrodes 5a, 6
The distance x of a and the distance y of the external electrodes 5c and 6c are formed at different distances, and the distances from the center point of the external electrode 5b to the center points of the external electrodes 5a, 6a, 5c and 6c are equal. To achieve higher density. In the embodiment of the present invention, three continuous internal electrodes 3a to 3c are provided.
Are connected to the external electrodes 5 and 6 as one set, but the present invention is not limited to this.

Next, a method for manufacturing the capacitor array 1 of the present invention will be described. From a slip in which a solvent, a dispersant, a binder, and the like are mixed with the dielectric powder and the sintering aid, a ceramic green sheet to be the dielectric layer 2a is formed by a doctor blade method. For the molding method, another method, a pulling method, a die coater, a gravure roll coater, or the like may be used.

The dielectric layer 2a is provided with an internal electrode 3 (3a to 3a).
c) The metal ink to be used is printed by a screen printing method.
Thereafter, the dielectric layers 2 on which the three types of internal electrodes 3a to 3c are printed are laminated in the order shown in the drawing, and then thermocompression-bonded to obtain the block-shaped laminated body 2.

Next, the block-shaped laminate 2 is heated at 250 ° C.
After calcining in a furnace at 400 ° C to remove the binder component,
The dielectric porcelain and the internal electrodes are simultaneously sintered at a suitable temperature of the ceramic material at 1250 to 1300 ° C. in a proper firing temperature.

Thereafter, in order to electrically connect each capacitor unit to the outside, external electrodes 5 and 6 are formed on the end face of the sintered body by a suitable electrode forming method. The external electrodes 5 and 6 can be formed by applying and baking a conductive paste by a method such as screen printing or by a suitable conductive film forming method such as electroless plating and sputtering.

Next, the laminate is cut into small individual, independent capacitor blocks with a push blade. When the laminate 2 is thick, it is desirable to cut by a dicing method. The cutting step may be performed in the state of a block or immediately after baking. However, by performing after the formation of the external electrodes 5 and 6, the formation of the external electrodes 5 and 6 becomes easy, and the characteristic measurement is performed once. There is an effect that can be done. Thus, the capacitor array 1 as shown in FIG. 1 is obtained.

Thus, according to the capacitor array 1 of the present invention, two internal electrodes 3a and 3b facing each other are provided between the layers of the laminate 2 formed by laminating a plurality of dielectric layers 3a.
When the internal electrodes 3a and 3b are different from each other,
To the end face side, and each extension portion and the laminate 2
The capacitor array 1 includes a capacitor unit N having a pair of external electrodes 5 and 6 connected at the end faces thereof, and the capacitor unit N includes a plurality of capacitor groups M arranged in the stacking direction of the dielectric layers. The capacitor group M has a configuration in which the capacitor units N are arranged in a staggered manner.

According to the configuration of the present invention, since the capacitor units N in the capacitor group M are arranged in a staggered manner, the capacitor units are formed in the dead space of the region 37 where no capacitance is generated between the capacitor units N. Therefore, high-density mounting can be realized by effectively using the dead space.

Further, since the dead space in the region 37 where no capacitance is generated between the capacitor units N is effectively used, the space in the region 37 where no capacitance is generated between the capacitor units N is reduced.
The flat main surface of the multilayer body 2 can be formed without generating a step at the portion of the main surface of the multilayer body 2 directly above the main body.

Here, in the above embodiment, the internal electrodes 3a to 3c formed on the laminate 2 are drawn to the same end face, but the present invention is not limited to this, and the internal electrodes 3a to 3c may be drawn from both sides. With such a structure, the inspection of the connection between the external electrodes 5 and 6 and the circuit board at the time of mounting can be confirmed by applying a probe to the external electrodes 5 and 6 on the opposite side to the mounting surface. It also has the effect of being easier.

It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention.

[0031]

As described above, according to the structure of the present invention,
Two internal electrodes facing each other are provided between layers of the laminated body formed by laminating a plurality of dielectric layers, and the internal electrodes extend from different positions to the end face side of the laminated body, and A capacitor array having a capacitor unit formed with a pair of external electrodes connected to a portion and an end face of the laminate, and wherein the capacitor unit includes a plurality of capacitor groups arranged in the laminating direction of the dielectric layer. Since the capacitor group is formed by arranging the respective capacitor units in a staggered manner, the capacitor units can be formed in a dead space in a region where no capacitance occurs between the capacitor units, thereby effectively reducing the dead space. Utilization can realize high-density mounting.

Further, since the dead space in the area where no capacitance is generated between the capacitor units is effectively used, the space in the area where no capacitance is generated between the capacitor units is reduced, and as a result, the area where the capacitance is not generated is reduced. A step is not generated at a portion of the main surface of the laminate directly above, and the main surface of the flat laminate can be formed.

Further, by pulling out the internal electrodes formed on the laminate from both end faces facing each other, the connection between the external electrodes 5 and 6 and the circuit board is inspected at the time of mounting, and the external electrodes on the side opposite to the mounting surface are probed. Thus, even if the capacitor array is downsized and it is difficult to inspect for a connection failure, the above-described method also has an effect that the inspection can be easily performed.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams illustrating a configuration of a capacitor array according to the present invention. FIG.
(B) is a plan view thereof.

FIG. 2 is a sectional view of the capacitor array of the present invention,
(A) is a partial cross-sectional view taken along line AA, and (b) is a partial cross-sectional view taken along line BB.

FIG. 3 is a diagram illustrating the structure of an internal electrode according to the present invention.

4A and 4B are diagrams illustrating a configuration of a conventional capacitor array, in which FIG. 4A is an external perspective view of the capacitor array, and FIG.
Is a plan view thereof.

FIG. 5 is a diagram illustrating the structure of a conventional internal electrode.

[Explanation of symbols]

 1 Capacitor array 2 Stack 2a Dielectric layer 3 (a to c) Internal electrode 5 External electrode 6・ ・ ・ ・ ・ ・ External electrode N ・ ・ ・ ・ ・ ・ ・ ・ ・ Capacitor unit M ・ ・ ・ ・ ・ ・ ・ ・ ・ Capacitor group

Continued on the front page F term (reference) 5E082 AA01 AB03 BC40 CC03 EE04 EE16 EE23 EE26 EE35 FG06 FG26 FG27 FG54 GG10 GG25 GG26 GG28 JJ03 JJ21 JJ23 LL02 LL03 MM22 MM24 PP08

Claims (1)

[Claims] At least two internal electrodes facing each other are provided between layers of a rectangular laminate formed by laminating a plurality of dielectric layers, and each of the internal electrodes extends from a different position toward an end face of the laminate. And a capacitor unit connected to an external electrode at each of the extending portions and an end face of the laminate,
The capacitor unit is a capacitor array including a plurality of capacitor groups arranged in a direction in which the dielectric layers are stacked, wherein the capacitor group is formed by arranging the capacitor units in a staggered manner. array.