JP2001183428A - Schmidt characteristic inspecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a Schmidt characteristic inspecting device, capable of shortening time for inspecting characteristics of a Schmidt input circuit. SOLUTION: This Schmidt characteristic inspecting device 15 is made up of a DA(digital-to-analog) converter 16, a hysteresis width count circuit, and a Schmidt characteristic output circuit 1A. The converter 16 outputs a voltage which is synchronized with a clock signal 1F. The count circuit is synchronized with the clock signal 1F and counts one level section time of a Schmidt output signal 14. For the period of measuring switching voltages Vth, Vtl, the output circuit 1A is set to output the clock only during a period when an output of the Schmidt input circuit is on one level, and after this period, to output the clock equating to the width of a hysteresis, each time the clock signal 1F is inputted. This enables inspection with digital input and digital output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a Schmitt input circuit and its inspection.

[0002]

2. Description of the Related Art In a semiconductor device, in an input circuit having a single threshold voltage, noise generated in an input signal at the time of switching may cause a malfunction in an internal circuit. In order to prevent this, a Schmitt input circuit is generally used.

Conventionally, in order to inspect a Schmitt input circuit, the inspection is performed after facilitating the inspection so that an input signal from a Schmitt input terminal can be output to an external terminal without passing through an internal circuit. I have.

FIG. 11 shows a semiconductor device having a conventional Schmitt input circuit, and FIG. 12 shows Schmitt characteristics.
This will be described with reference to FIG.

In FIG. 11, a semiconductor device 111 has a Schmitt input terminal 1 connected to an input of a Schmitt input circuit 112.
13 is connected, the output of the Schmitt input circuit 112 is connected to the internal circuit, and the wiring branched at the branch point 115 is connected to the Schmitt output terminal 114 so that the input signal from the Schmitt input terminal 113 passes through the internal circuit. And an inspection circuit configuration capable of outputting to the Schmitt output terminal 114. When the input switching voltage and the hysteresis width test of the Schmitt input circuit 112 are performed, L
The voltage application device 117 of the SI tester 116 is connected to the Schmitt input terminal 113, and the voltage measurement device 118 is connected to the Schmitt output terminal 114.

First, the rising input switching voltage V
When measuring th, as shown in FIG. 12, a voltage that rises stepwise with a constant voltage width from t1 to t8 of the input voltage waveform is sequentially applied from the voltage application device 117 to the Schmitt input terminal 113. The output of 112 is supplied to the voltage measuring device 11 through the Schmitt output terminal 114.
The measurement is performed step by step at step 8, and a Schmitt output waveform 123 is obtained. When the Schmitt output waveform 123 changes from 1 level to 0 level, the voltage generated from the voltage applying device 117 can be confirmed as the rising switching voltage Vth.

When the input switching voltage Vtl is measured, a voltage that decreases stepwise with a constant voltage width from t9 to t15 of the input voltage waveform 121 is sequentially applied from the voltage application device 117 to the Schmitt input terminal 112. The rest is the same as the above-described method, except that the Schmidt output waveform 123
Applying device 11 when voltage changes from 0 level to 1 level
7 can be confirmed as the switching voltage Vtl.

[0008]

According to the above-described conventional test facilitation and test method, when a general-purpose logic tester is used, the voltage generator and the voltage measuring device of the tester cannot be synchronized. In some tests, it takes about 3.5 (ms) to complete the measurement of the output after the application. For example, when the Schmitt characteristic is inspected in steps of 0.05 V from 0 V to 5 V, it takes about 175 (ms) to measure Vth and Vtl, and it is necessary to obtain the hysteresis width (Vth-Vtl) from the measured results. was there. Also, when measuring a semiconductor device equipped with N Schmitt input circuits, N * 350 (ms)
In addition, there is a problem that the inspection time is required and the inspection cost is increased.

Accordingly, the present invention makes it possible to perform a test using a synchronized pattern generator and an expected value comparator mounted on a general-purpose tester, and a Schmitt input test device capable of testing an input switching voltage and a hysteresis width in one cycle. The purpose is to provide.

[0010]

In order to achieve this object, a first Schmidt characteristic inspection apparatus according to the present invention comprises:
(B) an n-bit D / A converter that converts a digital value into an analog value in synchronization with a clock; (b) an AND circuit 1 having the clock signal and the Schmitt output signal as inputs; an output of the AND circuit 1; and the clock signal. UP / DO
A hysteresis width count circuit which is constituted by an n-bit UP / DOWN counter having a WN control signal as an input and counts a clock only when the Schmitt output signal is in one level section, and (c) an output signal group of the n-bit UP / DOWN counter. A NOR circuit having an input, a D flip-flop having an output signal of the NOR circuit and the clock signal as inputs, an output signal of the D flip-flop and an output of the AND circuit 1 as an input, and a characteristic monitor terminal as an output. In the measuring period of the rising switching voltage Vth and the falling switching voltage Vtl, the output of the Schmitt input circuit outputs a clock only during a one-level period, and the clock is input after the period.
A Schmitt characteristic output circuit set to output a clock until the bit UP / DOWN counter becomes zero is provided.

An n-bit DA converter, an n-bit UP /
The number of bits of the DOWN counter is set so that the input switching voltages Vth and Vtl of the Schmitt input circuit can be confirmed in consideration of the input voltage resolution, the number of steps, and the maximum input voltage.

In the Schmidt characteristic test according to the present invention, the output of the n-bit D / A converter is output from a Schmitt input circuit in a semiconductor device which is easily tested so that the output of the Schmitt input circuit can be output to an external terminal without passing through an internal circuit. It is connected to the input circuit, and the output terminal of the Schmitt input circuit is connected to the D circuit 1 during the hysteresis width counting circuit.

From the tester, an n-bit digital signal,
A clock signal, a reset signal, and an UP / DOWN control signal are given, and expected values are compared at a characteristic monitor terminal of a Schmitt characteristic output circuit.

(I) After resetting in the first period, a digital signal is supplied to the n-bit DA converter so as to increase the voltage, and the n-bit UP / DO signal is supplied from the UP / DOWN signal.
The WN counter provides a signal to count up, and the input clock is counted up until the output of the Schmitt input circuit changes only in one level section, that is, from 1 level to 0 level, and the input clock is output from the Schmitt characteristic output circuit. Therefore, it may be compared with the expected value in accordance with the switching voltage Vth standard. Here, one clock corresponds to the resolution of the input voltage.

(II) In order to decrease the voltage in the second period, n
A digital signal is supplied to a bit DA converter and UP /
When a signal that counts down the n-bit UP / DOWN counter is given from the DOWN signal, the Schmitt output becomes 1
The input clock signal is counted down only in the level section, that is, after the change from the 0 level to the 1 level, and the clock is output from the Schmitt characteristic output circuit. Therefore, it may be compared with the expected value in accordance with the switching voltage Vtl standard.

(III) When (I) to (II) are completed, n
The bit UP / DOWN counter has Vth measurement and Vtl
The hysteresis width, which is the difference between the number of clocks input for measurement, is stored. By continuously inputting the clock, the input clock is output from the Schmitt characteristic output circuit until the n-bit UP / DOWN counter becomes zero. Therefore, the input clock may be compared with the expected value in accordance with the hysteresis width standard.

According to the Schmidt characteristic apparatus and the inspection method of the present invention, the input voltage generation circuit and the characteristic measurement circuit of the inspection apparatus are synchronized, and the Schmitt characteristic measurement can be performed by digital input and digital output. The synchronized pattern generator and expected value comparator existing in the general-purpose logic tester can be used, and the input switching levels Vth and Vtl and the hysteresis width characteristic test are continuously performed.
Since the measurement can be performed in cycles, the inspection time can be significantly reduced.

According to a second Schmitt characteristic testing device of the present invention, a hysteresis width counting circuit and a Schmitt characteristic output circuit of the first Schmitt characteristic testing device are mounted between a Schmitt input circuit and a Schmitt output terminal in a semiconductor device. is there. The clock signal and reset signal are obtained from the system clock and system reset of the semiconductor device,
The DOWN signal is characterized by a configuration in which a control circuit including a counter that receives a clock signal as an input in the semiconductor device is added and generated.

With such a configuration, the effect of the first Schmitt characteristic inspection equipment value can be obtained without increasing the number of inspection terminals of the semiconductor device. In addition, incorporation into the semiconductor device enables high-speed inspection without any problems such as erroneous counting due to noise due to impedance mismatch caused by the load and wiring length of the inspection jig outside the semiconductor device, and is more stable. High-speed measurement can be performed.

The measuring method is the same as that of the first Schmidt characteristic inspection apparatus.

The third Schmidt characteristic inspection apparatus according to the present invention generally includes a plurality of Schmitt input circuits. In the first and second Schmitt input circuit inspection devices, a simultaneous measurement circuit comprising an AND circuit, an OR circuit, and a selector circuit is added between the output of each Schmitt input circuit and the hysteresis width count circuit, and the simultaneous measurement circuit Is characterized by switching between an input switching voltage test and a hysteresis width test using a characteristic switching terminal.
It is characterized in that the output voltage of the A-converter is applied at the same time and measurement is performed. When this simultaneous measurement circuit is inserted, the first and second
Due to the characteristics of the Schmitt characteristic inspection apparatus described above, two cycles are required to inspect the input switching voltage and the hysteresis width.
Therefore, when two Schmitt input circuits are mounted on a semiconductor device, the inspection time is twice as long as when one is mounted.
However, when three or more are mounted, the inspection can be performed in two cycles, and the inspection time and inspection cost can be further reduced.

The fourth Schmidt characteristic inspection apparatus according to the present invention is different from the first, second, and third Schmidt characteristic inspection apparatuses in that the DA converter connected to the Schmitt input circuit is structurally changed to a capacitor. This is modified so that a voltage linear in time can be applied to a Schmitt input circuit by using a constant current source built in a logic tester. The first terminal of the capacitor is connected to the input of the Schmitt input circuit, and the second terminal is connected to GND.
Further, a first end of the capacitor is connected to a first end of the relay 1, a second end of the relay 1 is connected to a first end of the relays 2, 3, and a second end of the relays 2, 3 is connected to a constant current of a tester. Source 1 (+
Current) and a constant current source 2 (−current), respectively, and a first end of the capacitor is connected to GND via a relay 4. The control of the relays 2 and 3 is performed by using the UP / DOWN control signal, and the control of the relays 2 and 3 is set to have the opposite polarity, and the control of the relays 1 and 4 is performed by using the reset control signal.
The control of No. 4 is characterized in that it is configured to be set to have the opposite polarity. However, when applying to the second Schmidt characteristic inspection apparatus, it is necessary to add an UP / DOWN control terminal because it does not exist.

Further, the absolute values of the currents of the constant current sources are made equal,
From the clock signal frequency and the time constant of the constant current, it is necessary to set so that the desired voltage can be charged up and down so that the voltage can be applied.

In the Schmidt characteristic inspection according to the present invention, only a method of generating an input voltage different from those of the first and second Schmidt characteristic inspection apparatuses will be described. (I) In the first measurement period, the relay 1 is turned on and the relay 4 is turned off to make the charge of the capacitor zero. (II) In the second measurement period, the relay 2 is turned on so that the constant current source 1 (+ current) outputs, and C is input to the Schmitt input.
, And a switching voltage Vth is measured. (III) In the third measurement period, the constant current source 2 (-current)
The relay 3 is turned on so as to output a voltage, a voltage is input while discharging a capacitor to the Schmitt input, and the switching voltage Vtl is measured.

According to such a configuration, a digital input signal of the DA converter is not required, and the input voltage generating circuit can be simplified.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a Schmidt characteristic inspection apparatus and an inspection method according to the present invention will be specifically described with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing a Schmitt according to a first embodiment of the present invention, in which a semiconductor whose inspection is facilitated so that the output of a Schmitt input circuit can be output in advance to an external terminal without passing through an internal circuit. A characteristic test is performed by connecting to an apparatus.

In FIG. 1, 11 is a semiconductor device, 12 is a Schmitt input circuit, 13 is a Schmitt input terminal, 14
Is a Schmitt output terminal, 15 is a Schmitt characteristic inspection device, 16 is a 3-bit DA converter, 1A is a Schmitt characteristic output circuit, 17 is a hysteresis width count circuit, 1
8, 1D is an AND circuit, 19 is a 3-bit UP / DOWN
Counter (However, U / D counts up when "1".) 1B is NOR circuit, 1C is D flip-flop, 1E is 3-bit digital input signal, 1F is clock signal, 1G is UP / DOWN control signal, 1H is a reset signal,
Reference numeral 1I denotes a characteristic monitor signal. In the semiconductor device 11, the Schmitt input terminal 13 is connected to the input of the Schmitt input circuit 12, the output of the Schmitt input terminal 13 is connected to an internal circuit, and the output of the Schmitt external input terminal 13 Is also connected to the Schmitt output terminal 14, so that a signal input from the Schmitt input terminal 13 can be output to the Schmitt output terminal 14 without passing through an internal circuit.

With respect to the Schmidt characteristic inspection device 15,
The Schmitt input voltage generation source is connected to the clock signal 1F at the clock input of the 3-bit DA converter 16, and receives digital data from the 3-bit digital input signal 1E to convert the analog value synchronized with the clock to the 3-bit DA converter. You can output from. On the Schmitt characteristic measurement side, the hysteresis width count circuit 1
Reference numeral 7 denotes an AN having as inputs the output of the Schmitt input circuit 12 obtained through the Schmitt output terminal 14 and the clock signal 1F.
It is composed of a 3-bit UP / DOWN counter 19 having an output of the D circuit 18, an UP / DOWN control signal 1G and a reset signal 1H as inputs, and the UP / DOWN counter 19 only when the output of the Schmitt input circuit 12 is at one level. Is input with a clock signal. The Schmitt characteristic output circuit 1A has a NOR circuit 1B having a 3-bit output of the 3-bit UP / DOWN counter 19 as an input, an output of the NOR circuit 1B as a D input, a clock signal 1F as a CK input, and a reset signal 1H as a reset signal 1H. D flip-flop 1C with RET input
Having the Q output of the D flip-flop 1C and the output of the AND circuit 18 as inputs, and having the characteristic monitor terminal 1I as the output.
A Schmitt input circuit 12
, And an input clock signal is output from the characteristic monitor terminal 1I in accordance with the output of the 3-bit UP / DOWN counter circuit 19.

That is, according to the configuration described above, analog data synchronized with the digital data input to the 3-bit DA converter input terminal 1E is output, and the clock terminal 1
The Schmitt characteristic can be confirmed by controlling whether or not the signal input from F is output to the characteristic monitor terminal 1I by the Schmitt characteristic output circuit 1A and the hysteresis width count circuit 17. The 3-bit DA converter 16, the hysteresis width count circuit 17, and the Schmitt characteristic output circuit 1A are synchronized by connecting them to the clock terminal 1F.

An inspection method using the Schmidt characteristic inspection apparatus according to the first embodiment will be described with reference to FIGS.

FIG. 2 is a diagram showing a connection at the time of inspection according to the first embodiment, and FIG. 3 is a diagram showing an operation timing at the time of inspection according to the first embodiment. Parts having the same functions as those in FIG. The explanation is omitted.

In FIG. 2, reference numeral 21 denotes a general-purpose tester;
Is a pattern generator and 23 is an expected value comparator. In the general-purpose tester 21, it is general that the pattern generator 22 and the expected value comparator 23 can be synchronized.

In FIG. 3, 31 is the output waveform of the 3-bit DA converter 16, 32 is the output waveform of the Schmitt input circuit 12, 33 is the input data of the 3-bit DA converter 16, 34 is the input waveform of the clock signal 1F, and 35 is the input waveform of the clock signal 1F. Input waveform of reset signal 17, 36 is UP / DOWN control signal 1G
37 is an output waveform of the characteristic monitor signal 1I,
38 is an output waveform of the AND circuit 18, 39 is a 3-bit UP
The count value of the / DOEN counter 19, 3A is the output waveform of the NOR circuit 1B, and 3B is the output waveform of the D flip-flop 1C.

The inspection is performed by the Schmidt characteristic inspection device 15-3.
Bit digital input signal 1E, clock signal 1F, UP
The / DOWN control signal 1G and the reset signal 1H are respectively connected to the pattern generator, and the Schmitt characteristic monitor signal 1I is connected to the expected value comparator 23 for execution.

First, the data of the 3-bit digital input signal 19 is input using a 3-bit DA converter.
2 ³ = 8 and Schmitt input circuit 1
2 which is an input voltage at which switching can be sufficiently confirmed.
Considering that X can be generated, the setting is made as shown in FIG.

The T0 period is a reset period of the Schmitt characteristic inspection device 15, and the count value of the 3-bit UP / DOWN counter 19 is set to "0" by the reset signal 1H, and the D flip-flop 1C is set to the 0 level. . Since the count value b of the 3-bit UP / DOWN counter 19 is "0", the output of the NOR circuit 1B is 1
Level. Therefore, no clock signal is output to the characteristic monitor terminal 1I.

From T1 to T9, the output of the 3-bit DA converter 16 is raised to the MAX voltage in synchronization with the clock to check the switching voltage Vth.

In the T1 period, the UP / DOWN control signal 1G is 1
Since the level is input, the 3-bit UP / DOWN counter 19 functions as an UP counter. Since the output of the Schmitt input circuit is at one level, the clock signal is AND
The D flip-flop 1C latches the output 1 level of the NOR circuit 1B during the period T0 while being output from the circuit 18 and being counted up by the 3-bit UP / DOWN counter 19. Therefore, the output of the AND circuit 1D is output from the AND circuit 1D. Since the signal is output as it is, a clock is output from the characteristic monitor signal 1I.

The same operation as the period T1 is repeated from the period T2 to the period T6. It should be noted that the 3-bit UP / D when the T6 operation is completed
The count value of the OWN counter is “6”.

In the period T7, the output of the Schmitt input circuit 12 becomes 0 level by switching, so that the clock signal 1F is not output from the AND circuit 18 and the 3-bit UP
The / DOWN counter 19 is not counted up. Also,
At the same time, the output of the AND circuit 18 is directly output from the AND circuit 1D. Thus, the switching level Vt
Since h is the moment when the clock signal of the characteristic monitor terminal 1I is stopped, the expected value L may be inserted in the clock input period during which the input analog voltage of the product specification is generated and compared.

In the period from T8 to T9, the same operation as in the period T7 is repeated. It should be noted that 3-bit UP / DO at the completion of the T9 operation
The count value of the WN counter remains "6".

In the period from T10 to T17, the output of the 3-bit DA converter 16 is lowered to 0 V in synchronization with the clock to check the switching voltage Vth.

In the period T10, since the UP / DOWN control signal 1G is input at the 0 level, the 3-bit UP / DOWN counter 19 functions as a DOWN counter. Since the output of the Schmitt input circuit is at the 0 level, the clock signal is A
Not output from ND circuit 18; 3-bit UP / DOWN
The counter 19 does not count down. At the same time, since the AND circuit 1D outputs the output of the AND circuit 18 as it is, no clock is output from the characteristic monitor signal 1I.

The same operation as in the period T10 is repeated until the periods T11 to T13. Note that the count value of the 3-bit UP / DOWN counter at the completion of the T12 operation remains "6".

In the period T14, the output of the Schmitt input circuit 12 becomes 1 level by switching, so that the clock input to the clock signal 1F is output from the AND circuit 18, and the 3-bit UP / DOWN counter 19 outputs DOWN.
N is counted. At the same time, the output signal of the AND circuit 18 is directly output from the AND circuit 1D. As described above, since the switching level Vtl is the moment when the clock output is generated at the characteristic monitor terminal, the expected value H is obtained during the clock input period when the input analog voltage according to the product specification is generated.
, And then compare.

In the period from T15 to T17, the same operation as in the period T14 is repeated. In addition, 3 bits U at the time of completion of T17 operation
The count value of the P / DOWN counter 19 is “2”.

After the period T18, the characteristic of the hysteresis width is confirmed.
It can be confirmed that the count value “2” of the WN counter 19 indicates a hysteresis width which is a voltage corresponding to 2 steps of the 3-bit DA converter 16.

In the period from T18 to T19, the output of the Schmitt input circuit 12 remains at 1 level, so that the clock input to the clock signal 1F is output from the AND circuit 18, and the 3-bit UP / DOWN counter 19 continues the DOWN count. At the same time, the output signal of the AND circuit 18 is directly output from the AND circuit 1D. At T19, since the count value of the 3-bit UP / DOWN counter 19 becomes "0", the output of the NOR circuit 1B becomes 1 level.

In the period T20, the output of the NOR circuit 1B becomes 1 level at T19, so that the D flip-flop 1
C latches and outputs 0 level to the AND circuit 2. As a result, the clock output from the AND circuit 1D is cut off, and the characteristic monitor terminal 1I outputs 0 level. Therefore, since the number of clocks output from the characteristic monitor terminal 1I after the period T18 becomes the hysteresis width, the comparison may be performed by inserting an expected value according to the standard.

It should be noted that the DA converter, U
The P / DOWN counter has three bits for convenience of explanation, and when measuring with high resolution, the number of bits may be further increased.

As described above, according to the Schmidt characteristic inspection apparatus of the first embodiment, since input voltage generation and output voltage measurement can be performed by digital input and digital output, a general-purpose tester and a pattern generator synchronized with each other are compared with expected values. Inspection can be performed using a tester, and the switching levels Vth and Vtl and the hysteresis width characteristic inspection can be measured in one continuous cycle, so that the inspection time can be shortened and the inspection cost can be reduced. For example, 0.05 to 0V to 5V
In the case where all Schmitt characteristics are inspected in increments of V, if the clock frequency is 1 MHz in the conventional inspection circuit / inspection method and 1 MHz in the inspection circuit / inspection method of the first embodiment, the inspection time is reduced by about 1600 times in about 220 μs. still,
Needless to say, testing at the limit frequency at which a general-purpose tester can generate further increases the effect.

(Embodiment 2) FIG. 4 is a diagram showing a Schmidt according to a second embodiment, in which a Schmitt output measuring unit of the Schmidt characteristic inspection apparatus described in the first embodiment is incorporated in a semiconductor device to be measured. Has become. FIG. 5 is a test signal timing chart of the second embodiment.

In FIG. 4, reference numeral 41 denotes a Schmitt characteristic inspection apparatus according to the second embodiment, reference numeral 42 denotes a system clock signal of the semiconductor device, reference numeral 43 denotes a system reset signal of the semiconductor device,
4 is an UP / DOWN control signal generation circuit, 45 is a 4-bit up counter, 46 and 47 are NOR circuits, 48 is an OR circuit,
9 is a T flip-flop, 51 is UP / DOWN in FIG.
Reference numeral 52 denotes an output waveform of the control signal generation circuit, and reference numeral 52 denotes an output waveform of the OR circuit 48. The description of the parts having the same functions as those in FIGS. 1 and 3 is omitted. Hysteresis width measuring circuit 17 and Schmitt characteristic output circuit 1 of Schmitt characteristic inspection device 41
A is configured to interrupt A between the output of the Schmitt input circuit 12 of the semiconductor device 11 to be measured and the Schmitt output terminal 14. The clock signal 1F is connected to the system clock signal 42 of the semiconductor device to obtain a clock, the reset signal 1H is connected to the system reset signal 3 of the semiconductor device under test to obtain a signal, and the UP / DOWN control signal is a clock. It is configured to be generated by the UP / DOWN control signal generation circuit generation 44 based on the clock of the signal 1H. The UP / DOWN control signal generating circuit 44 includes an up counter 45 having a clock signal 1F and a reset signal 1H as inputs, and a NOR circuit 4 having a 4 bit output signal of the up counter 45 as an input.
6, 47, and OR having inputs of NOR circuits 46, 47 as inputs
A circuit 48 and a T flip-flop 49 having an output of the OR circuit 48 as a T input and a reset signal 1H as a RET input, and the Q output of the D flip-flop 47 is a 3-bit UP in the hysteresis width measuring circuit 17. It is connected to the U / D of the / DOWN counter 19.

Here, the up counter 45 is a 3-bit DA
The bit width is selected so that the clock until the output of the converter reaches the MAX voltage value in FIG. 5 can be sufficiently counted, and the output of the NOR circuit 47 has a count output value {(number of clocks up to the MAX value) −1}. NO so that it becomes 0 level at
The output of the R circuit 46 needs to be set so that the 0 level is output when the counter output value is at the "1" level.

Here, UP / DOWN different from the operation of the first embodiment
The operation of the control signal generation circuit 44 will be described with reference to FIG.

The output waveform of the OR circuit 48 becomes one level during the period when the count output value of the 4-bit UP counter 45 is "1" and "9", that is, during the periods T1 and T9. For this reason, the Q inverted output of the T flip-flop changes from 1 level to 0 level after the period T9, and the UP / DOWN switching signal of the first embodiment can be generated from the clock signal 1F.

As described above, according to the Schmitt characteristic inspection apparatus of the second embodiment, the number of external parts for measurement can be reduced as compared with the Schmidt characteristic inspection apparatus of the first embodiment.
In addition, the effect can be obtained without increasing the number of terminals dedicated to inspection of the semiconductor device to be measured. In addition, by incorporating it into a semiconductor device, problems such as incorrect counting of counters due to noise due to impedance mismatch due to load and wiring length during high-speed inspection do not occur, and more stable high-speed measurement is possible. Become.

(Embodiment 3) FIG. 6 is a diagram showing a Schmitt according to Embodiment 3, which is used for measuring a semiconductor device having a plurality of Schmitt input circuits with the Schmidt characteristic inspection apparatus described in Embodiment 1. A simultaneous measurement circuit is added to the Schmitt output measurement device. In FIG. 6, 61 is a simultaneous measurement circuit, 62 is an AND circuit, and 63 is
OR circuits, 64, 65, and 66 are selector circuits, 67 is a characteristic switching terminal, 12a and 12b are Schmitt input circuits,
13a and 13b are Schmitt input terminals, 14a and 14b
Denotes a Schmitt output terminal, and a description of a portion having the same function as that of FIG. 1 will be omitted. The case where three Schmitt input circuits are mounted on the semiconductor device 11 is described as an example. AND circuit 62 and OR circuit 63 of simultaneous measurement circuit 61
The output is connected to the Schmitt input circuit 12, 1
AND circuit 62 having outputs of 2a and 13b as inputs and OR
A selector 64 having the output of the circuit 63 and the AND circuit 62 on the 1-selection side and an output of the OR circuit 63 on the 0-selection side and having the UP / DOWN switching signal as the select signal, and the selector 65 having the 65 selectable output of the AND circuit 62 The selector 65 having the output of the OR circuit 63 as one input on the selection side and having an UP / DOWN switching signal as a select signal, and the selector circuit 64,
And a selector 66 having a characteristic switching signal as a select signal and an output of the selector 66 as an input.
Is connected to the input of the AND circuit 18. 3
The output of the bit DA converter 16 is simultaneously connected to the Schmitt input terminals 13, 13a and 13b.

The measurement operation of the Schmidt characteristic inspection apparatus according to the third embodiment will be described with reference to FIG. Other circuit operations are described in the first embodiment.
Is the same as

FIG. 7 is a diagram showing the operation timing of the simultaneous measurement circuit 61. Reference numerals 71, 72, and 73 denote the Schmitt output waveforms of the respective Schmitt input circuits 12, 12a, and 12b; 74, an output waveform of the selector circuit 64; Is an output waveform of the select circuit 65.

Incidentally, the first Schmitt characteristic inspection device using a simultaneous measurement circuit requires two cycles of inspection in characteristic. This means that when measuring multiple Schmitt input terminals simultaneously, the input switching voltages Vth, Vt
1 is the worst characteristic when the voltage is switched by all of the Schmitt input circuits 71, 72, and 73, and the hysteresis width is best characterized by taking the difference between the voltages when at least one of the Schmitt input circuits 71, 72, and 73 is switched. Is to be worse.

In the first cycle, the characteristic switching signal is set to "0" and the switching voltage is checked.
Therefore, the selector circuit 66 selects and outputs the output of the selector circuit 65.

In the period from T0 to T9, UP / DOWN
Since the switching signal is at one level, the output of the OR circuit 63 is selected. That is, if all the Schmitt input circuits are switched, the output of the OR circuit 63 is inverted. Therefore, the period T8 is the switching voltage Vth.

UP / DOW during the period from T10 to T20
Since the N switching signal is at the 0 level, the output of the AND circuit 62 is selected. That is, when all the Schmitt input circuits switch, the output of the AND circuit 62 is inverted. Therefore, the period T15 is the switching voltage Vtl.

Since the signal output from the selector circuit 66 is input to the AND circuit 18 at any time during the period from T0 to T20, the expected value may be compared at the characteristic monitor terminal 1I. The hysteresis width at this time shows the widest case.

In the second cycle, the characteristic switching signal is set to one level and the hysteresis width is checked. Therefore, the selector circuit 66 selects and outputs the output of the selector circuit 64.

In the period from T0 to T9, UP / DOWN
Since the switching signal is at one level, the output of the AND circuit 62 is selected. That is, if at least one of the Schmitt input circuits switches, the output of the AND circuit 62 is inverted. Therefore, the period T7 is the switching voltage Vth.

UP / DOW during the period from T10 to T20
Since the N switching signal is at the 0 level, the output of the AND circuit 62 is selected. That is, if at least one of the Schmitt input circuits switches, the output of the AND circuit 62 is inverted. Therefore, the period T14 is the switching voltage Vtl.

Since the signal output from the selector circuit 66 is input to the AND circuit 18 at any time during the period T0 to T20, the expected value may be compared at the characteristic monitor terminal 1I. The switching voltages Vth and Vtl at this time show the case where the characteristics are the best.

As described above, even if three Schmitt input circuits are mounted, the worst characteristics of all Schmitt input circuits can be tested in a two-cycle test. The inspection time per circuit is shortened, and the inspection cost can be further reduced. It should be noted that the present invention can be applied to a case where two or more Schmitt input circuits are mounted, but the inspection time for two Schmitt input circuits is twice as long as that for one Schmitt input circuit.

(Embodiment 4) FIG. 8 is a diagram showing a Schmitt according to a fourth embodiment. When a plurality of Schmitt input circuits are mounted in the Schmitt inspection apparatus according to the second embodiment, the simultaneous measurement circuit according to the third embodiment is applied. It was done.

Although the structure is almost the same as that of the Schmidt of the third embodiment, only different parts will be described. Since the operation is the same, the description is omitted.

FIG. 9 shows a case where three input Schmitt circuits are mounted, and reference numeral 81 denotes a characteristic switching terminal.

As shown in the figure, the output terminal for monitoring the Schmitt characteristic becomes only the Schmitt output terminal 14 by adding the simultaneous measurement circuit 61, and the number of the Schmitt test terminals can be reduced by two. However, the characteristic switching signal 8
Since 1 is input from outside the semiconductor device, one dedicated terminal is required. That is, when three Schmitt input circuits are mounted, one inspection terminal can be reduced.

As described above, according to the Schmitt of the fourth embodiment, the present invention can be applied to a semiconductor device equipped with two or more Schmitt circuits, shortens the inspection time, and increases the number of Schmitt input circuits by one or more by three or more. The number of terminals can be reduced one by one.

In the case of a semiconductor device having three or more Schmitt input circuits, the number of terminals does not increase even if external terminals are provided without using the UP / DOWN control circuit 44. One terminal can be deleted every time the number of terminals increases.

(Embodiment 5) FIG. 1 according to Embodiment 1 of the present invention is a diagram showing a semiconductor device to be measured and a Schmitt of Embodiment 5, wherein the voltage source of the Schmitt device is changed from a DA converter to a capacitor. Things.

In FIG. 9, reference numerals 91 and 92 denote constant current sources;
Is a voltage generating circuit, 94, 95, 96, 97 are relays, 9
8 is a capacitor, 99 and 9A are inverter circuits, 9B is a contact, and 9C is the Schmitt inspection apparatus of FIG. 1 which does not include a voltage generator by a DA converter.

The voltage generating circuit 93 connects the constant current sources 91 and 92 of the general-purpose tester 21 to the first ends of the relays 94 and 95, respectively, and connects the second ends of the relays 94 and 95 to each other at the contact 9B. are doing. The control of the relay 94 is connected to the UP / DOWN signal 1G, and the control of the relay 95 is connected to the output of the inverter circuit 99 having the input of the UP / DOWN signal 1G. The contact 9B has a relay 9
7 is connected to the first end, and the second end is connected to the following (1) to
(3) is connected. (1) The second end of the relay 96 whose first end is connected to GND. (2) The second end of the capacitor 98 whose first end is connected to GND. (3) Semiconductor device 1
The reset signal 1H is connected for controlling the Schmitt input terminal 13 and the relay 96, and the output of the inverter circuit 1A having the reset signal 1H as an input is connected for controlling the relay 97.

The relays 95, 96, 97 and 98 are controlled, but are turned on at one level.

The operation of the voltage generating circuit 93 having such a configuration will be described with reference to FIG. FIG. 10 is an operation timing chart of the voltage generation circuit 93. Reference numeral 101 denotes an output voltage value of the capacitor 98, and a description of the same operation as in FIG. 2 described in the first embodiment will be omitted. For comparison of the voltage generation circuits, the DA converter 1 shown in the first embodiment is used.
6 is also shown.

First, the + current is determined in consideration of the capacitance of the capacitor 98 to the constant current source 91 and the time constant determined by the time until the MAX voltage is output. Further, the constant current source 92 needs to set a negative current whose absolute value is equal to that of the constant current source 91. The calculation formula is represented by I = CV / t, where I is the set current value, V is the generated MAX voltage, and C is the capacitance of the capacitor 98. Care must be taken in selecting the capacitance of the capacitor 98 so that the relationship between current and voltage does not become non-linear.

The period T0 is a reset period. Since the reset signal 1G becomes 1 level, the relay 96 is turned on and the relay 97 is turned off, and the electric charge charged in the capacitor 98 is extracted. At this time, since the UP / DOWN control signal 1G is at 1 level, the relay 94 is turned on, but the relay 97 is turned off.
Therefore, a large current does not flow through GND.

In the period T1, the reset signal goes to the 0 level, the relay 97 is turned on, and the relay 96 is turned off. Also, since the UP / DOWN control signal 1G is at one level,
Since the relay 94 is ON and the relay 97 remains OFF, the + constant current is applied to the capacitor 98 from the constant current source 91 and charged up according to the time constant, and rises to the voltage for one step.

The same operation as T1 is repeated from T2 to T9, and the voltage of the capacitor 98 becomes the MAX voltage at T9.

In the period T10, since the UP / DOWN control signal 1G becomes 0 level, the relay 94 is turned off,
Since the relay 97 is turned ON, a constant current is drawn from the constant current source 92 from the capacitor 98 in accordance with the time constant.
It drops by the voltage of the step.

The same operation as T10 is repeated from T11 to T17, and the voltage of the capacitor 98 becomes 0 V at T17.

As described above, when the clock signal 1F rises, the output voltage of the capacitor 98 is changed to the voltage of the first to fourth embodiments.
It can be seen that the output voltage is the same as the output voltage of the DA converter. According to such a configuration, the need for 3-bit digital signal data is eliminated, and simplification of the Schmitt input voltage generation circuit can be realized. Note that the second to fourth embodiments can also be applied. However, in the second and fourth embodiments, U
The P / DOWN signal 1G does not exist outside because it is generated in the semiconductor to be measured. Therefore, the P / DOWN signal 1G can be applied by inputting the same signal from a tester.

[0090]

As described above, according to the Schmitt characteristic inspection apparatus and the inspection method according to the present invention, since the input voltage generation and the Schmitt output measurement at the time of inspection can be performed digitally, synchronization which is a general function of a general-purpose tester can be achieved. The pattern generator and expected value comparator can be used, and the input switching voltage and the inspection time of the hysteresis width can be measured at the same time.
Inspection of a plurality of Schmitt input circuits can be simultaneously measured, so that inspection time can be reduced and inspection cost can be reduced. Further, by incorporating a Schmitt characteristic inspection circuit, measurement accuracy can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram of a Schmidt characteristic inspection apparatus according to a first embodiment.

FIG. 2 is a connection diagram at the time of inspection according to the first embodiment;

FIG. 3 is a diagram showing an operation timing during inspection according to the first embodiment;

FIG. 4 is a diagram of a Schmidt characteristic inspection apparatus according to a second embodiment.

FIG. 5 is a timing chart of a test signal according to the second embodiment.

FIG. 6 is a diagram of a Schmidt characteristic inspection apparatus according to a third embodiment.

FIG. 7 is a diagram showing operation timing of a simultaneous measurement circuit 61 according to a third embodiment.

FIG. 8 is a diagram of a Schmidt characteristic inspection apparatus according to a fourth embodiment.

FIG. 9 is a diagram of a Schmidt characteristic inspection apparatus according to a fifth embodiment.

FIG. 10 is an operation timing chart of the voltage generation circuit 103 according to the fifth embodiment.

FIG. 11 is a diagram showing a semiconductor device having a conventional Schmitt input circuit;

FIG. 12 is a diagram showing Schmidt characteristics

[Explanation of symbols]

11, 111 Semiconductor device 12, 12a, 12b, 112 Schmitt input circuit 13, 13a, 13b, 113 Schmitt input terminal 14, 14a, 14b, 114 Schmitt output terminal 15 Schmitt characteristic inspection circuit 16 3-bit DA converter 17 Hysteresis width count circuit 18, 1D, 62 AND circuit 19 3-bit UP / DOWN counter 1A Schmitt characteristic output circuit 1B, 46, 47 NOR circuit 1C D flip-flop 1E 3-bit digital signal 1F Clock signal 1G UP / DOWN control terminal 1H Reset signal 1I Characteristic monitor Signal 21, 116 General-purpose tester 22, 117 Pattern generator 23, 118 Expected value comparator 31 Output waveform of 3-bit DA converter 16 32 Output waveform of Schmitt input circuit 12 33 Input of 3-bit DA converter 16 Input data 34 Input waveform of clock signal 1F 35 Input waveform of reset signal 17 36 Input waveform of UP / DOWN control signal 1G 37 Output waveform of characteristic monitor signal 38 Output waveform of AND circuit 18 39 Count of 3-bit UP / DOWN counter 19 Value 3A Output waveform of NOR circuit 1B 3B Output waveform of D flip-flop 1C 41 Schmitt characteristic inspection device of Embodiment 2 42 System clock signal of semiconductor device 43 System reset signal of semiconductor device 44 UP / DOWN control signal generation circuit 45 4 bits Up counter 48, 63 OR circuit 49 T flip-flop 51 Output waveform of UP / DOWN control signal generation circuit 52 Output waveform of OR circuit 48 61 Simultaneous measurement circuit 64, 65, 66 Selector circuit 67 Characteristic switching terminal 71 Schmitt input circuit 12 Schmitt output waveform 72 Schmitt input Schmitt output waveform of the circuit 12a 73 Schmitt output waveform of the Schmitt input circuit 12b 74 Output waveform of the selector circuit 64 Output waveform of the select circuit 65 81 Characteristic switching terminals 91, 92 Constant current source 93 Voltage generation circuits 94, 95, 96, 97 Relay 98 Capacitor 99, 9A Inverter circuit 9B, 115 Contact 9C FIG. 1 without voltage source by DA converter
Schmidt inspection device 101 Output voltage value of capacitor 98 121 Input voltage waveform 122 Hysteresis width 123 Schmitt output waveform

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA01 AC03 AE06 AE08 AE14 AG07 AH07 AL11 AL16 5J043 AA09 9A001 BB06 EE05 KK31 LL05

Claims (5)

[Claims] A digital-to-analog converter that converts a digital value into an analog value in synchronization with a clock signal; and a Schmitt output using the clock signal, a Schmitt output signal of the semiconductor device, a reset signal, and an UP-DOWN control terminal as input signals. A hysteresis width count circuit for counting a clock only when the signal is at one level, an output of the hysteresis width count circuit, a clock signal, and a reset signal as input signals; a characteristic monitor terminal as an output; a rising switching voltage Vth and a falling switching voltage During the measurement period of the switching voltage Vtl, the output of the Schmitt input circuit outputs a clock only during the one-level period, and after the period is input, the clock is output until the count value of the hysteresis width count circuit becomes zero. Schmidt Schmidt characteristic test apparatus characterized by comprising a sexual output circuit. 2. The Schmitt characteristic inspection apparatus according to claim 1, wherein the hysteresis width counting circuit and the Schmitt characteristic output circuit are
The semiconductor device is mounted between the output of the Schmitt input circuit and the Schmitt output terminal of the semiconductor device. The clock signal and the reset signal are obtained from the system clock and system reset of the semiconductor device, and the UP / DOWN control signal is generated from the clock signal in the semiconductor device. A Schmidt characteristic inspection device obtained from an UP-DOWN control circuit. 3. A falling switch voltage is measured in a first period of inputting an analog voltage in synchronization with a clock from 0 V to a voltage at which switching of the Schmitt input circuit can be sufficiently confirmed at a constant resolution, and a switching voltage is measured and determined by a characteristic monitor terminal. At this time, the clock is counted up only when the Schmitt input circuit of the semiconductor device outputs "1" to the hysteresis width count circuit, and the analog voltage is synchronized with the clock from the voltage to 0V at the same fixed resolution as in the first period. The rising switching voltage is measured at the characteristic monitor terminal in the input second period, and the clock counts down to the hysteresis width count circuit only when the Schmitt input circuit of the semiconductor device outputs "1". The count value of the middle hysteresis width count circuit corresponds to the hysteresis width. Third inspection method using a semiconductor characteristic test device according to claim 1 or 2, characterized in that to determine the outputs hysteresis width only clock number of the count value of the hysteresis width count circuit in a period for inputting the clock. 4. A simultaneous measurement circuit having a characteristic switching control terminal between outputs of all Schmitt input circuits and a hysteresis width count circuit for measuring a semiconductor device having a plurality of Schmitt input circuits. The Schmidt characteristic inspection device according to claim 1 or 2, wherein 5. A clock connected to a Schmitt input circuit in a Schmitt characteristic test circuit according to claim 1, 2 or 4, using a time constant of a capacitor without using a DA converter for generating an analog voltage. Characteristic inspection device using an analog voltage generation circuit synchronized with the circuit.