JP2001147256A - Semiconductor device and its testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can have its functions tested only by an inexpensive test device without specially using an expensive high- speed digitizer and its testing method. SOLUTION: The semiconductor device 1 is provided with sample holding circuits SH1 to SHN which are connected to an analog output part in parallel so as to hold the signal voltage of the analog signal from an analog circuit 2, timing signal input terminals I1 to IN for inputting timing signals having the timing start times of the voltage signal of the analog signal delayed in order at constant time intervals (t) from outside the semiconductor device to the sample holding circuits, sample holding output terminals A1 to AN for outputting the sample holding circuit output signals to outside the semiconductor device, and an analog output terminal 5 which directly outputs the analog signal to outside of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device whose circuit function is tested by a test apparatus, and a method for measuring an analog signal voltage output from the semiconductor device to test the circuit function of the semiconductor device. More specifically, the present invention relates to a method for testing a settling time of an analog voltage waveform output from a digital / analog converter (DAC).

[0002]

2. Description of the Related Art FIG. 13 is a diagram showing a conventional semiconductor device and a test configuration thereof. In FIG. 13, reference numeral 1 denotes an analog / digital hybrid LSI incorporating a DAC circuit, for example.
Semiconductor device, 2 is a DAC circuit, 3 is a digital circuit for controlling the DAC circuit 2, 4a,..., 4a are digital signal input / output terminals, 5 is an analog output signal A _out of the DAC circuit 2 to the outside. DAC output terminal for output, 6
A high-speed digitizer for digitizing the analog output signal A _out of the C circuit 2 is a test device.

Next, the operation of the configuration shown in FIG. 13 will be described.

First, a test pattern for outputting a desired analog signal to be tested from the DAC circuit 2 is created and input to the semiconductor device 1. D in the semiconductor device 1
The analog output signal A _out output from the AC circuit 2 is digitized by the high-speed digitizer 6, and based on the digitized result, the test device 7 determines whether the function of the DAC circuit 2 is good or not.

For example, when testing the settling time from the zero-scale output to the full-scale output of the DAC circuit 2 in the semiconductor device 1, the DAC circuit 2 changes its analog output signal A _out from zero scale according to a test pattern. Transition to full scale. Test equipment 7
Then, using the digital data of the analog output signal A _out of the DAC circuit 2 digitized by the high-speed digitizer 6, the time required for the output voltage value of the DAC circuit 2 to stabilize within a range from zero scale to a predetermined full scale, That is, the settling time is obtained by calculation, and the obtained settling time is compared with a test standard value to determine whether the DAC circuit 2 is functional.

[0006]

For the measurement of the settling time of the analog output signal A _out outputted from the semiconductor device 1 [0005], requires accurate observation of the output waveform, Therefore, the analog output signal A _out in normal Is digitized at a sampling frequency on the order of GHz.
However, typical test equipment includes such a G
There is no high-speed digitizer on the order of Hz.

Therefore, conventionally, the analog output signal A _out
In order to test the settling time of a semiconductor device and a test device, the expensive G
Unless a high-speed digitizer having a sampling frequency on the order of Hz is prepared, implementation becomes difficult.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-described problem, and separately uses an expensive high-speed digitizer when testing the settling time of an analog signal output from a semiconductor device. It is an object of the present invention to provide a semiconductor device capable of performing a test using only an inexpensive test device without performing the test, and a test method thereof.

[0009]

In order to achieve the above object, a first semiconductor device according to the present invention is a semiconductor device whose circuit function is tested by a test device, wherein the first semiconductor device is synchronized with an edge of a trigger signal. An analog circuit that outputs an analog signal whose signal voltage transitions, and a plurality of analog circuits connected in parallel to an analog output unit of the analog circuit to hold a signal voltage of the analog signal output from the analog circuit. And a plurality of timing signals obtained by sequentially delaying the sampling start time of the signal voltage of the analog signal at a constant time interval t in synchronization with an edge of the trigger signal with respect to the plurality of sample hold circuits. A plurality of timing signal input terminals for inputting signals from outside the semiconductor device; and A plurality of sample-and-hold output terminals for outputting a plurality of sample-and-hold circuit output signals to the outside of the semiconductor device; and an analog for directly outputting the analog signal output from the analog circuit to the outside of the semiconductor device. And an output terminal.

According to the first semiconductor device, the signal voltage value at each time of the analog output signal is changed by the plurality of sample and hold circuits by the plurality of timing signals in which the sampling start time is sequentially delayed at the fixed time interval t. , The respective holding voltage values at that time can be measured by an external voltmeter, and the output waveform can be easily observed. As a result, it is not necessary to separately use an expensive high-speed digitizer having a sampling frequency on the order of GHz unlike the related art, and it is possible to test the settling time of an analog output signal using only an inexpensive test device.

In order to achieve the above object, a second semiconductor device according to the present invention is a semiconductor device whose circuit function is tested by a test device, wherein a signal voltage is synchronized with an edge of a trigger signal. An analog circuit that outputs an analog signal that transitions, and a plurality of sample-and-hold circuits connected in parallel to an analog output unit of the analog circuit to hold a signal voltage of the analog signal output from the analog circuit And a timing for inputting a plurality of timing signals obtained by sequentially delaying a sampling start time of the signal voltage of the analog signal at a predetermined time interval t to the plurality of sample and hold circuits in synchronization with an edge of the trigger signal. A generating circuit, and selecting the plurality of sample-and-hold circuit output signals during a test operation of the semiconductor device. A multiplexer for sequentially outputting the signals and selecting and outputting the analog signal during normal operation of the semiconductor device; and a multiplexer output terminal for outputting an output signal of the multiplexer to the outside of the semiconductor device. It is characterized by.

According to the second semiconductor device, in addition to the functions and effects of the first semiconductor device, a timing generating circuit and a multiplexer are provided in the semiconductor device. The test can be performed with only one multiplexer output terminal that outputs analog signals during normal operation and serially outputs sample-hold circuit output signals during test operation without the need for terminals and many sample-hold output terminals. Therefore, it is not necessary to greatly increase the number of input / output terminals, and the connection with the test equipment is simplified.

In the second semiconductor device, it is preferable that the timing generation circuit has a function of generating the plurality of timing signals with a delay of an arbitrary time T from an edge of the trigger signal.

According to this configuration, the timing at which the observation of the waveform is started can be controlled by adjusting the delay time T, so that the number of sample-and-hold circuits provided in the semiconductor device can be set regardless of the settling time value. It is possible to measure without increasing.

It is preferable that the timing generation circuit has a function of generating the plurality of timing signals in synchronization with the timing at which the analog signal becomes maximum or minimum after the arbitrary time T.

According to this configuration, it is possible to reliably determine whether or not the damped oscillation of the analog output signal to be tested is stable within a predetermined range after the settling time test standard value T. become.

In order to achieve the above object, a first test method of a semiconductor device according to the present invention is a method of inputting a trigger signal to a semiconductor device and outputting an analog signal in synchronization with an edge of the trigger signal. Inputting a first timing signal for causing the voltage to transition and simultaneously starting holding the analog signal in synchronization with the edge of the trigger signal to the semiconductor device, starting holding the signal voltage of the analog signal; The second to Nth timing signals sequentially delayed by a predetermined time interval from the first timing signal are individually input to the semiconductor device, and the analog signals at times corresponding to the second to Nth timing signals are input to the semiconductor device. A plurality of signal voltages of the analog signal are held at a time corresponding to the N-th timing signal, and the plurality of signal voltages of the analog signal are held. Wherein is output from the semiconductor device, a signal output from the semiconductor device and each voltage measurement,
It is characterized in that the quality of the circuit function of the semiconductor device is determined based on the result of the voltage measurement.

According to the first test method, the signal voltage value at each time of the analog output signal is individually held by a plurality of timing signals in which the sampling start time is sequentially delayed at a constant time interval t. Thus, each holding voltage value at that time can be measured by an external voltmeter, and the output waveform can be easily observed. As a result, it is not necessary to separately use an expensive high-speed digitizer having a sampling frequency on the order of GHz unlike the related art, and it is possible to test the settling time of an analog output signal using only an inexpensive test device.

In order to achieve the above object, a second test method for a semiconductor device according to the present invention is directed to a method for inputting a trigger signal to a semiconductor device and outputting the analog signal in synchronization with an edge of the trigger signal. The first signal generated in the semiconductor device that causes the signal voltage of the semiconductor device to transition and simultaneously starts holding the analog signal in synchronization with the edge of the trigger signal
Holding the signal voltage of the analog signal by the timing signal, and sequentially delaying the signal voltage by a predetermined time interval from the first timing signal according to the second to Nth timing signals in the semiconductor device. Wherein the signal voltages of the analog signals are individually held, and the Nth
At a time corresponding to the timing signal, the plurality of signal voltages of the analog signal are held, and the plurality of voltages of the held analog signal are sequentially output from the semiconductor device, and output from the semiconductor device. The voltage of each signal is measured, and the quality of the circuit function of the semiconductor device is determined based on the result of the voltage measurement.

According to the second test method, in addition to the functions and effects of the first semiconductor device, a large number of timing signals are input to the semiconductor device, and a large number of holding voltages of analog signals are output from the semiconductor device. This eliminates the need to output analog signals during normal operation and serially output a large number of holding voltages during test operation. This allows testing to be performed with one output, making it easy to connect semiconductor devices to test equipment. It can be carried out.

In the second test method, the first test method may include:
It is preferable to delay the timing signals from Nth to Nth by an arbitrary time T from the edge of the trigger signal.

According to this method, the timing at which the observation of the waveform is started can be controlled by adjusting the delay time T. Therefore, regardless of the settling time value, the number of sample and hold circuits provided in the semiconductor device can be reduced. It is possible to measure without increasing.

It is preferable that the second to Nth timing signals are generated in synchronization with the timing at which the analog signal becomes maximum or minimum after the arbitrary time T.

According to this method, it is possible to reliably determine whether or not the damped oscillation of the analog output signal to be tested is stable within a predetermined range after the settling time test standard value T. become.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
1 is a block diagram of a semiconductor device and a test device therefor according to an embodiment. As shown in FIG. 1, the semiconductor device 1 according to the present embodiment includes a DAC circuit 2, a digital circuit 3 for controlling the DAC circuit 2, a digital signal input / output terminal 4a,
, 4a, first to Nth sample and hold circuits SH1, SH2, SH3,..., SHN for holding the signal voltage of the analog output signal A _out of the DAC circuit 2, and first to Nth sample and hold circuits For the circuit, the first to Nth
Hold start timing signals S1, S2, S3,.
, IN for supplying SN, and output signals H1, H2, H3,..., H of the first to Nth sample and hold circuits.
N-th output terminal A for outputting N from the semiconductor device 1
, AN, and an output terminal 5 for directly outputting an analog signal A _out of the DAC circuit 2, and are connected to a test apparatus 7 having a timing generation circuit 8.

Next, a test method using the semiconductor device 1 and the test device 7 having the above configurations will be described.

First, in the test apparatus 7, a test pattern for outputting a desired analog signal to be tested from the DAC circuit 2 in the semiconductor device 1 is created, and the digital signal input / output terminals 4a,. Input to the semiconductor device 1 via the The analog output signal A _out output from the DAC circuit 2 in the semiconductor device 1 includes the first to N-th hold start timing signals S1, S2, S3,... Supplied from the timing generation circuit 8 in the test device 7. .., SHN at predetermined time intervals t, the output signals H1, H2,... Of the first to Nth sample and hold circuits SH1, SH2, SH3,. H3,..., HN are the first to Nth
Are output to the outside of the semiconductor device 1 from the output terminals A1, A2, A3,. All sample and hold circuits S
After the signal voltage is held at H1, SH2, SH3,..., SHN, these output terminals A1, A2, A3,.
By measuring the voltage value of AN with the test apparatus 7, the waveform of the analog output signal A _out can be observed.
From this result, the settling time of the analog output signal of the DAC circuit 2 to be tested is obtained by calculation, and the determined settling time is compared with a test standard value to determine whether the function of the DAC circuit 2 is good or bad. .

FIG. 2 is a timing chart of signals of respective parts for explaining the circuit operation in FIG. Here, DA
The measurement of the settling time from the zero-scale output to the full-scale output of the C circuit 2 will be described as an example. FIG.
As shown in (1), the analog output signal A _out of the DAC circuit 2 to be tested changes from a zero-scale value to a full-scale value in synchronization with the sampling clock sclk.

At this time, the data is generated by the test device 7 and
In synchronization with the sampling clock sclk synchronized with the timing at which all digital data input to the semiconductor device 1 via the digital signal input / output terminals 4a,. 1 is held at the timing signal input terminal I
1 to the first sample and hold circuit SH1,
The first sample-and-hold circuit SH1 starts holding the signal voltage of the analog output signal A _out.

Thereafter, the timing signal input terminals I2, I2
,..., IN have second delays of time t
, And the sample hold circuits SH1, SH2, SH3,..., SHN are respectively provided with the hold start timing signals S1, S2, S3,.
.., The signal voltage value of the analog signal A _{out at} the time corresponding to SN is held.

Then, all the sample and hold circuits SH
1 to SHN while the signal voltage is held,
By performing the voltage measurement on all the output terminals A1 to AN, the analog signal waveform A of the DAC circuit 2 is supplied to the test apparatus 7.
_out is taken in, the settling time is obtained by calculation, and the obtained settling time is compared with a test standard value to determine whether the function of the DAC circuit 2 is good or bad.

According to the semiconductor device 1 and the test device 7 according to the present embodiment, since the reciprocal of the delay time t between the hold start timing signals functions as the sampling frequency, high-speed sampling can be easily realized. For example,
Delay time t between each hold start timing signal is 1 ns
When this is set to 1, it means that 1 GHz sampling has been performed. In addition, the entire image of the analog output waveform can be observed in one shot, and can be used for purposes other than measuring the settling time.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
FIG. 3 is a block diagram of a semiconductor device and a test device according to the embodiment. As shown in FIG. 3, the semiconductor device 1 according to the present embodiment excludes the timing signal input terminals I1, I2, I3,. Hold start timing signal S
, SN, DAC output terminal A1, A2, A3,..., AN and DAC output terminal 5 in the first embodiment.
, And a multiplexer for newly selecting one of the output signals H1, H2, H3,..., HN of the first to Nth sample and hold circuits and the analog output signal A _out of the DAC circuit 2. 9, and an output terminal 10 for outputting a signal selected by the multiplexer 9 from the semiconductor device 1 to the outside. The output terminal 10 is connected to the test apparatus 5. In FIG. 3, reset is a reset signal for the timing generation circuit 8, and all the sample-and-hold circuits SH1 to SH are reset by the reset signal reset.
The holding of the signal voltage is released in HN.

FIG. 4 is a diagram showing a configuration of the timing generation circuit 8 in FIG. As shown in FIG. 4, the timing generation circuit 8 in the present embodiment includes a D flip-flop circuit dff in which the data input signal is fixed at a high level.
And delay circuits d1 to dN for delaying a signal by a delay time t
After the output of the D flip-flop dff is reset by the reset signal reset, the first hold start timing signal S1 is output in synchronization with the rising edge of the sampling clock sclk. A hold start timing signal is output with a delay of time t until SN.

FIG. 5 is a timing chart of signals of respective parts for explaining the circuit operation in FIG. In FIG.
reset is a reset signal for the timing generation circuit 8,
SS is a control signal for selecting an input of the multiplexer 9, M is an analog output signal of the multiplexer 9,
During normal operation, the analog output signal A _out of the DAC circuit 2 is output. Here, as in the first embodiment, DA
The measurement of the settling time from the zero-scale output to the full-scale output of the C circuit 2 will be described as an example.

As shown in FIG. 5, first, all the hold start timing signals S1 to S1 are reset by a reset signal reset.
SN becomes low level, and all sample and hold circuits SH
1 to SHN, the signal voltage holding is released.

From this state, the analog output signal A _out of the DAC circuit 2 transits from a zero scale value to a full scale value in synchronization with the sampling clock sclk.

At this time, the first hold start timing signal S1 is also supplied from the timing generation circuit 8 to the first sample hold circuit SH1 in synchronization with the sampling clock sclk to start holding the analog output signal _Aout. I do.

Thereafter, the hold start timing signals S2 to SN delayed by the time t are sequentially supplied to the sample hold circuits SH2 to SHN by the timing generation circuit 8, and the respective hold start timing signals S2 to SN
The signal voltage of the analog signal A _{out at} the time according to SN is held in the sample hold circuits SH2 to SHN.

Then, all the sample and hold circuits SH
After the signal voltage is held in 1 to SHN, the multiplexer 9 is controlled by the multiplexer control signal SS, and the output signal H1 of the first sample and hold circuit SH1 is output as the multiplexer output signal M. The voltage value is measured by the test device 7.

These are sequentially converted to an N-th sample-and-hold circuit S
By measuring the voltage up to the output signal HN of the HN, the analog signal waveform A _out of the DAC circuit 2 can be taken into the test apparatus 7. The settling time is calculated from the measurement result, and the determined settling time is compared with a test standard value to determine whether the function of the DAC circuit 2 is good or not.

As described above, according to the circuit configuration of the semiconductor device 1 of the present embodiment, the conventional problem can be solved without increasing the number of input and output terminals as compared with the conventional semiconductor device. it can.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
3 is a block diagram of a semiconductor device and a test device according to the embodiment. As shown in FIG. 6, in the semiconductor device 1 of the present embodiment, the configuration of the timing generation circuit 8 in the second embodiment is different from that of the second embodiment only in the timing generation circuit control signal en supplied from the newly provided input terminal 11. The first hold start timing signal S1 is generated after being delayed by an arbitrary time T from the sampling clock sclk, and then sequentially delayed by the time t until the Nth hold start timing signal SN. A new function of generating the hold start timing signal.

FIG. 7 is a diagram showing a configuration of the timing generation circuit 8 in FIG. As shown in FIG. 7, the timing generation circuit 8 according to the present embodiment includes delay circuits d1 to dN-1 for delaying a signal by a delay time t. From the hold start timing signal S1 (= en) to the N-th hold start timing signal SN, it has a function of sequentially delaying by time t and outputting.

FIG. 8 is a timing chart of signals of various parts in this embodiment. Here, only the differences from the second embodiment will be described. In the second embodiment, the first hold start timing signal S1
While supplied to the first sample and hold circuit SH1 in synchronization with the rising edge of the sampling clock sclk of the circuit 2, in the present embodiment, as shown in FIG. Hold start timing signal S1 delayed by
Is supplied to the first sample hold circuit SH1, and thereafter, the hold start timing signals S2 to SN sequentially delayed by a fixed time t are supplied to the sample hold circuits SH2 to SHN, respectively.

The semiconductor device according to the second embodiment is
In the configuration, the sampling clock scl of the DAC circuit 2 is used.
First sample at the timing synchronized with the rise of k
Since the hold of the hold circuit SH1 is started, the test
Analog signal A _outSet ring time
Becomes longer, the service provided in the semiconductor device 1 in proportion to it becomes longer.
The required number of sampling hold circuits also increases. However
However, according to the configuration of the semiconductor device of the present embodiment, the delay
Timing that adjusts the time T to start observing the waveform
What settling time value can be controlled
Even a sample and hold circuit provided in a semiconductor device
Measurement can be performed without increasing the number.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.

When the purpose is only to judge whether or not the settling time of the analog output signal is good, the first signal is not necessarily used.
As in the third embodiment, there is no need to sample the analog output signal at a certain time interval t to determine the settling time, and the analog output signal to be tested has the settling time test standard value T _It suffices if it can be confirmed that the stability is maintained within a predetermined range after the _spec . In the present embodiment, as in the first to third embodiments, a test of a settling time from zero-scale output to full-scale output of the DAC will be described as an example. In addition, since the transient phenomenon at this time is generally damped oscillation, in this embodiment, the analog signal voltage value at the test standard value T _spec of the _settling time and the local maximum and local minimum appearing after T _spec The analog signal voltage values are measured at only three points in total, and pass / fail judgment is made based on whether or not all of these points fall within a predetermined range.

FIG. 9 is a block diagram of a semiconductor device and a test device according to the fourth embodiment of the present invention. As shown in FIG. 9, the semiconductor device 1 according to the present embodiment includes a DAC circuit 2 and first to third sample-and-hold circuits SH that hold the signal voltage of the analog output signal A _out of the DAC circuit 2.
1 to SH3 and a timing generation circuit 8 for supplying the first to third hold start timing signals S1 to S3 to the first to third sample and hold circuits, respectively.
And the output signals H of the sample and hold circuits SH1 to SH3.
1 to H3 and a multiplexer 9 for selecting one of the analog output signals A _out of the DAC circuit 2, an output terminal 10 for outputting the output signal M of the multiplexer 9 to the outside of the semiconductor device 1, and a DAC circuit. 2, a digital circuit 3 for controlling the timing generation circuit 8 and the multiplexer 9, and digital signal input / output terminals 4a,.
And a timing generation circuit input terminal 11 for inputting a timing generation circuit control signal en. The timing generation circuit input terminal 11 is connected to the test apparatus 7.

FIG. 10 is a diagram showing a configuration of the timing generation circuit 8 provided in the semiconductor device 1 of FIG. 9. In FIG. 10, reference numeral 8 denotes a timing generation circuit, and 12 denotes a DAC circuit 2.
Differentiating circuit for determining the slope of the analog output signal A _out of the 13 comparison circuit for comparing the output signal A _out 'the reference voltage of the differential circuit 12 (0V), 14 inverted output signal POS of the comparison circuit 13 Inverter, DFF
1 and DFF2 are output signals P of the comparison circuit 13, respectively.
This is a D flip-flop that operates in synchronization with the OS and the rising edge of the output signal NEG of the inverter 14.

FIG. 11 is a timing chart of the signals of the respective parts of FIGS. 9 and 10. Since the operation of the multiplexer 9 is the same as that of the second embodiment when N = 3, it is omitted in FIG.

As shown in FIG. 11, first, the control signal en (= S1) for the timing generation circuit 8 is set to low level,
In addition, the reset signal reset causes the D flip-flop D
FF1 and DFF2 are reset and output signals S2 and S
By setting 3 to the low level, the holding of the signal voltage in all the sample hold circuits SH1 to SH3 is released. In this state, the analog output signal A of the DAC circuit 2 is
_out transitions from zero scale to full scale in synchronization with the rise of the sampling clock sclk.

A _out ′ is a signal obtained by differentiating the analog output signal A _out of the DAC circuit 2 at this time by the differentiating circuit 12 in the timing generating circuit 8.
_At the maximum and minimum points of _out , the output signal A _out ′ of the differentiating circuit 12 becomes 0V (that is, the slope = 0).

POS is a signal obtained by comparing the output signal A _out ′ of the differentiating circuit 12 with the reference voltage 0 V by the comparison circuit 13 in the timing generation circuit 8, and has a high level when A _out ′ is positive. On the other hand, in a negative section, the signal is at a low level.

NEG is an output signal POS of the comparison circuit 13.
Are inverted by the inverter 14. This signal P
The timing of the rising edge in the OS is the timing at which the analog output signal A _out is minimum, and the timing of the rising edge in the signal NEG is the timing at which the analog output signal A _out is maximum.

The control signal e for the timing generation circuit 8
n (= S1) is set to the test standard value T of the settling time from the rising edge of the sampling clock sclk.
Change from low level to high level by delaying _spec . In synchronization with the rising edge of en (= S1) at this time, the first sample-and-hold circuit SH1 starts holding the signal voltage of the analog output signal A _out.

Thereafter, from the timing generation circuit 8, the hold start timing signal S2 is supplied in synchronization with the rising edge of the signal POS, and the hold start timing signal S3 is supplied in synchronization with the rising edge of the signal NEG. As a result, the minimum value and the maximum value that appear for the first time after the test standard value T _spec of the analog output signal A _out are changed to the respective sample-and-hold circuits SH2 and S2.
Held at H3.

After the analog output signals are held in all the sample and hold circuits S1 to S3, the sample and hold circuit output signals H1, H2 and H3 are sequentially output from the multiplexer output terminal 10 as in the second embodiment. And the respective sample-and-hold circuit output signals H1, H
2. The signal voltage of H3 is measured by the test device 7 and the DAC is determined based on whether each measured value is within a predetermined range.
The function of the circuit 2 is determined.

Here, in the process of _obtaining the settling time of the analog output signal _Aout , it is necessary to confirm that the continuous maximum and minimum exist within a predetermined voltage range. In order to detect a pole, at least three signal voltages must be measured. From these, in the first to third embodiments, the number of sample-and-hold circuits provided in the semiconductor device 1 is reduced to three.
Obviously, if the number is less than the set value, the settling time cannot be tested.

However, according to the configuration of the fourth embodiment of the present invention, even when the number of the sample-and-hold circuits provided in the semiconductor device 1 is three, the test of the settling time can be performed. The number of sample-and-hold circuits used can be reduced as compared with the third embodiment.

In the first to third embodiments, all the components other than the test device 7 are configured in the semiconductor device 1. However, components other than the DAC circuit 2 and the digital circuit 3 in the semiconductor device 1 are external to the semiconductor device 1. It is also possible to configure in. Although not described, FIG. 12 is a block diagram of a semiconductor device and a test device in a case where components other than the DAC circuit 2 and the digital circuit 3 in the semiconductor device 1 are configured outside the semiconductor device 1 in the first embodiment. Show.

[0063]

As described above, according to the present invention,
The signal voltage value at each time of the analog output signal
, And each held voltage value at that time can be measured by an external voltmeter, so that the output waveform can be easily observed. As a result, it is possible to test the settling time of the analog output signal using only an inexpensive test device without using an expensive high-speed digitizer as in the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor device and a test device according to a first embodiment of the present invention;

FIG. 2 is a timing chart of signals of respective parts of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a block diagram of a semiconductor device and a test device according to a second embodiment of the present invention;

FIG. 4 is a configuration diagram of a timing generation circuit according to a second embodiment of the present invention;

FIG. 5 is a timing chart of signals of respective parts of the semiconductor device according to the second embodiment of the present invention;

FIG. 6 is a block diagram of a semiconductor device and a test device according to a third embodiment of the present invention;

FIG. 7 is a configuration diagram of a timing generation circuit according to a third embodiment of the present invention.

FIG. 8 is a timing chart of signals of respective parts of the semiconductor device according to the third embodiment of the present invention;

FIG. 9 is a block diagram of a semiconductor device and a test device according to a fourth embodiment of the present invention.

FIG. 10 is a configuration diagram of a timing generation circuit according to a fourth embodiment of the present invention.

FIG. 11 is a timing chart of signals of respective parts of the semiconductor device according to the fourth embodiment of the present invention;

FIG. 12 is a block diagram showing a modification of the semiconductor device and the test device according to the first embodiment of the present invention;

FIG. 13 is a block diagram of a conventional semiconductor device and a test device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 DAC circuit 3 Digital circuit 4a Digital signal input / output terminal 5 DAC output terminal 6 High-speed digitizer 7 Test device 8 Timing generation circuit 9 Multiplexer 10 Multiplexer output terminal 11 Timing generation circuit input terminal 12 Differentiation circuit 13 Comparison circuit 14 Inverter H1 to HN Sample hold circuit output signal S1 to SN Hold start timing signal I1 to IN Timing signal input terminal SH1 to SHN Sample hold circuit A1 to AN Hold voltage output terminal sclk Sampling clock A _out Analog output signal SS Multiplexer control signal M Multiplexer Output signal reset Reset signal for timing generation circuit dff D flip-flop d1 to dN-1 Delay circuit en Control signal for timing generation circuit A _out 'Differentiator output signal POS Comparison output signal NEG Inverter output signal DFF1, DFF2 D flip-flop

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hideki Harayama 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) AK13 AL16 5F038 DF03 DT03 DT15 EZ20 5J022 AB01 AC05 CA10 CE01 CF01 CF08 9A001 BB05 JJ48 KK31 KK54 LL05

Claims (8)

[Claims] 1. A semiconductor device whose circuit function is tested by a test device, comprising: an analog circuit that outputs an analog signal whose signal voltage transits in synchronization with an edge of a trigger signal; and an output from the analog circuit. A plurality of sample-and-hold circuits connected in parallel to an analog output unit of the analog circuit to hold a signal voltage of an analog signal; and a plurality of sample-and-hold circuits, synchronized with an edge of the trigger signal. A plurality of timing signal input terminals for inputting, from the outside of the semiconductor device, a plurality of timing signals obtained by sequentially delaying a sampling start time of the signal voltage of the analog signal at a fixed time interval t; Outputting a plurality of sample and hold circuit output signals output from the circuit to the outside of the semiconductor device A semiconductor device comprising: the plurality of sample and hold the output terminal of order, in that the analog signal outputted from the analog circuit and an analog output terminal for outputting directly to the outside of the semiconductor device. 2. A semiconductor device whose circuit function is tested by a test device, comprising: an analog circuit that outputs an analog signal whose signal voltage transits in synchronization with an edge of a trigger signal; and an output from the analog circuit. A plurality of sample-and-hold circuits connected in parallel to an analog output unit of the analog circuit to hold a signal voltage of an analog signal; and a plurality of sample-and-hold circuits, synchronized with an edge of the trigger signal. A timing generation circuit for inputting a plurality of timing signals obtained by sequentially delaying a sampling start time of the signal voltage of the analog signal at a predetermined time interval t; and outputting the plurality of sample-and-hold circuits during a test operation of the semiconductor device. Signals and sequentially output the signals, respectively, and during normal operation of the semiconductor device, the analog The semiconductor device according to claim a multiplexer for selectively outputting the grayed signal, that the output signal of said multiplexer and a multiplexer output terminal for outputting to the outside of the semiconductor device. 3. The semiconductor device according to claim 2, wherein said timing generation circuit has a function of generating each of said plurality of timing signals with a delay of an arbitrary time T from an edge of said trigger signal. 4. The semiconductor device according to claim 3, wherein the timing generation circuit has a function of generating the plurality of timing signals in synchronization with a timing at which the analog signal becomes maximum or minimum after the arbitrary time T. Test equipment. 5. A trigger signal is input to a semiconductor device, and a signal voltage of an analog signal output in synchronization with an edge of the trigger signal is changed. Simultaneously, the analog signal is held in synchronization with an edge of the trigger signal. Is input to the semiconductor device to start holding the signal voltage of the analog signal, and the second to N-th signals sequentially delayed by a predetermined time interval from the first timing signal are input. The timing signals up to are individually input to the semiconductor device to hold a plurality of signal voltages of the analog signal at times according to the second to Nth timing signals, and the time according to the Nth timing signal In the above, a plurality of signal voltages of the analog signal are held and output from the semiconductor device, and output from the semiconductor device. Signal the voltage measured, based on a result of the voltage measurement, the test method of a semiconductor device and judging the quality of the circuit function of the semiconductor device. 6. A trigger signal is input to a semiconductor device, and a signal voltage of an analog signal output in synchronization with an edge of the trigger signal is changed. Simultaneously, the analog signal is held in synchronization with an edge of the trigger signal. Starting the holding of the signal voltage of the analog signal by a first timing signal generated in the semiconductor device, and sequentially delaying the signal voltage by a predetermined time interval from the first timing signal in the semiconductor device. At times corresponding to the second to Nth timing signals, the signal voltages of the analog signals are individually held. At a time corresponding to the Nth timing signal, a plurality of signal voltages of the analog signals are held. The plurality of voltages of the held analog signal are sequentially output from the semiconductor device, The signals output by each voltage measurement, based on a result of the voltage measurement, the test method of a semiconductor device and judging the quality of the circuit function of the semiconductor device. 7. The method according to claim 6, wherein the first to Nth timing signals are delayed by an arbitrary time T from the edge of the trigger signal. 8. The method according to claim 7, wherein the second to Nth timing signals are generated in synchronization with the timing at which the analog signal becomes maximum or minimum after the arbitrary time T.