JP2001177106A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor device equipped with a transistor in which a channel is formed of thin film polycrystalline silicon to be improved in characteristics. SOLUTION: A semiconductor device is equipped with a transistor composed of a gate electrode 2, a source/drain region 3, and a channel 4. Dangling bonds reside in the source/drain region 3 and the channel 4 formed of thin film polycrystalline silicon to deteriorate the transistor in characteristics. Hydrogen is diffused through a plasma silicon nitride film 16 and introduced to the channel 4 to terminate dangling bonds. Hydrogen cannot pass through the silicon nitride film 6, an opening is provided to the silicon nitride film 6, a metal plug 9 is inserted into the opening, and hydrogen reaches the channel 4 traveling along the interface of the metal plug 9 inserted into the opening. An opening is bored in the silicon nitride film 6 to terminate dangling bonds, by which semiconductor device can be improved in characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor such as a thin film transistor used for a memory cell of a static memory, and more particularly to a technique for improving the characteristics of a transistor having a thin film polycrystalline silicon or the like in a channel portion and its manufacture. It is about the method.

[0002]

2. Description of the Related Art Thin-film polycrystalline silicon transistors (hereinafter, Thin Film Transistors: TF)
T) will be described.
At present, in an SRAM with a high degree of integration, in order to realize a low standby current (or a low standby current) in a small area, a P-channel MOS thin film polycrystalline silicon transistor (hereinafter referred to as a PMO)
There is a demand for a memory cell (hereinafter referred to as a complete CMOS type memory cell) in which S-TFTs are stacked.
For example, a standby current I _sb of a CMOS type low power consumption SRAM using a TFT is determined by an off current I _{off of the} TFT. Taking a 1 Mbit SRAM as an example, I _sb = I
_off × 10 ⁶ , and I _sb = I in a 4 Mbit SRAM
_off × 4 × 10 ⁶ . Thus, the standby current I _sb
Is a value obtained by multiplying the off current of the TFT by the number of memory cells. Therefore, the standby current I _{sb of the} entire SRAM can be significantly reduced by reducing the off current I _{off of} each TFT.

The cause of the off-current of the TFT is considered to be a current generated in a depletion layer between the drain and the channel. This generated current is caused by a trap level at a grain boundary of polycrystalline silicon or a defect in a crystal grain. Therefore, one method of reducing the off-state current of a TFT using polycrystalline silicon is to terminate the dangling bond forming the trap level with hydrogen or the like. Thereby,
The trap level in the band gap is reduced, and the generated current via the trap, that is, the off-state current of the TFT can be reduced. As a method of hydrogenation, a method of depositing a plasma nitride film after forming an aluminum wiring is generally used. However, a method of implanting hydrogen ions or a method of annealing in hydrogen plasma can also obtain the effect of hydrogenation. be able to.
Here, the plasma nitride film is a nitride film formed by a plasma CVD method.

At the same time, in a submicron device, an absolute step can be expected to increase, and the aspect ratio of a contact hole increases, so that a plug technique is indispensable. Therefore, it is necessary to planarize the interlayer film. When wet reflow of an oxide film is used for planarization, a silicon nitride film is provided as an OH-based stopper. Large-capacity SRAM requiring such plug technology
Will be described.

A conventional semiconductor device including a TFT will be described with reference to FIG. FIG. 5 is a cross-sectional view showing a part of the structure of the SRAM including the TFT. In the figure, 1 is a single crystal silicon substrate, 2 is a gate electrode of a TFT used as a load of a memory cell formed of polycrystalline silicon, 2
a is a gate electrode of another TFT used as a load of a memory cell formed of polycrystalline silicon; 3 is a source / drain region of a TFT formed of thin-film polycrystalline silicon; and 4 is a TFT formed of thin-film polycrystalline silicon. 5, a gate oxide film formed by the CVD method, 6 a silicon nitride film, and 7 an aluminum interlayer oxide film.

In order to manufacture this semiconductor device, an N-channel MOS-FET or the like is formed on single crystal silicon 1 and then a gate electrode 2 of a TFT and a gate electrode 2a of the other TFT are formed via an interlayer insulating film. Is formed of polycrystalline silicon.

Next, low pressure CVD (Chemical Vapor Depo)
Silicon oxide film 5 for gate oxide film by sition) method
Is deposited, for example, to a thickness of 40 nm, and then the second-layer polycrystalline silicon 3, 4 serving as an active body is deposited to a thickness of, for example, 30 nm.

In this state, ion implantation for source / drain is performed by photolithography while leaving the resist in the region 4 to be a channel. Thereafter, heat treatment is performed to activate the ionic species and form the source / drain regions 3 to form a TFT.

Further, after an interlayer insulating film is deposited, a silicon nitride film 6 for an OH-based stopper is deposited, for example, to a thickness of 100 nm. After depositing an oxide film 7 to which an impurity is added, a heat treatment is performed in a wet atmosphere to flatten the surface.

Thereafter, although not shown in the figure, a step of opening the planarized oxide film 7 and silicon nitride film 6 and a step of embedding a plug are performed for connection with an aluminum wiring formed in an upper layer. .

Next, the diffusion of hydrogen in a conventional semiconductor device will be described with reference to FIGS. FIG. 6 is a cross-sectional view around a TFT of a conventional semiconductor device. 6 and 7
In the above, 31 is a substrate, 32 is an oxide film, 33 is a TFT gate, 34 is a TFT source, 35 is a TFT drain, 36 is an interlayer nitride film, 37 is a contact hole, 41
Is titanium nitride, 42 is a tungsten plug, 4
Reference numeral 3 denotes an aluminum wiring, 44 denotes a plasma nitride film, 50 denotes a hydrogen diffusion path from the plasma nitride film, and 54 denotes an interlayer film (flat film) flattened by wet reflow. When the plasma nitride film 54 is deposited, the hydrogen in the plasma nitride film reaches the thin film transistor through the diffusion path 50 in FIG. 6 and hydrogenates the TFT.
Can be made.

It is important to planarize the lower film to prevent disconnection of the aluminum wiring. As a planarization method, an oxide film containing a large amount of boron, phosphorus, or the like is deposited at a thickness of about 1 μm, and a temperature of about 700 ° C.
Wet reflow in which heat treatment is performed in water vapor at 00 ° C. to perform reflow has a greater reflow effect than heat treatment in an oxygen O ₂ or nitrogen N ₂ atmosphere. However, when this wet reflow method is applied to the planarization of an interlayer film of an SRAM using a TFT, there is a problem that an OH group contained in an atmosphere at the time of wet reflow oxidizes the TFT and its channel region disappears. There is. Therefore, a nitride film (interlayer nitride film 36), which does not allow OH groups to pass, is sandwiched between the TFT and the oxide film containing a large amount of boron, phosphorus, etc., thereby preventing oxidation of the TFT. This interlayer nitride film 36 is formed at a temperature of about 780 ° C. by a low pressure CVD method (hereinafter, referred to as an LPCVD method). The nitride film formed by the LPCVD method does not contain hydrogen, and has a very small hydrogen diffusion coefficient due to its dense film quality. On the contrary, the plasma nitride film contains a large amount of hydrogen and releases hydrogen in a later heat treatment.

However, the use of the interlayer nitride film 36 causes a new problem. Interlayer nitride film 36
Is not only impervious to OH groups, but also
Since the diffusion of hydrogen therein is also prevented, the effect of hydrogenation on the TFT is remarkably reduced, so that the dangling bond at the channel portion of the TFT cannot be terminated, which causes a problem that the off-current increases. Hydrogen is
Our intensive studies have shown that even an interlayer nitride film of about 200 angstroms hardly permeates.
Hydrogen can reach the TFT only from the hole in the interlayer nitride film 36 that was opened at the same time as opening the contact hole 37 in FIG. 7 (path 50 in FIG. 7).

[0014]

The thin-film polycrystalline silicon used for the channel portion and the source / drain regions of the TFT contains many dangling bonds. By terminating this dangling bond, TF
It is known that among the characteristics of T, off-current characteristics and on-current characteristics are improved. As a method for terminating the dangling bond, after the aluminum wiring step is terminated, there is a case where hydrogen contained in the plasma nitride film used for the passivation film is diffused by about ten and several percent to terminate the dangling bond.

However, since the conventional semiconductor memory device is configured as described above, the PMO used as a load
The structure is such that a silicon nitride film is deposited on the S-TFT. Then, the silicon nitride film having a dense structure hinders the diffusion of hydrogen and prevents the hydrogen from reaching the channel portion of the TFT. Therefore, there is a problem that the dangling bond of the TFT cannot be terminated by hydrogen, and the characteristics of the TFT cannot be improved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. When a interlayer film is flattened by wet reflow, a channel portion of a TFT using a polycrystalline semiconductor is oxidized by an OH group or the like. An object of the present invention is to improve the characteristics of a TFT by diffusing a substance necessary for terminating a dangling bond of a TFT such as hydrogen diffusion without extinguishing, and to provide a method for manufacturing such a TFT. It is an object.

[0017]

Means for Solving the Problems Claim 1 of the present invention
The present invention relates to a semiconductor device, comprising: a transistor using a polycrystalline semiconductor thin film in a channel portion; a silicon nitride film formed above the transistor; and a plasma silicon nitride film formed above the silicon nitride film. Wherein the silicon nitride film is opened.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a transistor using a polycrystalline semiconductor thin film in a channel portion; and forming a silicon nitride film above the transistor. The process of
A step of opening the silicon nitride film; and a step of introducing hydrogen to a channel portion of the transistor through the opening of the silicon nitride film.

According to a third aspect of the present invention,
3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of introducing hydrogen includes a step of forming a plasma silicon nitride film above the silicon nitride film.

According to a fourth aspect of the present invention, there is provided a semiconductor device, a transistor using a polycrystalline semiconductor thin film in a channel portion, a silicon nitride film formed above the transistor, and the silicon nitride film. And a hole having a larger size than the conductor, the conductor including a silicon nitride film and a plasma silicon nitride film formed above the conductor. Having.

According to a fifth aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein a first wiring formed above the silicon nitride film and an opening formed in the silicon nitride film are formed. And a second wiring for electrically connecting the gate electrode of the transistor and the first wiring.

According to a sixth aspect of the present invention, there is provided:
3. The method for manufacturing a semiconductor device according to claim 2, wherein a first wiring electrically connected to a gate electrode of the transistor is provided in an opening formed in the silicon nitride film;
Forming a second wiring above the silicon nitride film, the second wiring being electrically connected to the gate electrode of the transistor via the first wiring.

According to a seventh aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein a first wiring formed above the silicon nitride film and an opening formed in the silicon nitride film are formed. And a second wiring for electrically connecting the source / drain region of the transistor and the first wiring.

According to the eighth aspect of the present invention,
3. The method of manufacturing a semiconductor device according to claim 2, wherein the source of the transistor is located in the opening formed in the silicon nitride film.
Arranging a first wiring connected to the drain region, and forming a second wiring electrically connected to the source / drain region of the transistor via the first wiring above the silicon nitride film; And a step of forming the same.

According to a ninth aspect of the present invention, there is provided a semiconductor device, comprising: a transistor formed above a semiconductor substrate, using a polycrystalline semiconductor thin film for a channel portion; and an opening formed above the transistor. A first wiring formed above the silicon nitride film, a first wiring formed in the opening formed in the silicon nitride film, and electrically connecting the semiconductor substrate and the first wiring. And a plasma silicon nitride film formed above the first and second wires, wherein hydrogen from the plasma silicon nitride film passes through the second wire and It is introduced into the channel portion of the transistor.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
Forming a transistor using a polycrystalline semiconductor thin film in a channel portion; forming a silicon nitride film having an opening above the transistor; and forming the semiconductor in the opening formed in the silicon nitride film. Disposing a first wiring electrically connected to the substrate; and forming a second wiring electrically connected to the semiconductor substrate via the first wiring above the silicon nitride film. Forming, and forming a plasma silicon nitride film over the first and second wirings, wherein hydrogen from the plasma silicon nitride film passes through the first wiring and the channel of the transistor. It is characterized by being introduced into the department.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a transistor having a channel of a polycrystalline semiconductor thin film; and forming a silicon nitride film above the transistor. When,
A step of making at least a part of the silicon nitride film porous; and a step of forming a plasma silicon nitride film above the silicon nitride film.

According to a twelfth aspect of the present invention, there is provided a semiconductor device, comprising: a transistor using a polycrystalline semiconductor thin film in a channel portion; and a first film formed above the transistor and positively charged. A non-charged insulating film formed above the first film, a second film formed above the insulating film and negatively charged, and formed above the second film; A plasma silicon nitride film.

According to a thirteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a transistor having a channel of a polycrystalline semiconductor thin film; and forming a first negatively charged transistor above the transistor. Depositing a film, forming an uncharged insulating film above the first film, depositing a positively charged second film above the insulating film, Forming a plasma silicon nitride film above the film.

A semiconductor device according to claim 14 of the present invention is a transistor using a polycrystalline semiconductor thin film in a channel portion, a silicon nitride film formed on the transistor, and the silicon nitride film. And a plasma silicon nitride film formed above the transistor, wherein the pattern of the silicon nitride film is formed in the same desired shape as the channel pattern of the transistor.

According to a fifteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a polycrystalline semiconductor thin film used for a channel of a transistor, and forming a silicon nitride film on the polycrystalline semiconductor thin film. Depositing, patterning the silicon nitride film into the same desired pattern as the polycrystalline semiconductor thin film, and forming a plasma silicon nitride film above the silicon nitride film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: depositing a thick polycrystalline semiconductor film used for a channel of a transistor; and forming a silicon oxide film containing impurities on the transistor. And reducing the level of the silicon oxide film by performing a heat treatment in an atmosphere of molecules containing OH groups, and reducing the thickness of the polycrystalline semiconductor film by oxidizing the polycrystalline semiconductor film of the transistor. A step of forming a film to a desired thickness; and a step of forming a plasma silicon nitride film above the silicon nitride film.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a sectional view showing a part of a memory cell of the SRAM according to the first embodiment of the present invention. In the figure, 1 is a single-crystal silicon substrate, 2 is a gate electrode of a TFT constituting a load of a memory cell formed of polycrystalline silicon, and 2a is a gate electrode of another TFT constituting a load of the memory cell. 3 is a source / drain region of a TFT formed of thin-film polycrystalline silicon, 4 is a channel of a TFT formed of thin-film polycrystalline silicon, 5 is a gate oxide film formed by CVD, 6 is silicon nitride. Reference numeral 7 denotes an aluminum interlayer oxide film, and reference numeral 8 denotes a hole at an opening of the aluminum interlayer oxide film 7 and the silicon nitride film 6.

Hereinafter, the manufacturing process will be described. After an N-channel MOSFET or the like is formed on single crystal silicon 1, a gate electrode 2 of the TFT and a gate electrode 2a of the other TFT are formed of polycrystalline silicon via an interlayer insulating film.

Next, low pressure CVD (Chemical Vapor Depos)
silicon oxide film 5 for the gate oxide film by the
Is deposited, for example, to a thickness of 40 nm, and then the second-layer polycrystalline silicon 3, 4 serving as an active body is deposited to a thickness of, for example, 30 nm.

In this state, source / drain ion implantation is performed by photolithography while leaving the resist in the region 4 to be a channel. Thereafter, heat treatment is performed to activate the ionic species and form the source / drain regions 3 to form a TFT.

Further, after an interlayer insulating film is deposited, a silicon nitride film 6 for an OH-based stopper is deposited to a thickness of 100 nm by, for example, LPCVD. After depositing an oxide film 7 to which an impurity is added, a heat treatment is performed in a wet atmosphere to flatten the surface.

Here, the silicon nitride film 6 and the oxide film 7 above the contact portion between the gate electrode 2a and the thin polycrystalline silicon 3 are opened, and the silicon nitride film 6 for the OH-based stopper is opened.
Open hole 8 at Generally, the position where the hole 8 is opened is in the vicinity of the TFT where hydrogen can be introduced into the channel portion 4 of the TFT and at a position where the base and the upper layer are not adversely affected. In consideration of introducing hydrogen into the channel portion 4 of the TFT, it is desirable that the silicon nitride film 6 be opened directly above the channel portion 4. However, when the silicon nitride film 6 is opened by etching, it is difficult to control the etching depth, and the possibility of damaging the channel portion 4 of the TFT is large. It is desirable to open the silicon nitride film 6. By doing so, the gate electrode 2a and the thin-film polycrystalline silicon 3 can also serve as an etching stopper, which facilitates the manufacture of the device.

Thereafter, although not shown in the figure, the step of opening the flattened oxide film 7 and the silicon nitride film 6 and the step of embedding plugs are combined for flattening or an aluminum wiring formed on an upper layer. Done for connection with. At this time, a tungsten plug is formed in the hole 8. Finally, a passivation film is formed on these, for example, with a plasma nitride film. When the passivation film is formed, the substrate temperature is about 350 ° C., and the heat causes hydrogen contained in the passivation film to diffuse, pass through the hole 8, and pass through the interface of the tungsten plug formed in the hole 8. The channel portion 4 and the source / drain region 3 of the TFT. As a result, dangling bonds included in the channel portion 4 and the source / drain region 3 of the TFT are terminated, and
FT characteristics can be improved.

In the above embodiment, a tungsten plug is buried after opening the hole 8, but an oxide film may be buried in the hole 8 after opening the hole 8 for planarization.

Embodiment 2 FIG. 2 is a sectional view showing a part of the memory cell of the SRAM according to the second embodiment of the present invention. In FIG. 2, 9 is a metal plug, 10 is a silicon nitride film 6, an aluminum interlayer oxide film 7, and a hole opened in the thin-film polycrystalline silicon 3, and the same reference numerals as those in FIG. Embodiment 1 shown in FIG. 1 and FIG.
The second embodiment is different from the second embodiment in the following points.

First, in the semiconductor device shown in FIG. 1, after a contact pattern is formed by photolithography, a gate oxide film 5 between the gate electrode 2a and the source / drain region 3 is opened by etching to make contact. I was taking.

On the other hand, the semiconductor device in FIG.
The step of forming a contact between the gate electrode 2a and the source / drain region 3 is eliminated, and the aluminum interlayer oxide film 7 is removed.
(FIG. 2A), a hole 10 is formed, a metal plug 9 is buried, and a contact is made between the gate electrode 2a and the source / drain region 3 (FIG. 2A).
(B)).

As described above, according to the present embodiment, the opening of the silicon nitride film 6 and the connection between the gate electrode 2a and the source / drain region 3 can be made simultaneously.

In this embodiment, as in the first embodiment, the dangling bond between the channel portion 4 and the source / drain region 3 of the TFT is formed using the hole 10 as the opening of the silicon nitride film 6. The termination can be performed, and the characteristics of the TFT can be improved.

In this embodiment, a metal is used as a plug material to be buried in the hole 10. However, any other material such as polycrystalline silicon doped with impurities may be used as long as the material can make ohmic connection. It has the same effect as.

Embodiment 3 FIG. 3 is a cross-sectional view showing a part of a memory cell of an SRAM with multilayer wiring according to a third embodiment of the present invention. In the figure, reference numeral 11 denotes a first-layer aluminum wiring, 12 denotes a metal plug for connecting a device formed on the single-crystal silicon substrate 1 to the first-layer aluminum wiring 11, 13 denotes a metal plug, and 14 denotes a first layer. An interlayer insulating film formed between the aluminum wiring and the second level aluminum wiring, 15
Is a second layer aluminum pad formed on the interlayer insulating film 14, 16 is a plasma silicon nitride film, 18 is a dummy through hole provided in the interlayer insulating film 14, and has the same reference numerals as those in FIG. Indicates the same contents as in FIG.

As described above, as the number of wirings increases, the distance between the channel portion of the TFT and the plasma silicon nitride film 16 serving as a passivation film increases, and diffusion of hydrogen from the plasma silicon nitride film 16 becomes more difficult. become. Therefore, by providing a dummy through hole and diffusing hydrogen therefrom, the dangling bond of the thin-film polycrystalline silicon can be easily terminated.

Hereinafter, the manufacturing process will be described. FIG.
After the step shown in (b) is completed, an interlayer film 7 is further formed to cover the upper portion of the metal plug 9. Next, the aluminum contact portion is opened by photolithography and anisotropic etching, and the metal plug 12 is embedded. After that, the first layer aluminum wiring 11 is formed by patterning.

Next, an interlayer insulating film 14 is deposited between the first layer aluminum wiring and the second layer aluminum wiring. Thereafter, a dummy through hole 18 is formed in the interlayer insulating film 14, and the metal plug 13 is embedded in the through hole 18. Next, the through hole 18 is capped using a second layer aluminum pad. Since hydrogen is diffused from this through hole 18,
Hydrogen efficiently reaches the channel portion 4 of the TFT, and the dangling bond can be terminated. The through holes 18 need to be provided so as not to hinder the second level aluminum wiring.

In this embodiment, the through hole 18 formed between the first-layer aluminum wiring and the second-layer aluminum wiring is filled with the metal plug 13. Through hole 18 with only layer aluminum pad 15
May be filled.

Embodiment 4 FIG. FIG. 4 is a cross-sectional view showing a part of a memory cell of an SRAM with multilayer wiring according to a fourth embodiment of the present invention. In the figure, reference numeral 17 denotes a second layer aluminum wiring, and the same reference numerals as those in FIG. 3 indicate the same contents.
The semiconductor memory device shown in FIG. 3 is characterized in that the dummy through hole 18 is formed right above the metal plug 12, but the semiconductor memory device shown in the present embodiment is formed of thin-film polycrystalline silicon. It is formed on a metal plug 9 formed to connect the source / drain region 3 of the TFT and the gate electrode 2a formed of polycrystalline silicon.
Since hydrogen is diffused from this through hole 18, TF
Hydrogen efficiently reaches the channel portion 4 of T, and the dangling bond can be terminated. The through holes 18 need to be provided so as not to hinder the second level aluminum wiring.

In the present embodiment, the through hole 1
Although an example is shown in which nothing is buried inside 8, another material other than the oxide film may be buried, and for example, a metal plug may be buried so as not to disturb the second-layer aluminum wiring.

In the first to fourth embodiments, hydrogen is used as a substance that terminates a dangling bond. However, another substance may be used as long as it can terminate a dangling bond. The same effects as those of the above-described embodiment can be obtained.

Embodiment 5 8 to 15 are sectional views showing Embodiment 5 of the present invention in accordance with a process flow. In the figure, 31 is an insulating film, 33 is a TFT gate, 34 is a TFT source, 35 is a TFT drain,
36 is an interlayer nitride film, 37 is a contact hole, 38a,
38b is a portion from which the nitride film has been removed by wet etching, 39 is an oxide film formed by the CVD method, 40
a, 40b are oxide films to be removed by dry etching,
41 is a titanium nitride, 42 is a tungsten plug, 43 is an aluminum wiring, 44 is a plasma nitride film, 50 is a hydrogen diffusion path from the plasma nitride film, and 54 is an interlayer film planarized by wet reflow.

FIG. 8 shows that a TFT having a gate 33, a source 34, and a drain 35 is formed in an oxide film 32 on a substrate 31, and an oxide film 32, an interlayer nitride film 36, an oxide containing a large amount of boron, phosphorus and the like from below. FIG. 9 is a view showing a state in which the films are formed in the order of oxide films 54 which are planarized by a wet reflow method.

FIG. 9 is a view showing a state in which the contact hole 37 has been opened by the usual photolithography and etching.

Here, hot phosphoric acid (temperature about 170 ° C.) is heated to about 5
Soak for hours. FIG. 10 shows a state in which only the interlayer nitride film 36 is etched by about 2 μm in the lateral direction by hot phosphoric acid. More hydrogen in the plasma nitride film reaches the thin film transistor through the removed portions 38a and 38b of the interlayer nitride film 36.

The off current I _{off of the} TFT is determined by the electric field E applied to the drain injection end and the number N of dangling bonds of polysilicon contained therein, as shown in Expression 1.

[0060]

(Equation 1)

Therefore, if the dangling bond at the drain end is sufficiently terminated, the off-state current can be reduced to almost the same level as that of the TFT of the conventional semiconductor device having no interlayer nitride film and sufficiently hydrogenated (FIG. 6). Can be reduced.
The amount of wet etching of the interlayer nitride film 36 by hot phosphoric acid may be set to be equal to or longer than the distance between the contact hole 37 and the drain injection end 58 of the TFT.

FIG. 11 is a view showing that an oxide film 39 is deposited by a CVD method after removing a part of the nitride film with hot phosphoric acid. Since the oxide film 39 formed by the CVD method has good coverage, it can also be deposited in gaps such as 38a and 38b, and can fill the gaps. This step is necessary to improve the adhesion of titanium at the portions 38a and 38b from which the nitride film has been removed when titanium is sputtered later. Therefore, the interlayer nitride film 36 is thin,
When there is no problem with the adhesion of titanium, FIGS.
Can be omitted.

FIG. 12 is a view showing a process of opening a portion 40b to be a contact hole 37 by oxide film dry etching. Instead of the oxide film 39, another film having good coverage may be used. For example, polysilicon formed by a CVD method can be used. In this case, since the polysilicon is conductive, the contact hole 37 is formed.
A contact can be made without opening the portion 40b, which is to be used, and the contact resistance can be reduced as compared with the case where the oxide film 39 formed by the CVD method is used.
However, when a conductive film is used for embedding, it is necessary to prevent the aluminum wiring from short-circuiting at a portion 40a of the film used for embedding in FIG. For this purpose, a process of removing the portion 40a in advance or cutting off the portion 40a simultaneously with patterning of the aluminum wiring may be added.

FIG. 13 is a view showing a state where titanium nitride 41 is formed by sputtering titanium and annealing in a nitrogen atmosphere. FIG. 14 is a view showing a state where the tungsten plug 42 is formed. FIG. 15 shows a state where an aluminum wiring 43 is formed and a plasma nitride film 44 is deposited. Compared to the conventional semiconductor device shown in FIG.
More hydrogen in the plasma nitride film 44 is transferred to the diffusion layer path 5.
Since it diffuses through 0 and hydrogenates the TFT, a TFT with low off-state current can be formed. The same effect can be obtained by immersing in a plasma hydrogen atmosphere instead of depositing the plasma nitride film 44. The titanium nitride 41 and the tungsten plug 42 may not be provided, and the same effects as in the present embodiment can be obtained.

Embodiment 6 FIG. 16 and 17 are cross-sectional views showing a semiconductor device according to the sixth embodiment in accordance with a process flow. In the figure, 31 is a substrate, 32 is an oxide film, 33 is a TFT gate, 34 is a TFT source, 3
5 is a drain of the TFT, 36 is an interlayer nitride film, 44 is a plasma nitride film, 48 is a porous nitride film by silicon implantation, 49 is silicon implantation, 50 is a hydrogen diffusion path from the plasma nitride film, and 54 is a wet reflow. This is a flattened flat film.

FIG. 16 shows the film 5 formed by wet reflow.
FIG. 4 is a diagram showing a state where the flattening of No. 4 is completed and silicon implantation 49 is performed. Since silicon implantation is performed to increase the lattice spacing by increasing the proportion of silicon in the interlayer nitride film 36 and to make the interlayer nitride film 36 porous, the silicon implantation is performed.
So that the injection peak is at the depth of. For example, depth 4
When the interlayer nitride film 36 is located at a position of 000 angstroms, the implantation is performed at an energy of about 200 keV.
The injection amount is set to 10 ¹⁵ / cm ² or more. The purpose of this silicon implantation is to increase the diffusion coefficient of hydrogen in the film and to make the interlayer nitride film 36 porous so that it can easily permeate from top to bottom. Ions or other ions may be implanted.

FIG. 17 is a view showing a state where the plasma nitride film 44 is deposited. Contact holes for simplicity,
Aluminum wiring, tungsten plug, etc. are omitted. Since the interlayer nitride film 48 is in a porous state by silicon implantation, hydrogen easily permeates in the plasma nitride film 48, and hydrogen reaches the TFT through the diffusion path 50, and the TFT is hydrogenated. Can be made.

In the fifth and sixth embodiments, after the planarization is performed using the interlayer nitride film 36, the diffusion path 50 of hydrogen from the plasma nitride film is secured by wet etching and silicon implantation. Embodiments 7 and 8 described below are characterized in that OH groups during planarization are stopped using a film other than the interlayer nitride film 36.

Embodiment 7 FIG. 18 is a cross-sectional view showing one of the manufacturing steps of the semiconductor device according to the seventh embodiment.
In FIG. 18, 31 is a substrate, 32a and 32b are insulating films,
33 is a gate of the TFT, 34 is a source of the TFT, 35 is a drain of the TFT, 46 is an OH group, 54 is a flat film planarized by wet reflow, 55 is a region into which a large amount of N-type impurities are implanted, and 56 is a P film. A region 57 containing a large amount of type impurities is an electric field formed by the electric charges in the region 55 and the region 56.

FIG. 18 shows a TFT gate 33 and a source 3
4. After the formation of the drain 35, an interlayer nitride film 32a is deposited to a thickness of about 3000 angstroms, and boron is implanted into the surface thereof to form a region 56 containing a large amount of P-type impurities. This implantation needs to be performed so as not to reach the TFT. Next, an interlayer nitride film 32b is deposited to a thickness of 1000 angstroms, and phosphorus is implanted into the surface thereof to form an
5 is formed. An electric field 57 is generated between the two layers by the impurities contained in the two layers. This electric field prevents OH groups from reaching the thin film transistor during wet reflow.

Assuming that the two layers 55 and 56 are parallel plate capacitors, the acceleration voltage V (V) equal to the energy of the OH group that can be captured between the electrodes is expressed by the following equation (2).

[0072]

(Equation 2)

Here, q is the elementary charge (C), N is the amount of impurity implanted (/ cm ² ), and C is the capacitance (F) of the capacitor.
There is.

[0074]

(Equation 3)

Here, K ₀ is the relative dielectric constant of the oxide film, ε ₀ is the dielectric constant of vacuum (F / cm), and d (cm) is the distance between the layers 55 and 56. Assuming that the implantation amount of the impurities into the two layers 55 and 56 is both 6 × 10 ¹⁴ / cm ² , it can be seen from Equations 2 and 3 that the OH group having an energy of about 1 keV is decelerated and captured in this film. it can. By adjusting the injection amount of the two layers, the electric field 57 can be formed only between the layers 55 and 56, and the electric field does not leak to other parts and does not affect the operation of the TFT.

As described above, the interlayer can be flattened without oxidizing the TFT as a result. That is, an oxide film 2 containing a large amount of boron and phosphorus for planarization is formed thereon.
4 and wet reflow is performed, the OH groups contained in the atmosphere at the time of wet reflow pass through the path 46 to planarize the oxide film 54, reach the region formed by the layers 55 and 56, and transfer energy there. Loses and does not enter the TFT area. Here, the layers 55 and 5 containing these two impurities are used.
Although 6 is formed by implantation, an oxide film containing impurities may be deposited in advance. Polysilicon containing impurities may be deposited, but it is necessary to oxidize the side wall so as not to cause a short circuit when the contact hole is opened, or to accumulate electric charge by insulating the side wall from others.

Since the interlayer nitride film is not used, the thin film transistor can be hydrogenated by hydrogen in the plasma nitride film during the deposition of the plasma nitride film after the formation of the contact hole, the tungsten plug, and the aluminum wiring. Contrary to the OH group, the hydrogen ions H ⁺ are accelerated by the electric field 57, so that the hydrogenation effect is obtained.

That is, if this structure is used, the flattening can be performed by wet reflow without reducing the effect of hydrogenation of the TFT and without oxidizing the TFT.

In the present embodiment, another film is used in place of the interlayer nitride film to realize flattening by wet reflow without reducing the effect of hydrogenation of the TFT. In the following eighth and ninth embodiments, hydrogen is interposed in advance below the interlayer nitride film by utilizing the property of the interlayer nitride film that does not pass hydrogen.

Embodiment 8 FIG. FIG. 19 is a cross-sectional view showing one of the manufacturing steps of the semiconductor device according to the eighth embodiment.
In FIG. 19, 31 is a substrate, 32 is an insulating film, 33 is TF
The gate of T, 34 is the source of the TFT, 35 is the drain of the TFT, 36 is the interlayer nitride film, and 47 is the hydrogen implantation.

FIG. 19 shows that after forming the TFT, the oxide film 32,
The interlayer nitride film 36 has been deposited in this order. Here between layers
Hydrogen is implanted into the TFT below the nitride film 36 (implanted amount 10¹⁶/
cm ^Two) To hydrogenate the TFT.

Thereafter, an oxide film containing a large amount of boron and phosphorus is deposited and flattened by wet reflow. Normally, hydrogen as a dangling bond terminator is 8
If a heat treatment at a temperature of from 00 ° C. to 900 ° C. is applied, it diffuses out and loses its function. However, since the interlayer nitride film 36 has an effect of suppressing the diffusion of hydrogen, hydrogen diffused out of polysilicon during wet reflow (heat treatment at 800 ° C. to 900 ° C.) moves out of the interlayer nitride film 36. Does not spread. Then, in the heat treatment (about 400 ° C.) after the formation of the aluminum wiring, the aluminum is again diffused into the polysilicon channel of the TFT and hydrogenated (rehydrogenation). Since the requirement for the interlayer nitride film 36 in this structure is that it does not allow hydrogen to pass through, contrary to the fifth and sixth embodiments, it is desirable that the interlayer nitride film 36 be deposited as thick as about several thousand angstroms.

Using this structure, TF
The effect of hydrogenation of T can be obtained, and the TFT can be flattened by wet reflow without oxidation.

Embodiment 9 FIG. FIG. 20 is a cross-sectional view showing one of the manufacturing steps of the semiconductor device according to the ninth embodiment.
20, 31 is a substrate, 32 is an insulating film, 33 is TF
T gate, 34 a TFT source, 35 a TFT drain, 36 an interlayer nitride film, 44 a plasma nitride film, 5
Numeral 0 denotes a hydrogen diffusion path from the plasma nitride film.

FIG. 20 shows a TFT (gate 33, source 3).
4, drain 35), a plasma nitride film 44 is deposited for about 5000 angstroms, and then an interlayer nitride film 3 is formed.
FIG. 6 is a diagram showing that No. 6 is deposited at 1000 Å. During the deposition of the plasma nitride film 44, the hydrogenation of the TFT is performed. As shown in the diffusion path 50, there is nothing blocking the hydrogen between the plasma nitride film 44 and the TFT.
The TFT is fully hydrogenated.

Thereafter, an oxide film containing a large amount of boron and phosphorus is deposited and flattened by wet reflow. Since the interlayer nitride film 36 has an effect of suppressing the diffusion of hydrogen, the hydrogen diffused out of the polysilicon during the wet reflow (heat treatment at 800 ° C. to 900 ° C.)
It does not diffuse out of 6. Then, in the heat treatment (about 400 ° C.) after the formation of the aluminum wiring, the aluminum is again diffused into the polysilicon channel of the TFT and hydrogenated (rehydrogenation).

As in the eighth embodiment, by using this structure, the effect of hydrogenation of the TFT can be obtained by rehydrogenation, and the TFT can be flattened by wet reflow without oxidation.

Embodiments 5 to 9 described above are
The first is that the TFT will not be oxidized during wet reflow.
The present invention is based on the idea that flattening and hydrogenation are performed. The tenth embodiment described below is characterized in that the TFT is formed thick in advance in anticipation of oxidation of the TFT during wet reflow.

Embodiment 10 FIG. FIGS. 21 and 22 are cross-sectional views illustrating one of the manufacturing steps of the semiconductor device according to the tenth embodiment. In the figure, 31 is a substrate, 32 is an insulating film,
33 is a gate of the TFT, 34 is a source of the TFT, 35 is a drain of the TFT, 46 is an OH group, 51 is a polysilicon thick film in which channel polysilicon is formed thick in advance, and 52 is oxidized by wet reflow to be thinned. A polysilicon thin film, 53 is an interlayer film having many steps, and 54 is an interlayer film planarized by wet reflow.

FIG. 21 is a view showing that a TFT in which polysilicon 51 is deposited thick (400 Å) in advance is formed, and then an oxide film 53 containing a large amount of boron and phosphorus is deposited and flattened by a wet reflow method. It is. In this structure, the TFT is oxidized by the OH group because there is no interlayer nitride film on the TFT. The channel of the thinned transistor is formed thicker by that amount.

FIG. 23 shows the remaining polysilicon film thickness when an oxide film containing a large amount of boron and phosphorus is deposited on a 400-Å-thick polysilicon film immediately after its formation at 10,000 Å and wet reflowed at 820 ° C. It is a figure which shows the relationship of a wet reflow time. As a result of our intensive studies, in the time domain of less than one hour, the polysilicon film thickness decreases almost linearly, and the uniformity of the polysilicon film on the wafer surface is extremely high and is less than ± 5%. Has been verified. According to FIG. 23, it can be seen that the 400 angstrom thick polysilicon is reduced to about 150 angstrom by 820 ° C. wet reflow for 60/60.

FIG. 22 shows that the interlayer film 53 is flattened by performing a wet reflow process at 820 ° C. for 60 minutes.
This is where the polysilicon 51 has been thinned and the polysilicon 52 has been formed. As described above, the thickness of the polysilicon 52 of this TFT is about 150 Å. In this structure, the interlayer nitride film is not used, so that hydrogen in the plasma nitride film can freely diffuse into the TFT during the deposition of the plasma nitride film.
Off current can be reduced. If the uniformity of the oxidation of polysilicon by wet reflow in the wafer surface is very good, the thickness of the polysilicon is set to be thin (for example, 350 Å) in the channel portion to be deposited first, thereby further reducing the thickness (about 100 Å). Angstrom), and the off-state current of the TFT can be further reduced.

Oxidation due to wet reflow occurs only on the surface of the polysilicon, but hydrogen from the plasma nitride film diffuses to some extent in the polysilicon film. The following embodiment 11 utilizes this difference.

Embodiment 11 FIG. FIG. 24 is a sectional view of the TFT, and FIG. 25 is a sectional view taken along the line AA 'of FIG. The structure is such that the interlayer nitride film 36 is overlaid on the polysilicon 59 in the same pattern. A manufacturing method for realizing this structure will be described below.

FIG. 26 shows that an oxide film 32 is formed on a substrate,
FIG. 9 is a view showing a step of forming a gate electrode 33 and depositing a polysilicon 59 on a gate insulating film 60 and a channel portion.
Up to this point, it is the same as the conventional one.

Next, the interlayer nitride film 3 is formed by LPCVD.
6 is deposited (FIG. 27).

Next, the same resist pattern 61 as the desired channel pattern is formed by photolithography (FIG. 28).

Next, the interlayer nitride film 3 is etched by an etching method.
6 and the polysilicon 59 are patterned (FIG. 29). However, if the thickness of the polysilicon 59 constituting the channel is less than the thickness at which the polysilicon 59 will not be oxidized in the subsequent reflow, the polysilicon 59 is not patterned here. However, the polysilicon 59 remains without being oxidized during the reflow, similarly to the pattern of the interlayer nitride film 36.

Next, a silicon oxide film 53 containing phosphorus or boron is deposited by a CVD method, and a reflow heat treatment is performed in an atmosphere containing water vapor 46 to flatten the silicon oxide film 53 (FIG. 30).

Finally, a plasma nitride film 44 is deposited by a plasma CVD method (FIG. 31).

In FIG. 30, the pattern end of the polysilicon 59 is oxidized in the channel portion and slightly narrowed because the interlayer nitride film 36 is not present on the entire surface, but it is about 0.01 to 0.05 μm and the channel width is 0.5 to 0. It is sufficiently smaller than 10 .mu.m. Hydrogen from the plasma nitride film 44 has a thickness of 1.0 μm during deposition and during subsequent sintering (about 450 ° C.).
Due to the above diffusion, even if the interlayer nitride film 36 is present, it diffuses from the side surface of the polysilicon 59 in the channel portion as shown in FIG.
9 to reduce the trap level.

Therefore, according to this method, the film can be prevented from being reduced or lost due to oxidation of the polysilicon 59 in the channel portion due to wet reflow without hindering diffusion of hydrogen into the polysilicon in a later step. .

[0103]

As described above, according to the semiconductor device of the first or ninth aspect, the silicon nitride film formed on the transistor using the polycrystalline semiconductor thin film is opened in the channel portion. Therefore, a substance that terminates a dangling bond of the transistor, for example, hydrogen can be introduced into the channel portion of the transistor from the plasma silicon nitride film formed thereon, whereby the transistor characteristics can be improved. There is.

According to the method of manufacturing a semiconductor device according to the second, third, or tenth aspect, the step of opening the silicon nitride film and introducing hydrogen into the channel portion of the transistor through the opening is performed. The dangling bond included in the transistor can be terminated, and the characteristics of the transistor can be improved.

According to the semiconductor device of the fourth aspect of the present invention, the silicon nitride film is formed as a hole for the contact hole so as to have a hole having an opening size larger than that of the contact hole. Thus, a substance that terminates a dangling bond, for example, hydrogen can be easily introduced into the channel portion of the transistor through a hole having a large opening dimension, and thus there is an effect that characteristics of the transistor can be improved.

According to the semiconductor device according to the fifth or seventh aspect or the semiconductor device according to the sixth or eighth aspect, the silicon nitride film passes through the channel of the transistor in a simple process without increasing the area. There is an effect that a substance that cannot be introduced can be introduced.

According to the method of manufacturing a semiconductor device of the present invention, at least a part of the silicon nitride film is made porous, and a step of forming a plasma silicon nitride film thereon is provided, so that the method becomes porous. By introducing a substance that terminates a dangling bond from the plasma silicon nitride film, such as hydrogen, through a part of the silicon nitride film, the characteristics of the transistor can be improved.

According to the method of manufacturing a semiconductor device of the invention described in claim 12, and the method of manufacturing a semiconductor device of the invention described in claim 13, the first film positively charged on the transistor and the second film negatively charged on the transistor. An OH group having a negative charge, for example, is prevented from entering the channel portion of the transistor by the electric field created by the film. In addition, a substance for terminating dangling bonds, such as hydrogen ions, can be easily introduced from the plasma silicon nitride film into the channel portion, which has an effect that characteristics of the transistor can be improved.

According to the semiconductor device of the invention and the method of manufacturing the semiconductor device of the invention, the pattern of the silicon nitride film is formed in the same desired shape as the channel pattern of the transistor. In addition, a substance for protecting dangling bonds such as hydrogen from the plasma silicon nitride film is introduced from a portion not covered with the silicon nitride film while protecting the channel portion of the transistor in which the silicon nitride film is formed. And the characteristics of the transistor can be improved.

According to the method of manufacturing a semiconductor device of the present invention, a step of depositing a thick polycrystalline semiconductor film used for a channel of a transistor and a step of oxidizing and thinning the polycrystalline semiconductor film are performed. The method includes a step of forming a polycrystalline semiconductor film to a desired thickness and a step of forming a plasma silicon nitride film. Since a film for protecting the polycrystalline semiconductor film is not required, dangling bonds are terminated. Can be easily introduced from the plasma silicon nitride film, and the characteristics of the transistor can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of a memory cell of an SRAM according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view showing a part of a memory cell of an SRAM according to a second embodiment of the present invention;

FIG. 3 is a cross-sectional view showing a part of a memory cell of an SRAM with multilayer wiring according to a third embodiment of the present invention;

FIG. 4 is a cross-sectional view showing a part of a memory cell of an SRAM with multilayer wiring according to a fourth embodiment of the present invention;

FIG. 5 is a cross-sectional view showing a part of a conventional SRAM memory cell.

FIG. 6 is a cross-sectional view around a thin film transistor of a conventional semiconductor device that does not use wet reflow;

FIG. 7 is a cross-sectional view around a thin film transistor of a conventional semiconductor device using wet reflow.

FIG. 8 is a sectional view illustrating a manufacturing process of the semiconductor device according to the fifth embodiment of the present invention;

FIG. 9 is a sectional view illustrating a manufacturing step of the semiconductor device according to the fifth embodiment of the present invention;

FIG. 10 is a sectional view illustrating a manufacturing step of the semiconductor device according to the fifth embodiment of the present invention;

FIG. 11 is a sectional view illustrating a manufacturing step of the semiconductor device according to the fifth embodiment of the present invention;

FIG. 12 is a sectional view illustrating a manufacturing process of the semiconductor device according to the fifth embodiment of the present invention;

FIG. 13 is a sectional view illustrating a manufacturing step of the semiconductor device according to the fifth embodiment of the present invention;

FIG. 14 is a sectional view illustrating a manufacturing step of the semiconductor device according to the fifth embodiment of the present invention;

FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 16 is a sectional view illustrating a manufacturing step of the semiconductor device according to the sixth embodiment of the present invention;

FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the sixth embodiment of the present invention;

FIG. 18 is a cross-sectional view of a manufacturing step of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 19 is a cross-sectional view of a manufacturing step of the semiconductor device according to the eighth embodiment of the present invention;

FIG. 20 is a cross-sectional view of a manufacturing step of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the tenth embodiment of the present invention;

FIG. 22 is a cross-sectional view of a manufacturing step of the semiconductor device according to the tenth embodiment of the present invention;

FIG. 23 is a diagram showing a relationship between a polysilicon film thickness and a wet reflow time in the present invention.

FIG. 24 is a plan view of a thin film transistor according to Embodiment 11 of the present invention.

FIG. 25 is a sectional view taken along line AA ′ of FIG. 24;

FIG. 26 is a sectional view of a manufacturing step in Embodiment 11 of the present invention.

FIG. 27 is a cross-sectional view showing a manufacturing step in Embodiment 11 of the present invention.

FIG. 28 is a cross-sectional view showing a manufacturing step in Embodiment 11 of the present invention.

FIG. 29 is a cross-sectional view of a manufacturing step in Embodiment 11 of the present invention.

FIG. 30 is a cross-sectional view of a manufacturing step in Embodiment 11 of the present invention.

FIG. 31 is a cross-sectional view of a manufacturing step in Embodiment 11 of the present invention.

[Explanation of symbols]

1 single crystal silicon substrate, 2 gate electrode, 2a gate electrode, 3 source / drain region, 4 channel section,
5 gate oxide film, 6 silicon nitride film, 7, 14 interlayer oxide film, 8, 10, 18 through hole, 9, 11,
13 metal plug, 12 first layer aluminum wiring, 15 second layer aluminum pad, 17 second layer aluminum wiring, 31 substrate, 32 oxide film, 33 gate electrode, 34 source,
35 drain, 36 interlayer nitride film, 37 contact hole, 39 oxide film, 41 titanium nitride, 4
2 Tungsten plug, 43 aluminum wiring, 44 plasma nitride film, 45 ion exchange film, 46 OH-based gas, 48 interlayer nitride film, 50 hydrogen diffusion path,
51 polysilicon, 52 polysilicon, 53 interlayer film before reflow, 54 interlayer film after reflow, 55 region with much N-type impurity implantation, 56 region with much P-type impurity implantation, 59 polysilicon, 60 gate Insulating film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigenobu Maeda 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation, within LSI Research Institute (72) Inventor Shigeto Maekawa 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation LSI Research Institute

Claims (16)

[Claims] A transistor using a polycrystalline semiconductor thin film in a channel portion; a silicon nitride film formed above the transistor; a plasma silicon nitride film formed above the silicon nitride film; A semiconductor device having an opening in a silicon nitride film. A step of forming a transistor using a polycrystalline semiconductor thin film in a channel portion; a step of forming a silicon nitride film above the transistor; a step of opening the silicon nitride film; Introducing hydrogen into the channel portion of the transistor through the opening of the semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 2, wherein said step of introducing hydrogen includes a step of forming a plasma silicon nitride film above said silicon nitride film. 4. A transistor using a polycrystalline semiconductor thin film in a channel portion, a silicon nitride film formed above the transistor, a conductor penetrating the silicon nitride film, the silicon nitride film and the conductor And a plasma silicon nitride film formed above the conductor, wherein the silicon nitride film penetrates the conductor and has a hole larger in size than the conductor. 5. A first semiconductor device formed above a silicon nitride film.
And a second wiring disposed in an opening formed in the silicon nitride film and electrically connecting a gate electrode of a transistor and the first wiring. 1
13. The semiconductor device according to claim 1. 6. A step of arranging a first wiring electrically connected to a gate electrode of the transistor in an opening formed in the silicon nitride film; and a step of arranging a gate electrode of the transistor through the first wiring. Forming a second wiring electrically connected to the silicon nitride film above the silicon nitride film. 7. A first semiconductor device formed above a silicon nitride film.
And a second wiring disposed in an opening formed in the silicon nitride film and electrically connecting the source / drain region of the transistor and the first wiring. The semiconductor device according to claim 1. 8. A step of arranging a first wiring connected to a source / drain region of a transistor in an opening formed in a silicon nitride film, and a step of arranging a source / drain of the transistor via the first wiring. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising: forming a second wiring electrically connected to the region above the silicon nitride film. 9. A transistor formed above a semiconductor substrate and using a polycrystalline semiconductor thin film in a channel portion; a silicon nitride film formed above the transistor and having an opening; and formed above the silicon nitride film. A first wiring, a second wiring disposed in the opening formed in the silicon nitride film, and electrically connecting the semiconductor substrate to the first wiring; And a plasma silicon nitride film formed above the second wiring, wherein hydrogen is introduced from the plasma silicon nitride film into the channel portion of the transistor through the second wiring. apparatus. 10. A step of forming a transistor using a polycrystalline semiconductor thin film in a channel portion above a semiconductor substrate; a step of forming a silicon nitride film having an opening above the transistor; Disposing a first wiring electrically connected to the semiconductor substrate in the opening formed in the semiconductor substrate; and forming the first wiring over the silicon nitride film via the first wiring. Forming a second wiring to be electrically connected; and forming a plasma silicon nitride film above the first and second wirings, wherein hydrogen from the plasma silicon nitride film A method for manufacturing a semiconductor device, wherein the semiconductor device is introduced into the channel portion of the transistor through one wiring. 11. A step of forming a transistor having a channel of a polycrystalline semiconductor thin film; a step of forming a silicon nitride film above the transistor; a step of making at least a portion of the silicon nitride film porous; Forming a plasma silicon nitride film above the nitride film. 12. A transistor using a polycrystalline semiconductor thin film in a channel portion, and a first positively charged first transistor formed above the transistor.
A non-charged insulating film formed above the first film and a non-charged second film formed above the insulating film and negatively charged; And a plasma silicon nitride film to be formed. 13. A step of forming a transistor having a channel of a polycrystalline semiconductor thin film, a step of depositing a negatively charged first film above the transistor, and a step of charging above the first film. Forming a non-insulating film, depositing a positively charged second film over the insulating film, and forming a plasma silicon nitride film over the second film Device manufacturing method. 14. A transistor using a polycrystalline semiconductor thin film in a channel portion, a silicon nitride film formed on the transistor, and a plasma silicon nitride film formed above the silicon nitride film, A semiconductor device, wherein the pattern of the silicon nitride film is formed in the same desired shape as the channel pattern of the transistor. 15. A step of forming a polycrystalline semiconductor thin film used for a channel of a transistor; a step of depositing a silicon nitride film on the polycrystalline semiconductor thin film; A method of manufacturing a semiconductor device, comprising: a step of patterning into a desired pattern; and a step of forming a plasma silicon nitride film above the silicon nitride film. 16. A step of depositing a thick polycrystalline semiconductor film used for a channel of a transistor, a step of depositing a silicon oxide film containing impurities on the transistor, and performing a heat treatment in an atmosphere of molecules containing OH groups. A step of reducing the step of the silicon oxide film and oxidizing the polycrystalline semiconductor film of the transistor to make the polycrystalline semiconductor film a desired thickness; and Forming a plasma silicon nitride film.