JP2001175618A - Parallel computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stop barrier-synchronous process TAT of a parallel computer system from increasing. SOLUTION: In each of clusters coupled by an inter-cluster coupling network, a remote access controller which is connected to arithmetic processors is provided with an in-cluster synchronism controller 310. The number of object arithmetic processors of in-cluster barrier synchronism is previously written to a counter 305. With an instruction from an arithmetic processor having reached a barrier synchronism point, the counter 305 is made to count down and its value is sent out to the arithmetic processor through a data input transfer device 303. Consequently, it can be recognized that all the arithmetic processors in the cluster have reached the barrier synchronism point. The inter-cluster coupling network is also provided with an inter-cluster barrier synchronism controller of nearly the same constitution and the counter to which the number of object clusters of inter-cluster barrier synchronism is previously written is made to count down with an instruction from a cluster having achieved in-cluster barrier synchronization.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer system, and more particularly to a cluster-connected parallel computer system connected via an inter-cluster interconnection network.

[0002]

2. Description of the Related Art A conventional parallel computer system having a cluster configuration includes a plurality of clusters and an inter-cluster interconnection network connecting the clusters. The cluster is a parallel computer node composed of a plurality of arithmetic processors, a main storage device, and an intra-cluster interconnection network that connects the inter-cluster interconnection networks.

[0003] As a type of the inter-cluster interconnection network, for example, a full crossbar (sloss bar switch) can be selected, but this interconnection network only routes communication (access) between clusters. Therefore, in order to perform synchronous control between a plurality of arithmetic processors belonging to different clusters, for example, a parallel processing machine written by Shinji Tomita and Toshinori Sueyoshi (edited by the Institute of Electronics, Information and Communication Engineers, published by Ohmsha), p. It is necessary to provide a barrier synchronizer in the interconnection network between clusters using the technique described in 117-120.

[0004] The barrier synchronizer is provided with a counter, and the processor of each node can access the counter. Before the start of barrier synchronization, one processor sets an initial value to a counter. The initial value is the number of processors that perform barrier synchronization. Barrier synchronization is initiated and each processor decrements the counter when the synchronization point is reached. When all processors reach the synchronization point and the value of the counter becomes 0, the barrier synchronization is completed. After reaching the synchronization point and decrementing the counter, each processor performs a spin lock to read whether the value of the counter is 0 or not. If the read value is 0, it can be recognized that the barrier synchronization has been completed.

[0005]

However, in the above-described conventional parallel computer system, when all processors in all nodes perform barrier synchronization, a decrement request for a counter issued by all processors and a read request for the counter are simultaneously performed. publish. In this case, since access to the counter is concentrated, access is serialized by contention arbitration, and TAT (Turn Around Time) of access is performed.
Is reduced. There is a problem that the reduction of the TAT causes an increase in the processing time of the entire barrier synchronization. The performance degradation of the barrier synchronization accompanying the concentration of accesses to the counter tends to become more remarkable as the number of processors increases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a parallel computer system in which barrier synchronization is speeded up, and in particular, even if the number of processors performing parallel processing increases, the barrier synchronization processing TAT does not increase.

[0007]

According to a first aspect of the present invention, there is provided a cluster system for controlling, within a cluster connected by an inter-cluster interconnection network, barrier synchronization within a cluster for each processor in the cluster. An internal barrier synchronization control means is provided, and an inter-cluster barrier synchronization control means for controlling inter-cluster barrier synchronization for each of the clusters is provided in the inter-cluster interconnection network.

A second parallel computer system according to the present invention includes a plurality of arithmetic processors, a main storage device, these arithmetic processors, a remote access control device for controlling inter-cluster data transfer, and the arithmetic processor, the main storage device, In a parallel computer system having a cluster configuration including a plurality of clusters each including an intra-cluster interconnection network connecting remote access control devices and an inter-cluster interconnection network connecting the plurality of clusters, The control device is provided with an intra-cluster barrier synchronization control device that controls intra-cluster barrier synchronization for each processor in the cluster, and the inter-cluster interconnection network includes a cluster for the cluster that has completed the intra-cluster barrier synchronization. Barrier between clusters that performs the same control between barriers Characterized in that a synchronization control device.

Specifically, in the parallel computer system according to the present invention, the remote access control device is connected to the intra-cluster interconnection network, and issues an inter-cluster data transfer request command or an intra-cluster barrier synchronization counter access from the arithmetic processor. An input circuit for inputting an instruction, and receiving the inter-cluster data transfer request instruction from the input circuit;
If it is a write transfer command, sends data loaded from the main storage device to the cluster interconnection network; if it is a read transfer instruction, sends the data to the inter-cluster interconnection network; A data input / transfer device for storing data input from the interconnection network in the main storage device, and transferring the data to the data output device upon receiving the read transfer command to perform the same operation as at the time of the write transfer command; And an intra-cluster barrier synchronization control device that controls the intra-cluster barrier synchronization when receiving the intra-cluster barrier synchronization counter access command from the input circuit.

Further, the intra-cluster barrier synchronization control device writes in advance the number of arithmetic processors performing the intra-cluster barrier synchronization from a predetermined arithmetic processor in the cluster, and decrements each time the arithmetic processor reaches a barrier synchronization point. Counter, a decrementer for executing the decrement by decrementing the count value of the counter by 1, and a write / read request for the counter according to the content of the instruction when the intra-cluster barrier synchronization counter access instruction is received from the input circuit. Alternatively, a write control circuit for making a decrement request, and a read control circuit for sending the count value sent from the counter by the read request to the decrementer and transferring the count value to the data input / transfer device and sending it to the arithmetic processor It consists of.

A barrier completion notifying circuit for judging the completion of intra-cluster barrier synchronization based on the notification from the read control circuit and notifying the inter-cluster barrier synchronizing device of the completion of barrier synchronization is provided to the intra-cluster barrier synchronization control device. It may be added.

Further, the inter-cluster interconnection network is connected to each of the clusters and receives an input of data or an inter-cluster barrier synchronization counter access instruction from the arithmetic processor, and an instruction to receive data from the input circuit. And an inter-cluster barrier synchronization control device for controlling the intra-cluster barrier synchronization when receiving the inter-cluster barrier synchronization counter access command from the input circuit. .

Further, the inter-cluster barrier synchronization control device includes a request contention arbitration circuit for arbitrating a plurality of inter-cluster barrier synchronization counter access instructions issued from different clusters, A counter in which the number of clusters for performing barrier synchronization is written in advance and decremented each time the cluster reaches a barrier synchronization point; a decrementer for reducing the count value of the counter by 1 to perform the decrement; and a request contention arbitration circuit. Upon receiving the inter-cluster barrier synchronization counter access instruction arbitrated in step (1), a write control circuit for issuing a write, read request or decrement request to the counter according to the contents thereof, and a counter transmitted from the counter in response to the read request. Sends out a value to the decrementer composed of a read control circuit for transferring to the clusters are transferred to the inter-cluster connection network.

In the present invention, the barrier synchronization counter is divided into the inter-cluster barrier synchronization counter and the intra-cluster barrier synchronization counter, so that the barrier synchronization between the processors in the cluster can be performed in each cluster in parallel.
Since the counter decrement of the barrier synchronization between clusters can be performed by one access of the cluster representative from each cluster, the barrier synchronization processing time can be reduced.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a system configuration example of a parallel computer having a general cluster configuration to which the present invention is applied. 1
1, 1... 1n indicate clusters, respectively, and these clusters 11 to 1n independently constitute one parallel computer as shown in FIG. Reference numeral 2 denotes an inter-cluster interconnection network that connects n clusters 11 to 1n. Each of the clusters 10 to 1n is prepared for one port for the inter-cluster interconnection network 2, and this port and the inter-cluster interconnection network 2 are connected by a link. Therefore, if the number of clusters is n, the inter-cluster interconnection network 2 has an n-input, n-output network configuration.

All communication of requests between the clusters 11 to 1n is performed via the inter-cluster interconnection network 2. The inter-cluster interconnected network 2 has a function of, when a plurality of requests for requesting the same cluster arrive at the same time, competing for these requests and routing the request.

FIG. 2 shows a general configuration example of clusters 11 to 1n having the same configuration. Since 211, 212... 21m indicate arithmetic processors, if each of the n clusters has m arithmetic processors, it means that the parallel computer system has n × m arithmetic processors. 230 indicates a main storage device in the cluster. It is assumed that the main storage device 230 can be accessed by both an arithmetic processor in its own cluster and an arithmetic processor in another cluster. Accessing a main storage device in the own cluster by an arithmetic processor in the own cluster is called local access, and accessing a main storage device in another cluster is called remote access.

Reference numeral 220 denotes an intra-cluster interconnection network. The intra-cluster interconnection network 220 connects the arithmetic processors 211 to 21m in the own cluster and the main storage device 230.
One port is provided as an access path to the inter-cluster interconnection network 2 via the remote access control device 240 described later. Accordingly, the inter-cluster interconnection network 2 arbitrates requests for local access sent from a plurality of arithmetic processors in its own cluster and remote access sent from the inter-cluster interconnection network 2 and arbitrates each request. Is routed to a desired main memory, arithmetic processor, and interconnection network 2 between clusters.

When remote access is made to the main storage device 230 of another cluster, the path of the request starts from the self-processor and starts from the intra-cluster interconnection network 220, the inter-cluster interconnection network 2 and the other networks. Through the intra-cluster interconnection network 220 of the cluster, it reaches the main storage device 230 of the other cluster.
Access is performed in the reverse direction of the above path.

Reference numeral 240 denotes a remote access control device. The remote access control device 240 is connected to the intra-cluster interconnection network 220 and the inter-cluster interconnection network 2.
The remote access control device 220 includes processors 211 to
An inter-cluster data transfer request command issued by 21m is accepted. There are two types of the inter-cluster data transfer request command: a read data transfer command and a write data transfer command.
The write transfer instruction is an instruction for transferring data from the main storage device in the own cluster to the main storage device in another cluster, and the read transfer instruction is for transferring data from the main storage device in the other cluster to the main storage device in the own cluster. Instruction to transfer.

FIG. 3 shows an example of the configuration of a remote access control device 240 to which the present invention is applied.
1, data output transfer device 302, data input transfer device 3
03 and an intra-cluster barrier synchronization control device 310. Furthermore, the intra-cluster barrier synchronization control device 310
It comprises a write control circuit 304, a counter 305, a read control circuit 306, and a decrementer 307.

The input circuit 301 includes processors 211 and 2
1m is transferred to the data output transfer device 302. If the command is a barrier synchronization counter access command, it is transferred to the intra-cluster barrier synchronization control device 310.

The write transfer command among the inter-cluster data transfer commands is transmitted from the input circuit 301 to the data output transfer device 30.
2 When receiving the write transfer command, the data output transfer device 302 loads data from the main storage device 230 via the input circuit 301, and sends the loaded data to the inter-cluster interconnection network 2. When the data input / transfer device 303 of the data transfer destination cluster receives the data transferred from the inter-cluster interconnection network 2, the data is transferred to the main storage device 230 via the intra-cluster interconnection network 220.
Store in

On the other hand, a read transfer command among the inter-cluster data transfer commands is also transferred from the input circuit 301 to the data output transfer circuit 302. When receiving the read transfer command, the data output transfer device 302 transfers this to the inter-cluster interconnection network 2. When a read transfer command is input from the inter-cluster interconnection network 2, the data input device 303 of the command transfer destination cluster transmits the read transfer command to the data output transfer device 302.
Transfer to Upon receiving the read transfer command, the data output transfer device 302 loads data from the main storage device 230 via the intra-cluster interconnection network 220 and the input circuit 301, and transfers the loaded data to the inter-cluster interconnection network 2.
To send to. If the data input / transfer device 303 of the destination cluster (read transfer command source cluster) receives the data transferred from the inter-cluster interconnection network 2, the data is transferred to the main storage device via the intra-cluster interconnection network 220. Store at 230.

The barrier synchronization counter access instruction is transferred from the input circuit 301 to the intra-cluster barrier synchronization control device 310. The barrier synchronization counter access instruction includes three types of instructions: a counter read instruction, a counter write instruction, and a counter decrement instruction. The counter write instruction is issued together with write data from the processors 211 to 21m and is an instruction to store data in the counter 305. The counter read command is issued from the processors 211 to 21m, reads the counter 305, and returns the read data to the processors 211 to 21m. The counter decrement instruction is issued from the processors 211 to 21m and has a counter value 305.
Is an instruction to decrement the count value. The count value before decrement is returned to the processor.

The counter write command is transferred from the input circuit 301 to the intra-cluster barrier synchronization control device 310. When receiving the counter write command, the write control circuit 304 sends a write access request and write data to the counter 305. When the counter 305 receives the write access request, it updates the count value of the counter 305 to the received write data.

On the other hand, the counter read command is input to the input circuit 30.
1 to the intra-cluster barrier synchronization control device 310. Upon input of the counter read command, the write control circuit 301 sends a read access request to the counter 305. Upon receiving the read access request, the counter 305 sends the count value of the counter 305 to the read control circuit 306. The read control circuit 306 transfers the read data to the data input transfer device 303. The data input / transfer device 303 transfers the read data to the processor 2 via the intra-cluster interconnection network 220 and the main storage device 230.
Return to 11-21m.

The counter decrement command is transferred from the input circuit 301 to the barrier control device 310. Upon input of the counter decrement command, the write control circuit 301 sends a decrement access request to the counter 305. Upon receiving the decrement access request, the counter 305 sends the count value of the counter 305 to the read control circuit 306. Read control circuit 30
6 sends the read data to the decrementer 307. The read data is transferred to the data input transfer device 303, and the read data is returned to the processors 211 to 21m. The decrementer 307 performs an operation of subtracting -1 from the read data, and transfers the operated data to the write control circuit 304. The write control circuit 304 sends the data after the decrement operation to the counter 305 together with the write access request. The counter 305 writes the received data.

FIG. 4 shows an example of the configuration of the inter-cluster interconnection network 2, in which the inter-cluster interconnection network 401 and the clusters 11 to 11 are arranged.
It comprises input circuits 411 to 41n corresponding to 1n and an inter-cluster barrier synchronization control device 410. Further, the inter-cluster barrier synchronization control device 410 includes a request contention arbitration circuit 402, a write control circuit 404, a counter 405, a read control circuit 406, and a decrementer 407. If the input circuits 411 to 41n receive the data from the clusters 11 to 1n, the input circuits 411 to 41n transmit the data to the inter-cluster connection network
To send to. If it is an inter-cluster barrier synchronization counter access command, it is sent to the inter-cluster barrier synchronization control device 410.

The inter-cluster barrier synchronization counter access instruction is transferred from the input circuits 411 to 41n to the inter-cluster barrier synchronization control device 410. The inter-cluster barrier synchronization counter access instruction includes three types of instructions: an inter-cluster counter read instruction, an inter-cluster counter write instruction, and an inter-cluster counter decrement instruction. The inter-cluster counter write instruction is an instruction issued with the write data from the processors 211 to 21m and storing the data in the counter 405. The inter-cluster counter read instruction is issued from the processors 211 to 21m, reads the counter 405, and reads the read data from the processor 21.
It is an instruction to return to 1 to 21 m. The inter-cluster counter decrement instruction is an instruction issued by the processors 211 to 21m to decrement the count value of the counter 405. The count value before decrement is returned to the processor.

The inter-cluster counter write command is sent from the input circuits 411 to 41n through the inter-cluster barrier synchronization control device 31.
0 is transferred. When a plurality of inter-cluster counter write instructions issued from different clusters are simultaneously input, the request contention arbitration circuit 402 arbitrates and selects one instruction and sends it to the write control circuit 404. Other instructions are also sequentially selected for arbitration and sent to the write control circuit 404. Upon receiving the inter-cluster counter write command, the write control circuit 404 sends a write access request and write data to the counter 405. Upon receiving the write access request, the counter 405 updates the count value of the counter 405 to the received write data.

The inter-cluster counter read command is sent from the input circuits 411 to 41n through the inter-cluster barrier synchronization control device 41.
0 is transferred. When receiving the inter-cluster counter read command, the write control circuit 404 sends a read access request to the counter 405. Upon receiving the read access request, the counter 405 sends the count value of the counter 405 to the read control circuit 406. The read control circuit 406 transfers the read data to the inter-cluster connection network 40.
Transfer to 1. The inter-cluster connection network 401 returns the read data to the processors 211 to 21m.

The inter-cluster counter decrement instruction is transferred from the input circuits 411 to 41n to the barrier control device 410. When receiving the inter-cluster counter decrement command, the write control circuit 404 sends a decrement access request to the counter 405. Counter 405
Sends a count value of the counter 405 to the read control circuit 406 upon receipt of the decrement access request. The read control circuit 406 sends the read data to the decrementer 407. The read data is transferred to the inter-cluster connection network 401, and the read data is returned to the processors 211 to 21m. The decrementer 407 performs an operation of decreasing the data by one, and transfers the operated data to the write control circuit 404. Light control circuit 40
4 sends the data after the decrement operation to the counter 405 together with the write access request. The counter 405 writes the received data.

Next, the processors 211 to 2 in the cluster
An operation of performing barrier synchronization for 1 m will be described. Prior to the start of the barrier synchronization, the processor 211 writes the number of processors performing the barrier synchronization to the counter 305 using a counter write instruction. In this embodiment, the m value is written. When the barrier synchronization is started, the processor that has reached the barrier synchronization point issues a counter decrement instruction to the counter 305. A processor whose return value of the counter decrement instruction is 1 can recognize that all processors have reached the barrier synchronization point. This processor issues an inter-cluster counter decrement instruction to the inter-cluster interconnection network 2.

The operation of performing barrier synchronization between processors 211 to 21m in all clusters will be described. Before the start of barrier synchronization, the processor 211 of the cluster 11 writes the number of clusters for which barrier synchronization is to be performed to the counter 405 using a counter write instruction. In this embodiment, the n value is written. If the barrier synchronization is started, if the return value of the inter-cluster counter decrement instruction of the processor that has issued the above-described inter-cluster counter decrement instruction is 1, it can be recognized that all clusters have reached the barrier synchronization point. it can.

Next, another example of the remote access control device 240 to which the present invention is applied will be described with reference to FIG. As is apparent from a comparison of FIG. 5 with FIG. 3, a barrier completion notification circuit 508 is provided in the intra-cluster barrier synchronization control device 510 in this embodiment.

The barrier completion notifying circuit 508 includes a counter 3
It can be recognized from the notification from the read control circuit 306 that the count value of 05 has changed to 0 value. The fact that the count value of the counter 305 has changed to 0 means that
Indicates that barrier synchronization within the cluster has been completed. At this time, the barrier completion notification circuit 508 sends an inter-cluster counter decrement instruction to the data output transfer device 502. Also in this embodiment, the inter-cluster interconnection network 2 shown in FIG. 4 can be used as it is. Therefore, the data output transfer device 502 transfers this inter-cluster counter decrement instruction to the inter-cluster interconnection network 2, and the counter 405 of the inter-cluster barrier synchronization control device 410 is decremented by one.

In the first embodiment described above, the arithmetic processor that has recognized that the barrier synchronization point in the cluster has been reached issues an inter-cluster counter decrement instruction to the inter-cluster interconnection network 2. In the second embodiment, since the inter-cluster counter decrement instruction is issued directly from the barrier completion notifying circuit 508, the barrier synchronization can be further speeded up.

[0040]

According to the configuration of the present invention described above, barrier synchronization between processors in a cluster can be performed in each cluster in parallel. Further, the counter decrement of the barrier synchronization between the clusters requires only one access of the cluster representative from each cluster. Therefore, access to the inter-cluster barrier synchronization control device can be reduced, and barrier synchronization can be speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a general parallel computer system to which the present invention is applied;

FIG. 2 is a block diagram showing a configuration example of a general cluster in the parallel computer system shown in FIG. 1;

FIG. 3 is a block diagram showing a remote access control device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing an interconnection network between clusters according to the present invention;

FIG. 5 is a block diagram showing a remote access control device according to a second embodiment of the present invention.

[Explanation of symbols]

 2 Inter-Cluster Interconnection Network 11 Cluster 12 Cluster 1n Cluster 210 Arithmetic Processor 211 Arithmetic Processor 21m Arithmetic Processor 220 Inter-Cluster Interconnection Network 230 Main Storage Device 240 Remote Access Controller 301 Input Circuit 302 Data Output Transfer Device 303 Data Input Transfer Device 304 Write control device 305 Counter 306 Read control device 307 Decrementer 310 Intra-cluster barrier synchronization control device 401 Inter-cluster interconnection network 404 Write control device 405 Counter 406 Read control device 407 Decrementer 410 Inter-cluster barrier synchronization control device 411 Input circuit 412 Input circuit 41n input Circuit 502 Data output transfer device 508 Barrier completion notification device 510 Barrier synchronization control device

Claims (7)

[Claims] 1. An intra-cluster barrier synchronization control means for controlling intra-cluster barrier synchronization for each processor in the cluster in a cluster connected by an inter-cluster interconnection network; A parallel computer system, wherein inter-cluster barrier synchronization control means for controlling inter-cluster barrier synchronization for each cluster is provided in a network. 2. A plurality of arithmetic processors, a main storage device, a remote access control device for controlling these arithmetic processors, data transfer between clusters, and a cluster for connecting the arithmetic processor, the main storage device, and the remote access control device. In a parallel computer system having a cluster configuration including a plurality of clusters each including an interconnection network and an inter-cluster interconnection network connecting the plurality of clusters, the remote access control device includes: An intra-cluster barrier synchronization control device for controlling intra-cluster barrier synchronization for the arithmetic processor is provided. The inter-cluster interconnection network further includes inter-cluster barriers for controlling the same inter-cluster barrier for the cluster that has completed the intra-cluster barrier synchronization. A barrier synchronization control device is provided. Parallel computer system that. 3. An input circuit which is connected to the intra-cluster interconnection network and receives an inter-cluster data transfer request instruction or an intra-cluster barrier synchronization counter access instruction from the arithmetic processor, and Receiving the inter-cluster data transfer request command from the circuit; if the command is a write transfer command, sends the data loaded from the main memory to the cluster interconnection network; A data output transfer device for transmitting the data input from the inter-cluster interconnection network to the main storage device, and, when the read transfer command is received, transferring the data to the data output device to perform the write transfer command. A data input transfer device for performing the same operation as the above, and Parallel computer system according to claim 2, characterized in that they are composed of a rear synchronous counter access instruction to receive a cluster barrier synchronization control unit for controlling said cluster barrier synchronization. 4. The intra-cluster barrier synchronization control device, wherein the number of arithmetic processors performing the intra-cluster barrier synchronization is written in advance from a predetermined arithmetic processor in the cluster, and is decremented each time the arithmetic processor reaches a barrier synchronization point. A decrementer for reducing the count value of the counter by 1 to execute the decrement, and receiving a write / read request for the counter according to the content of the instruction when the intra-cluster barrier synchronous counter access instruction is received from the input circuit. A write control circuit for making a decrement request; a read control circuit for sending the count value sent from the counter in response to the read request to the decrementer, transferring the count value to the data input transfer device, and sending it to the arithmetic processor. Parallel computer system according to claim 2 or claim 3, characterized in that it is configured. 5. The in-cluster barrier synchronization control device,
5. A barrier completion notifying circuit for judging completion of barrier synchronization within a cluster based on a notification from the read control circuit and notifying the inter-cluster barrier synchronizer of the completion of barrier synchronization is provided. A parallel computer system according to any one of the above. 6. The inter-cluster interconnection network is connected to each of the clusters and receives an input of data or an inter-cluster barrier synchronization counter access instruction from the arithmetic processor, and an instruction to receive data from the input circuit. And an inter-cluster barrier synchronization control device for controlling the intra-cluster barrier synchronization when receiving the inter-cluster barrier synchronization counter access command from the input circuit. 6. The parallel computer system according to claim 2, wherein: 7. An inter-cluster barrier synchronization control device, comprising: a request contention arbitration circuit for arbitrating a plurality of inter-cluster barrier synchronization counter access instructions issued from different clusters; A counter in which the number of clusters for performing barrier synchronization is written in advance and decremented each time the cluster reaches a barrier synchronization point; a decrementer for reducing the count value of the counter by 1 to execute the decrement; and a request contention arbitration circuit. Upon receiving the inter-cluster barrier synchronization counter access instruction arbitrated in step (a), a write control circuit for issuing a write, read request or decrement request to the counter according to the content thereof, and a count value transmitted from the counter in response to the read request 7. The parallel computer system according to claim 2, further comprising: a read control circuit that sends the data to the decrementer and transfers the data to the inter-cluster connection network to transfer the data to the cluster. .