JP2001175456A - Arithmetic unit, arithmetic method and calculator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic unit and a computer, capable of performing the arithmetic operation of data in plural data formats, using a simple configuration. SOLUTION: This arithmetic unit is provided with an IEEE post-processing part, which is common to an adding/subtracting par, a multiplying part, and a dividing part, and at the time of operating the processing of data in an IEEE format, the outputs of the adding/subtracting part, the multiplying part, and the dividing part are post-processed by the IEEE post-processing part, and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computing device, a computing method, and a computing device, and more particularly, to a computing device, a computing method, and a computing device for performing a floating-point operation. Current,
The floating-point arithmetic includes a plurality of floating-point arithmetic formats such as a digit single-precision floating-point format, a digit double-precision floating-point format, and an IEEE single-precision floating-point format. These multiple floating-point arithmetic formats include exponentiation width,
The radix of the exponent, the presence or absence of the rounding operation, etc. are different.

For this reason, a plurality of floating point arithmetic circuits cannot be handled by one floating point arithmetic circuit. In order to realize an arithmetic device that can support a plurality of floating-point arithmetic formats, it is necessary to provide an arithmetic circuit corresponding to each floating-point arithmetic format, and the circuit scale becomes large. Therefore, it is desired that a plurality of floating point formats can be operated without increasing the circuit scale.

[0003]

2. Description of the Related Art A floating-point number is a numerical expression method in which a number is represented by an exponent and a mantissa. For example, if a numerical value is x, a mantissa is m, an exponent is e, and a radix is B, then x = m × B ^e (1) Floating point numbers are widely used in calculations in the fields of scientific and technical computing and computer graphics.

FIG. 1 is a diagram for explaining the representation of a floating point by a binary number. The floating-point value 1 is
It consists of an exponent part 3 and a mantissa part 4. The sign unit 2 stores a sign for identifying whether the numerical value 1 is positive or negative in a binary number. For example, if the sign part 2 is “0”, it is positive, and the sign part 2
Is negative if “1”. In the exponent part 3, a numerical value corresponding to “e” in Expression (1) is stored in a binary number.

In the mantissa part 4, a numerical value corresponding to "m" in the equation (1) is stored in a binary number. This floating point number
There are various forms of expression. The main ones are digit floating point format and IEEE (The Institute of Electrical
and Electronic Engineers) There is a floating point format.
The digit floating-point format is a format in which a numerical value x ₁₆ is represented by x ₁₆ = m × 16 ^e (2).

In the IEEE floating point format, a numerical value x
_IEEE is a format represented by x _IEEE = m × 2 ^e (3). Next, the case where the digit floating point format and the IEEE floating point format are expressed in bits will be described.

First, the case where the digit floating-point format is expressed in bits will be described. The digit floating-point format, when expressed in bits, includes, for example, a single-precision expression format, a double-precision expression format, and an extended-precision expression format. FIG. 2 is a diagram for explaining a case where a numerical value in a digit floating point format is represented by bits. FIG. 2A shows a digit single precision floating point format, and FIG. 2B shows a digit double precision floating point format.

As shown in FIG. 2A, a bit string 5 in a single-precision floating-point format has a 1-bit code
It is represented by a 32-bit bit string including a 7-bit exponent 7 and a 24-bit mantissa 8. As shown in FIG. 2B, the bit string 9 in the digit double precision floating-point format is represented by a bit string of a total of 64 bits including a 1-bit sign part 10, a 7-bit exponent part 11, and a 56-bit mantissa part 12. .

In the digit floating-point format, a value that cannot be represented by digit alignment or the like due to arithmetic processing is truncated. Next, IEEE
A case where the floating-point format is represented by bits will be described. The IEEE floating-point format includes, for example, a single-precision representation format, a double-precision representation format, and an extended-precision representation format when expressed in bits.

FIG. 3 is a diagram for explaining a case where a numerical value in the IEEE floating point format is represented by bits. FIG.
3A shows the IEEE single-precision floating-point format, and FIG. 3B shows the IEEE double-precision floating-point format. As shown in FIG. 3A, the bit string 13 in the IEEE single-precision floating-point format is composed of a 1-bit sign part 14, an 8-bit exponent part 7, and 23.
It is represented by a bit string of a total of 32 bits of the mantissa part 15 of bits.

As shown in FIG. 3B, the bit string 17 in the IEEE double-precision floating-point format is
8, 11-bit exponent part 19, 52-bit mantissa part 20
Is represented by a bit string of 64 bits in total. In addition, IEEE
In the E-floating-point format, values that cannot be represented by digit alignment or the like due to arithmetic processing are not truncated.
The result is the result of rounding in the specified mode. For this reason, the arithmetic error in the IEEE floating point format is smaller than that in the digit floating point format. As described above, the arithmetic device that processes the IEEE floating-point format requires a bit-unit shifter and a rounding circuit that are not required in the digit floating-point format.

On the other hand, in a conventional computer that handles only the digit floating point format, the operation width of the exponent operation unit is 7
A bit is fine. Also, there is no need for rounding after the operation. However, the digit floating-point format has a large number of calculation errors. Furthermore, in recent years, IEEE floating-point format has become a standard in programs such as JAVA. For this reason, in addition to the digit floating-point format, a highly accurate IE
A computer capable of handling the EE floating point format is desired.

In view of the above, it is possible to expand the operation width of the exponent operation unit and add a mantissa digit alignment bit shifter and a rounding circuit to a conventional floating point arithmetic unit that handles the digit floating point format, thereby enabling processing in the IEEE floating point format. Computing devices have been developed. Here, first, a conventional floating point addition / subtraction apparatus will be described.

FIG. 4 is a block diagram showing an example of a conventional floating point addition / subtraction apparatus. The floating point addition / subtraction device 21
It performs addition and subtraction in a digit floating-point format and addition and subtraction of numerical values in an IEEE floating-point format. The floating point addition / subtraction device 21 includes input units 22 and 23, an exponent comparison unit 2
4, exponent difference detecting section 25, digit matching section 26, adding section 27, normalized number counting section 28, normalizing section 29, exponent correcting section 30,
Selection units 31 to 34, output unit 35, overflow bit holding unit 3
6, a rounding operation unit 37 and a control unit 38.

Input units 22 and 23 are supplied with numerical values in a floating-point format. The input units 22 and 23 switch the number of exponent bits and the number of mantissa bits between a digit floating point format and an IEEE floating point format. Input unit 2
The exponent bits of the numerical values input from 2 and 23 are supplied to the exponent comparing unit 24, the exponent difference detecting unit 25, and the selecting unit 31. The mantissa bits are supplied to the selection units 32 and 33.

The exponent comparing section 24 compares the exponent bit from the input section 22 with the exponent bit from the input section 23, and controls the selecting sections 31, 32, and 33. The selection unit 31 selects the larger exponent bit and supplies it to the exponent correction unit 30.
The selecting unit 32 selects the mantissa bit of the smaller numerical value of the exponent bit and supplies it to the digit matching unit 26. The selecting unit 33 selects the mantissa bit of the larger value of the exponent bit and supplies the selected mantissa bit to the adding unit 27.

The exponent difference detecting section 25 detects an exponent difference between the exponent bit from the input section 22 and the exponent bit from the input section 23 and supplies it to the digit matching section 26. The digit matching unit 26 includes the selecting unit 3
The mantissa bits supplied from 2 are shifted according to the exponent difference supplied from the exponent difference detection unit 25 to perform digit alignment. The mantissa bits that have been digit-aligned by the digit matching unit 26 are supplied to the adding unit 27. When performing addition and subtraction in the IEEE floating-point format, the digit matching unit 26 performs the overflow bit holding unit 36.
Holds overflow bits.

The adder 27 adds the mantissa bits from the digitizer 26 and the mantissa bits from the selector 33. The mantissa bits added by the adding unit 27 are supplied to the normalizing unit 29 and the selecting unit 34. Further, the adding unit 27 sets the number required for normalization in the normalization counting unit 28. The normalization counting unit 28 controls the normalization unit 29 according to the number set by the adding unit 27. The normalization unit 29 is supplied with the addition result from the addition unit 27, and normalizes the addition result by the number set in the normalization counting unit 28. Note that the normalization unit 2
9 performs IEEE floating-point arithmetic,
Performs digit alignment shift in bit units.

The mantissa bits normalized by the normalizing section 29 are supplied to a selecting section 34. The selection unit 34 selects either the mantissa bit from the normalization unit 29 or the mantissa bit from the addition unit 29 by the normalization counting unit 28 and supplies the selected bit to the output unit 35. The selection unit 34 includes the normalized counting unit 2
If it is determined in step 8 that normalization is not necessary, the addition unit 2
7 and outputs a mantissa bit from the normalized count unit 2
If it is determined in step 8 that normalization is necessary, the mantissa bit normalized by the normalization unit 29 is selectively output.

Further, the normalization counting section 28 includes the adding section 2
The correction value corresponding to the number set from 7 is supplied to the exponent correction unit 30. The exponent correction unit 30 corrects the exponent bit from the selection unit 31 according to the correction value from the normalization count unit 28. When adding or subtracting a numerical value in the digit floating point format, the rounding operation unit 37 supplies the mantissa bit from the selection unit 34 to the output unit 35 as it is. Rounding operation unit 37
Performs addition and subtraction of numbers in the IEEE floating-point format, performs a rounding operation according to the overflow bit held in the overflow bit holding unit 36, and outputs the rounding operation result to the output unit 35.
To supply.

The output unit 35 combines the exponent bits from the exponent correction unit 30 and the mantissa bits from the selection unit 34 and outputs the result as an operation result. The control unit 38 controls the number of digits of exponent bits and mantissa bits in the digit floating-point format and the IEEE floating-point format, the overflow bit holding operation in the overflow bit holding unit 36, and the operation in the rounding operation unit 37. .

Next, the floating point multiplication device will be described. FIG. 5 is a block diagram showing an example of a conventional floating-point multiplication device. The floating point multiplication device 39 includes input units 40, 4
1, exponent operation unit 42, mantissa multiplication unit 43, normalization count unit 44, normalization unit 45, exponent correction unit 46, rounding operation unit 4
7, an output unit 48, and a control unit 49.

The input units 40 and 41 correspond to the input unit 22 of FIG.
Similarly to 23, the input floating-point numerical value is divided into exponents and mantissas. The exponent divided by the input units 40 and 41 is supplied to the exponent calculation unit 42. The exponent calculation unit 42 adds the exponents from the input units 40 and 41. The exponent added by the exponent operation unit 42 is supplied to the exponent correction unit 46.

The mantissa divided by the input units 40 and 41 is supplied to a mantissa multiplication unit 43. The mantissa multiplication unit 43
The mantissa supplied from the input units 40 and 41 is multiplied. The multiplication result in the mantissa multiplication unit 43 is supplied to a normalization unit 45. Further, the mantissa multiplication unit 43 supplies the multiplication result and the required number of times of normalization to the normalization counting unit 44. The normalization counting section 44 controls the normalization number of the normalization section 45 according to the number of normalizations supplied from the mantissa multiplication section 43, and supplies an exponent correction value to the exponent correction section 46.

The normalizing section 45 normalizes the multiplication result from the mantissa multiplication section 43 by the number of times of normalization from the normalization counting section 44 and supplies the result to the rounding operation section 47. When normalization is unnecessary, the normalization unit 45 outputs the multiplication result from the mantissa multiplication unit 43 as it is. It should be noted that the normalization unit 45 performs a digit-alignment shift in units of bits when performing an operation in IEEE floating point.

The rounding operation unit 47 performs a rounding operation on the normalized result from the normalizing unit 45. The rounding operation unit 47 includes the control unit 4
9, the rounding operation is performed at the time of the IEEE floating point operation, and the output of the normalizing unit 45 is output as it is at the time of the digit floating point operation. The output of the rounding section 47 is supplied to an output section 48. The output section 48 is supplied with the exponent from the exponent correction section 46 and the mantissa from the rounding operation section 47. The output unit 48 combines and outputs the exponent from the exponent correction unit 46 and the mantissa from the rounding operation unit 47.

Next, a conventional floating point divider will be described. FIG. 6 is a block diagram showing an example of a conventional floating-point divider. The floating-point division device 50 includes input units 51 and 52, an exponent operation unit 53, a mantissa division unit 54, a normalization count unit 55, a normalization unit 56, an exponent correction unit 57, a rounding operation unit 58, an output unit 59, and a control unit. 60.

The input units 51 and 52 correspond to the input unit 2 shown in FIG.
2, 23 and the floating point is divided into exponents and mantissas as in the input sections 40 and 41 shown in FIG. The exponent is supplied from the input units 51 and 52 to the exponent calculator 53. The exponent operation unit 53 performs exponent subtraction. The calculation result in the exponent calculation unit 53 is supplied to the exponent correction unit 57. Significand division unit 54
Are supplied with mantissas from the input units 40 and 41. The mantissa division unit 54 divides the mantissa from the input unit 40 by the mantissa from the input unit 40. The result of the division by the mantissa division unit 54 is supplied to a normalization unit 56. Further, the mantissa division unit 54 counts the number of times of normalization necessary according to the division result into a normalization count unit 55.
To supply.

The normalization counting section 55 controls the normalization number of the normalization section 56 in accordance with the number of times of normalization supplied from the mantissa division section 54 in the same manner as the normalization counting section 44 of FIG. The index correction value is supplied to the section 57. Further, the exponent correction unit 57 converts the exponent from the exponent calculation unit 53 into a normalization count unit 55 similarly to the exponent correction unit 46 in FIG.
Is corrected by the exponent correction value from. The exponent corrected by the exponent correction unit 57 is supplied to the output unit 59.

The rounding section 58 is provided with the rounding section 47 shown in FIG.
Similarly, the normalization result from the normalization unit 55 is rounded. The rounding operation unit 58 performs the rounding operation at the time of the IEEE floating point operation by the control unit 60, and outputs the output of the normalization unit 58 as it is at the time of the digit floating point operation. The output of the rounding operation unit 58 is supplied to an output unit 59. The output section 59 is supplied with the exponent from the exponent correction section 57, and is supplied with the mantissa from the rounding operation section 58. The output unit 59 is configured as shown in FIG.
, The exponent from the exponent correction unit 57 and the mantissa from the rounding operation unit 58 are combined and output.

[0031]

However, the exponent operation width and the radix of the exponent are different between the conventional digit format and the IEEE format. Due to this difference, when an arithmetic operation of the IEEE format is performed by the arithmetic device of the digit format, a digit-alignment shift in units of bits before and after the operation and a rounding operation after the operation are required.

Conventionally, the arithmetic unit of the digit type uses IEEE.
Addition, subtraction, multiplication,
Each arithmetic unit for division is provided with a digit-by-bit digit shifter and a rounding arithmetic circuit. Therefore, there is a problem that the number of gates is increased. The present invention has been made in view of the above points, and an object of the present invention is to provide an arithmetic device and a calculation device capable of calculating data in a plurality of data formats with a simple configuration.

[0033]

A first aspect of the present invention is a plurality of operation means for performing a common operation on a plurality of input data in a data format, each of which has a different operation content, and a data format of the input data. And a processing unit that is used in common in operations having different contents of the operation and performs common additional processing on data in a predetermined data format according to a result of the determination by the determining unit. It is characterized by the following.

A second aspect of the present invention provides a plurality of arithmetic means for performing different types of operations on input data, and a common additional process used in the different types of operations and commonly used in the operation process on the input data. Performing processing means. Claim 3 is a calculation method for performing a calculation on input data of at least one data format among a plurality of data formats, wherein a determination procedure for determining a data format of the input data, and a determination result in the determination procedure. The present invention is characterized by comprising an operation procedure for performing a corresponding operation, and a processing procedure for performing an additional process in an operation process in the operation procedure in accordance with a result of the judgment in the operation procedure.

According to a fourth aspect of the present invention, there is provided an arithmetic method for performing an arithmetic operation on input data, wherein an arithmetic procedure for performing a predetermined arithmetic operation by arithmetic means for performing different types of arithmetic operations on the input data; And a processing procedure for performing predetermined additional processing by processing means for performing common additional processing in the operation process in the operation procedure.

According to a fifth aspect of the present invention, there is provided a computing device having an arithmetic circuit for performing an arithmetic operation on input data of at least one data format among a plurality of data formats, wherein the arithmetic circuit operates on input data of a plurality of data formats. A plurality of operation units each performing a common operation and having different operation contents, determining means for determining the data format of the input data, and a shared use in the operation having the different operation contents; A processing unit for performing common additional processing on data in a predetermined data format in response to the processing.

According to the present invention, there is no need to perform common additional processing in each of a plurality of arithmetic means, so that the circuit configuration can be simplified. In addition, since a plurality of calculation means may execute a predetermined process, the plurality of calculation means do not cause a delay due to additional processing, and the processing can be performed efficiently.

[0038]

FIG. 7 is a schematic block diagram showing an embodiment of a computer according to the present invention. Calculation device 1 of the present embodiment
00 is the instruction control unit 101, the operation unit 10
2. It is composed of a storage control unit 103. The command control unit 101 controls the arithmetic unit 102 and the storage control unit 103 according to a command supplied from the outside.

The arithmetic unit 102 includes a floating-point arithmetic unit 104. The floating-point arithmetic unit 104 is configured as described below.
It is possible to operate on a plurality of floating point data. The storage control unit 104 stores input data and calculation results in a memory connected to the outside. Next, the floating-point arithmetic unit of this embodiment will be described in detail.

FIG. 8 is a block diagram showing a floating-point arithmetic unit according to an embodiment of the present invention. The floating point arithmetic unit 104 includes input registers 105, 10
6, addition / subtraction unit 107, multiplication unit 108, division unit 109, I
It comprises an EEE post-processing unit 110, a result selection unit 111, and a result register 112.

The input registers 105 and 106 are supplied with numerical values in floating-point format, and temporarily hold the supplied numerical values. The numerical values held in the input registers 105 and 106 are supplied to an addition / subtraction unit 107, a multiplication unit 108, and a division unit 109. The addition / subtraction unit 107 adds / subtracts the numerical values supplied from the input registers 105 and 106 as described later. The multiplication unit 108 is provided in the input register 10 as described later.
5, multiply by the numerical value supplied from 106. Division unit 10
9 divides the numerical value supplied from the input registers 105 and 106 as described later.

The IEEE post-processing unit 110 includes the addition / subtraction unit 10
7. The multiplication unit 108 and the division unit 109 are provided in common, and perform a normalization bit shift and a rounding operation necessary for calculating a numerical value in the IEEE floating point format in addition, subtraction, multiplication, and division. Next, the addition / subtraction unit 1 of the present embodiment
07 will be described in detail. FIG. 9 is a block diagram showing the arrangement of an addition / subtraction unit in an embodiment of the computing device according to the present invention. 4, the same components as those of FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted.

The adder / subtractor 107 of this embodiment is different from the adder / subtracter 21 shown in FIG.
3. A format correction unit 114 and an IEEE control unit 115 are provided. The format determination unit 113 includes the instruction control unit 101
Supplies a command control signal. The format determination unit 113
Whether the floating-point format operated according to the command control signal supplied from the command control unit 101 is a digit format,
It is determined whether the format is the IEEE format. The determination result of the format determination unit 113 is supplied to the format correction unit 114 and the IEEE control unit 115.

When the result of the determination from the format determination unit 113 is determined to be in the digit format, the format correction unit 114 supplies the 7 bits of the exponent part of the digit format to the exponent difference detection unit 25. Correct the bit length. Also,
If the result of the determination from the format determination unit 113 is determined to be the IEEE single-precision format, the format correction unit 114
9 bits of exponent part of EEE single precision format is exponent difference detector 2
5, the bit length is corrected to be supplied to the exponent difference detection unit 25 when the bit length is corrected to be supplied to the exponent difference detection unit 25. Correct the length.

The IEEE control unit 115 includes the format determination unit 11
3 according to the determination result from the IEEE post-processing unit 11
Output to 0. The IEEE post-processing unit 110 is controlled so that it operates when the information from the IEEE control unit 115 is in the IEEE format, and stops when the information is in the digit format. In FIG. 4, the output of the normalization unit 29 is supplied only to the selection unit 34, but in this embodiment, the output of the normalization unit 29 can be directly supplied to the IEEE post-processing unit 110. Further, in FIG. 4, the output of the exponent correction unit 30 is
Although supplied to only the output unit 35, in the present embodiment, the exponent correction unit 30 can be directly supplied to the IEEE post-processing unit 110. In this embodiment, the overflow bit holding unit 36 is used.
Are directly supplied to the IEEE post-processing unit 110.

Next, the multiplication unit 108 will be described in detail. FIG. 10 is a block diagram showing the arrangement of a multiplication unit according to an embodiment of the computing device of the present invention. 5, the same components as those in FIGS. 5 and 9 are denoted by the same reference numerals, and description thereof will be omitted. The multiplication unit 108 of the present embodiment has a configuration in which the rounding operation unit 47 of the multiplication unit 39 shown in FIG. 5 is deleted, and a format determination unit 113, a format correction unit 114, and an IEEE control unit 115 shown in FIG. 9 are provided. I have. Also, the multiplication unit 108 can directly supply the outputs of the exponent correction unit 46 and the normalization unit 45 to the IEEE post-processing unit 110.

Next, the division unit 109 will be described in detail. FIG. 11 is a block diagram showing the arrangement of a division unit in a computing device according to an embodiment of the present invention. 6, the same components as those in FIGS. 6 and 9 are denoted by the same reference numerals, and description thereof will be omitted. The division unit 109 of the present embodiment eliminates the rounding operation unit 58 of the division unit 50 shown in FIG. 6 and includes a format determination unit 113, a format correction unit 114, and an IEEE control unit 115 shown in FIG. Further, the division unit 109 can directly supply the outputs of the exponent correction unit 57 and the normalization unit 56 to the IEEE post-processing unit 110.

Next, the IEEE post-processing unit 110 will be described in detail. FIG. 12 is a block diagram of the IEEE post-processing unit of the embodiment of the computing device according to the present invention. The IEEE post-processing unit 110 includes a control unit 116, selection units 117 and 11,
8, bit shift number counting circuit 119, bit shifter 120, exponent correction units 121 and 122, rounding operation unit 12
3. It comprises an output unit 124.

The control section 116 is supplied with control information indicating the operation format from the IEEE control section 115 of the addition / subtraction section 107, the multiplication section 108, and the division section 109. The control unit 116
Selectors 117 and 118 and output unit 12 according to control information
4 is controlled. The selection unit 117 includes the addition / subtraction unit 107, the multiplication unit 108, and the exponent correction units 30, 46, and 5 of the division unit 109.
An index is supplied from 7. The selection unit 117 includes the control unit 11
6, the exponent correction units 30, 46, 57
Alternatively outputs the exponent from. The exponent output from the selector 117 is supplied to the exponent corrector 121.

The selection unit 118 is supplied with mantissas from the addition / subtraction unit 107, the multiplication unit 108, and the normalization units 29, 45, and 56 of the division unit 109. The selection unit 118 alternatively outputs mantissas from the normalization units 29, 45, and 56 according to a control signal from the control unit 116. The mantissa output from the selection unit 118 is supplied to the bit shift number counting circuit 119 and the bit shifter 120.

The bit shift number counting circuit 119 counts the remaining bit shift numbers of the bit shift performed on the mantissa from the selector 118. The bit shifter 120 performs a bit shift on the supplied mantissa. FIG. 13 is a diagram for explaining the bit shift operation of the embodiment of the computer according to the present invention. FIG. 13A is a diagram showing bit positions of a sign part, an exponent part, and a mantissa part of each format;
FIG. 13B is a diagram for explaining the bit shift operation.

As shown in FIG. 13A, in the IEEE single precision format, 0 bit is a sign, 1 to 8 bits are an exponent, and 9 to 1 are exponents.
Three bits become a mantissa. At this time, in the case of the IEEE single precision format as shown in FIG.
The left shift is performed so that the “bit” becomes the most significant bit. In the case of the IEEE double precision format, the right shift is performed so that the twelfth bit “11 bit” becomes the most significant bit. The output of the bit shifter 120 is supplied to the rounding operation unit 123.

The rounding operation section 123 includes a bit shifter 120
Rounds to the mantissa supplied from. The rounding operation is an operation for rounding a digit overflowed by a bit shift or the like to a predetermined bit. A control signal is supplied from the instruction control unit 101 to the rounding operation unit 123. Rounding operation unit 1
23 is turned on / off in response to a control signal. The output mantissa of the rounding operation unit 123 is supplied to the output unit 124.

The count value of the bit shift number counting circuit 119 is supplied to the exponent correction unit 121. The exponent correction unit 121 includes a bit shift number counting circuit 119
Is added or subtracted to the exponent selected by the selection unit 117 according to the shift direction, thereby correcting the exponent.
The exponent corrected by the exponent correction unit 121 is stored in the exponent correction unit 12.
2 is supplied. The exponent correction unit 122 includes the rounding operation unit 12
3 and an exponent correction value is supplied from the rounding operation unit 123. When an overflow occurs during the rounding operation, the rounding operation unit 123 supplies a correction value according to the overflow to the exponent correction unit 122. The exponent correction unit 122 corrects the exponent from the exponent correction unit 121 by adding or subtracting the correction value supplied from the rounding operation unit 123 to the exponent from the exponent correction unit 121. The output index of the index correction unit 122 is supplied to the output unit 124.

The output section 124 receives the exponent from the exponent correction section 122 and the mantissa from the rounding operation section 123. The output unit 124 combines and outputs the exponent from the exponent correction unit 122 and the mantissa from the rounding operation unit 123. A control signal is supplied from the control unit 116 to the output unit 124. The output unit 124 stops outputting when the control signal from the control unit 116 is a signal indicating a digit format. The output of the output unit 124 is the output of the IEEE post-processing unit 110. The output of the IEEE post-processing unit 110 is supplied to the selection unit 111.

The selection section 111 includes an output of the output section 35 of the addition / subtraction section 107, an output of the output section 48 of the multiplication section 108, an output of the output section 59 of the division section 109, and an IEEE post-processing section 110.
The output of the output unit 124 is supplied to the command control unit 1
One of the outputs is selectively output in response to a control signal supplied from 01. The selector 111 outputs the data from the adder / subtractor 107 at the time of digit format addition and subtraction, outputs the data from the multiplier 108 at the time of digit format multiplication, and outputs the data from the divider 108 at the time of digit format division. Output data. In addition, the selection unit 111 performs the IEEE operation in the case of the IEEE format operation.
The data from the post-processing unit 110 is output.

The data output from the selector 111 is supplied to the result register 112. Result register 112
Holds the data from the selection unit 111. According to the present embodiment, the bit shift and rounding operations of the IEEE format operation are performed collectively by the IEEE post-processing unit 110, so that the addition / subtraction unit 107, the multiplication unit 108, and the division unit 109 include the bit shifter and the rounding operation unit. Becomes unnecessary. Therefore, the configuration of the arithmetic device can be simplified.

The addition / subtraction unit 107, the multiplication unit 108, and the division unit 109 need only perform addition / subtraction, multiplication, and division, so that there is no delay due to bit shift and rounding operations during the operation, and the operation can be performed efficiently. It can be performed. Next, a specific example of the calculation will be described with reference to the drawings. FIG. 14 is a diagram showing the calculation progress of addition and subtraction in the IEEE single precision format in one embodiment of the computer of the present invention. In FIG. 14, the left column 201 shows the calculation progress at the time of addition, and the right column 202 shows the calculation progress at the time of subtraction. FIG. 15 is a diagram showing a calculation process of addition in the IEEE double precision format in one embodiment of the computer of the present invention. FIG. 16 is a diagram showing a calculation process of subtraction in the IEEE double precision format in one embodiment of the computer of the present invention.

In FIG. 14, FIG. 15, and FIG. 16, the first row L1 shows input data to the input units 22 and 23. Second
Row L2 shows the output of the exponent correction unit 114. Third row L3
Indicates the output of the exponent difference detection unit 25. The fourth row L4 shows the output of the digit matching unit 26. The fifth row L5 shows the data held in the overflow bit holding unit 36. The sixth row L6 indicates the input / output of the mantissa addition / subtraction unit 27. The seventh row L7 shows the output of the normalized number counting unit 28. The eighth row L8 indicates that the normalization unit 29
The output of The ninth row L9 shows the output of the exponent correction unit 30. The tenth row L10 indicates that the exponent correction unit 30
Exponential data supplied to post-processing section 110 and normalization section 2
9 shows mantissa data supplied to the IEEE post-processing unit 110 from No. 9.

The eleventh row L11 shows the output of the bit shift number counting section 119. The twelfth row L12 indicates the output of the bit shifter 120. The thirteenth row L13 indicates an output of the exponent correction unit 122. A fourteenth row L14 indicates an output of the rounding operation unit 123. The fifteenth row L15 includes the output unit 124
The output of FIG. 17 shows an example of the computer according to the embodiment of the present invention.
FIG. 18 is a diagram showing a calculation progress of an IEEE single-precision format multiplication, and FIG. 18 is a diagram showing a calculation progress of an IEEE double-precision format multiplication of an embodiment of the computer of the present invention.

In FIGS. 17 and 18, the first row L1 is
4 shows input data to the input units 40 and 41. 2nd row L2
Indicates the output of the exponent correction unit 114. The third row L3 shows the output of the exponent difference detection unit 42. The fourth row L4 shows the output of the mantissa multiplication unit 43. The fifth row L5 shows the output of the normalization counting unit 44. The sixth row L6 shows the output of the normalization unit 45. The seventh row L7 shows the output of the exponent correction unit 46.
The eighth row L8 shows the output of the exponent correction unit 46 and the normalization unit 45. The ninth row L9 includes a bit shift number counting unit 11
9 shows the output. The tenth row L10 includes the bit shifter 12
Indicates an output of 0. The eleventh row L11 includes an exponent correction unit 122
The output of The twelfth row L12 indicates the output of the rounding operation unit 123. The thirteenth row L13 indicates the output of the output unit 124.

FIG. 19 shows an IE of an embodiment of the computer according to the present invention.
FIG. 20 is a diagram showing the calculation progress of division in the EE single precision format, and FIG. 20 is a diagram showing the calculation progress of division in the IEEE double precision format in one embodiment of the computer of the present invention. 19 and 20, a first row L1 indicates input data to the input units 51 and 52.
The second row L2 shows the output of the exponent correction unit 114. The third row L3 shows the output of the exponent difference detection unit 53. 4th row L4
Indicates the output of the mantissa divider 54. The fifth row L5 shows the output of the normalization counting unit 55. The sixth row L6 shows the output of the normalization unit 56. The seventh row L7 shows the output of the exponent correction unit 57. The eighth row L8 shows the output of the exponent correction unit 57 and the normalization unit 56. The ninth row L9 shows the output of the bit shift number counting unit 119. The tenth row L10 shows the output of the bit shifter 120. The eleventh row L11 indicates the output of the exponent correction unit 122. The twelfth row L12 indicates the output of the rounding operation unit 123. The thirteenth row L13 indicates that the output unit 1
24 shows the output.

[0063]

As described above, according to the present invention, since it is not necessary to perform additional processing in each of a plurality of arithmetic means, there is an advantage that the circuit configuration can be simplified. Further, according to the present invention, since a plurality of arithmetic means need only execute a predetermined process, there is no delay due to additional processing in the plurality of arithmetic means, and the processing can be performed efficiently. Having.

[Brief description of the drawings]

FIG. 1 is a diagram for describing a representation of a floating point in a binary number.

FIG. 2 is a diagram for explaining a case where a numerical value in a digit floating-point format is represented by bits.

FIG. 3 is a diagram for explaining a case where a numerical value in the IEEE floating-point format is represented by bits.

FIG. 4 is a block diagram of an example of a conventional floating point addition / subtraction apparatus.

FIG. 5 is a block diagram of an example of a conventional floating-point multiplication device.

FIG. 6 is a block diagram illustrating an example of a conventional floating-point divider.

FIG. 7 is a schematic block diagram of an embodiment of a computing device according to the present invention.

FIG. 8 is a block diagram of a floating-point arithmetic unit according to an embodiment of the present invention.

FIG. 9 is a block diagram of an addition / subtraction unit of the embodiment of the calculation device of the present invention.

FIG. 10 is a block configuration diagram of a multiplication unit of one embodiment of the calculation device of the present invention.

FIG. 11 is a block configuration diagram of a division unit of one embodiment of the calculation device of the present invention.

FIG. 12 is a block diagram of an IEEE post-processing unit of a computing device according to an embodiment of the present invention.

FIG. 13 is a diagram for explaining a bit shift operation of the embodiment of the computer of the present invention.

FIG. 14 is a diagram illustrating a calculation progress of addition and subtraction in the IEEE single precision format in one embodiment of the computer of the present invention.

FIG. 15 is a diagram showing a calculation progress of addition in the IEEE double precision format in one embodiment of the computer of the present invention.

FIG. 16 is a diagram showing a calculation progress of subtraction in the IEEE double precision format in one embodiment of the computer of the present invention.

FIG. 17 is a diagram showing a calculation progress of IEEE single-precision multiplication in one embodiment of the computer of the present invention.

FIG. 18 is a diagram showing a calculation process of IEEE double-precision format multiplication of an embodiment of the computer of the present invention.

FIG. 19 is a diagram showing a calculation progress of an IEEE single-precision division in an embodiment of the computer of the present invention.

FIG. 20 is a diagram showing a calculation progress of division in the IEEE double precision format in one embodiment of the computer of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 computing device 101 instruction control unit 102 arithmetic unit 103 storage control unit 104 floating point unit 105, 106 input register 107 addition / subtraction unit 108 multiplication unit 109 division unit 110 IEEE post-processing unit 111 result selection unit 112 result register 113 type determination unit 114 format Correction unit 115 IEEE control unit 116 Control unit 117, 118 Selection unit 119 Bit shift number counting unit 120 Bit shifter 121, 122 Exponent correction unit 123 Rounding bit operation unit 124 Output unit

Claims (5)

[Claims] 1. A plurality of arithmetic means for performing a common operation on input data in a plurality of data formats, each of which has a different arithmetic content, a determining means for determining a data format of the input data, and a different arithmetic content. An arithmetic unit comprising: a processing unit that is used in common in an arithmetic operation and performs common additional processing on data in a predetermined data format in accordance with a result of the determination by the determining unit. 2. A plurality of operation means for performing different types of operations on input data, and processing means used in common in the different types of operations and performing common additional processing in an operation process on the input data. An arithmetic device comprising: 3. An operation method for performing an operation on input data of at least one data format among a plurality of data formats, comprising: a determination step of determining a data format of the input data; A calculation procedure for performing a corresponding calculation. A processing procedure for performing an additional process in a calculation process in the calculation procedure according to a determination result in the determination procedure. 4. An operation method for performing an operation on input data, comprising: an operation procedure for performing a predetermined operation by operation means for performing different types of operations on the input data; And a processing procedure for performing predetermined additional processing by processing means for performing common additional processing in a calculation process in the calculation procedure. 5. A computing device having an operation circuit for performing an operation on input data in at least one data format among a plurality of data formats, wherein the operation circuit is common to input data in a plurality of data formats. A plurality of operation units each performing a different operation, each of the operation units having different operation contents; a determination unit that determines a data format of the input data; And a processing unit for performing common additional processing on the data in the data format.