JP2001174785A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of fetching display data in addition to reduction in FPC area as far as possible for reducing the price. SOLUTION: A wiring is provided on a glass substrate in stead of an FPC, and transmission is performed via the wiring, and further, signals are transferred via the wiring on the glass substrate and the inside of a driver by providing also the driver at least with input-output pins for the signals including display data. In this case, in order to prevent differences in delay amounts caused by wiring resistance or the like from being accumulated, the signals corresponding to the display data are once synchronized in the driver before being outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a transmission system in which wiring is provided on a liquid crystal display panel and at least a part of control signals and display data are transmitted inside an electrode driving circuit of the liquid crystal panel. It is another object of the present invention to provide a liquid crystal display device having a transmission method capable of transmitting data regardless of the resistance of wirings and connection portions and the characteristics of transistors forming the electrode driving circuit.

[0002]

2. Description of the Related Art In a conventional liquid crystal display device, at least two sides of a liquid crystal display panel, a drain electrode driving circuit (hereinafter referred to as a drain driver) for driving respective electrodes, and a gate electrode driving circuit (hereinafter referred to as a gate driver). )
Place. Hereinafter, a configuration of a TFT liquid crystal module in which a TFT is arranged in a pixel portion will be described with reference to FIG.

FIG. 13 is a diagram showing a part of a conventional liquid crystal display module.
02 is the upper glass surface, 1303 is the lower glass substrate, 13
A control circuit board 04 outputs control signals, display data, and voltages necessary for driving the liquid crystal panel. Reference numeral 1305 denotes a drain-side flexible printed circuit board (hereinafter, abbreviated as a drain-side FPC) that transfers signals and voltages necessary for driving the drain electrode among the signals and voltages generated by the control circuit board 1304 to a drain driver.
It is.

A drain driver 1306 drives a drain electrode of the liquid crystal panel, and generates a drain voltage according to a signal and a voltage transferred from the control circuit board 1304. Reference numeral 1307 denotes a drain line connected in the column direction to a drain electrode of a TFT element arranged in each pixel of the liquid crystal display panel.

[0005] Here, in the notation of the drain driver 1307 and the drain line, the subscript 1 is added to the first drain driver in the order in which the display data is transferred from the control board.
The subscript 2 is sequentially added to the second drain driver. Reference numeral 1308 denotes a gate-side flexible printed circuit (hereinafter, abbreviated as gate-side FPC) that transfers signals and voltages necessary for driving the gate electrode among the signals and voltages generated by the control circuit board 1304 to the gate driver IC. A gate driver 1309 drives a gate electrode of the liquid crystal panel, and generates a gate voltage according to a signal and a voltage transferred from the control circuit board 1304. 1310 is a gate line. The gate driver and the gate line are also suffixed similarly to the drain driver and the drain line.

Next, the operation will be described. In accordance with input data from an external system (not shown), the control circuit board 1304 generates a signal and a voltage necessary for driving the drain electrode and a signal and a voltage required for driving the gate electrode. The generated voltages and signals are supplied to the drain driver 1306 through the drain-side FPC 1305 and to the gate driver 1309, respectively.
The transfer is performed via C1308 and the upper glass surface 130
2. The display color is controlled by applying a drain voltage and a gate voltage to the liquid crystal layer held between the lower glass surfaces 1303, respectively.

As a liquid crystal display device having such a configuration,
For example, JP-A-10-268838 is known.

[0008]

In the conventional method of transferring all signal lines via the FPC, the cost of the FPC member is required, and this portion causes a rise in the price of the liquid crystal display device. . As a method of solving this, when transferring signals such as display data and grayscale voltages, FP
Instead of using C, wiring may be formed on a glass substrate or inside a driver IC chip, and transfer may be performed using this.

However, materials that can be formed on a glass substrate are generally Cr, Mo, Ta, Al, or alloys thereof, and have a higher resistance than Cu used in FPC. Would. Further, when the above-described configuration is used, it is necessary to join the wiring on the glass substrate and the driver IC, but this portion is joined by pressure bonding, and there is a problem that the resistance value varies.

Here, the problem caused by the variation in the resistance value will be described with reference to FIG. FIG. 14 is a diagram showing the relationship between the transfer signal and the display data. It is assumed that the display data is taken into the drain driver IC in synchronization with the rise / fall of the transfer clock. Tsu
1, Tsu2 is setup time, Toh1, Toh2
Indicates a hold time. When the suffix is 1, the timing does not deviate, and when the suffix is 2, the timing deviates.

Now, when the resistance value of the wiring is large, it is assumed that a delay occurs in the transfer signal that defines the timing for fetching the display data as in the case where the subscript is indicated by 2 due to the difference between the wiring resistance and the wiring capacitance. In this case, as shown in FIG.
In the hold time of Tsu2, the display data depends on the next display data, and accurate display data cannot be acquired. Therefore, a display screen different from a desired display may be obtained.

Further, when the data is sequentially transferred within the driver as described above, even if the first driver can capture the display data, the delay time caused by the first driver is generated. Since the differences are sequentially accumulated by passing through the drivers, a large deviation occurs in the display data transferred through all the drivers.

An object of the present invention is to provide a liquid crystal display panel having a data transfer method for arranging a signal line on a glass substrate and satisfying a setup / hold time even when a resistance value of the signal line is large. The purpose is to:

[0014]

In order to solve the above-mentioned problems, a drain driver in a liquid crystal display device of the present invention generates a reference clock inside the driver, and outputs a signal corresponding to display data including a transfer signal to the reference signal. Provides means for latching. Here, the reference signal is generated by generating an n-multiplied signal internally based on a single signal and a method of generating an n-multiplied signal inside the driver based on n signals having different phases. Becomes possible.

By using the above configuration, the output of the display data once captured in the driver does not cause the phase of the transfer signal to be shifted from that of all the display data. Can be captured.

Further, when viewed from the control circuit board, display data is not transferred to a driver that is located at a farther end electrically than a driver that is taking in data, thereby reducing power consumption. Aim for reduction.

[0017]

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a diagram showing transmission timing in the first embodiment, and each signal has a role described later.

FIG. 2 is a diagram showing a part of a wiring method in the liquid crystal module of the first embodiment.

Reference numeral 201 denotes a part of the liquid crystal module. In this embodiment, the display area of the liquid crystal module 201 has 3072 (1024 × RGB) drain lines and 768 gate lines. . 202 is an upper glass surface, 203 is a lower glass surface, holds liquid crystal between the two glass surfaces, has a drain line and a gate line between them, and controls the voltage applied to the drain line and the gate line. The display color is controlled accordingly. A control circuit board 204 outputs a control signal, display data, and voltage necessary for driving the liquid crystal panel based on an external input. 205 is the control circuit board 20
4 is a drain-side FPC 205 that transfers signals and voltages necessary for driving the drain electrode to the drain driver IC among the signals and voltages generated in step 4.
, And a drain-side wiring provided on the lower glass substrate to transfer the signal transferred via the first glass substrate to the first drain driver in the order in which one line of display data is transferred. , And the subscript 2 is sequentially added to the input of the second drain driver. A drain driver 207 drives a drain electrode of the liquid crystal panel, and generates a drain voltage according to a signal and a voltage transferred from the control circuit board 204. The notation of the drain driver 207 indicates that the first drain driver has a suffix 1 like the wiring.
, And the subscript 2 is sequentially added to the second drain driver. Further, it is assumed that the drain driver 207 in this embodiment has 258 output voltage lines,
Therefore, it is assumed that the drain driver is constituted by 12 drain drivers from 3072 ÷ 258.

Reference numeral 208 denotes a drain line, and 258 drain lines are connected as a set to one drain driver. Reference numeral 209 denotes a gate-side FP that transfers signals and voltages necessary for driving the gate electrode among the signals and voltages generated by the control circuit board 204 to the gate driver IC.
C and 210 are gate-side wirings provided on the lower glass substrate for transferring signals and gate voltages transferred through the gate-side FPC 209, and are sequentially added with subscripts like the drain-side wirings. A gate driver 211 drives a gate electrode of the liquid crystal panel, and generates a gate voltage according to a signal and a voltage transferred from the control circuit board 204. The designations of the gate drivers are also sequentially numbered, and the gate driver 211 in this embodiment has 256 output voltage lines, so that the drain driver is 768 ÷ 256 to 3
It is assumed that the gate driver is constituted by a plurality of gate drivers. Reference numeral 212 denotes a gate line, which is connected to one gate driver as a set of 256 gate lines.

FIG. 3 shows the relationship of the transmission signals on the drain side, among the wiring methods shown in FIG. 301
Is a power supply voltage that is always applied via the drain-side FPC 205, and is a power supply serving as a reference when driving the drain driver. Reference numeral 302 denotes an enable signal, and the enable signal 302 is a signal indicating an input period of display data.
As shown in the timing diagram of FIG.
When the input enable signal 07 becomes high level, the capture of the display data starts from the rising edge of the next transfer signal, and when the capture of the 258 drain lines is completed, the output enable signal is changed from low level to high level. Indicates that data transfer to the next stage drain driver is valid. A transfer signal 303 captures display data at both rising and falling edges of the transfer signal 303. Reference numeral 304 denotes display data. In this embodiment, a plurality of bits (for example, 6 bits) correspond to data of one drain line, and data of three drain lines are transferred at the same time. An inversion signal 305 changes the polarity of the output voltage applied to the drain voltage according to the polarity of the inversion signal. Reference numeral 306 denotes an output signal, and a voltage according to the display data stored at the fall of the output signal is applied to the drain line. Reference numeral 307 denotes a gradation voltage which is constituted by a plurality of voltage lines and determines a voltage value to be applied to the drain voltage 208.

FIG. 4 is a diagram showing the configuration of the drain driver in the first embodiment. Here, the first drain driver 207-1 is assumed, but the meaning of the subscript is not particularly specified. In the figure, reference numerals 301 to 307 are the same as those shown in FIG.

Reference numeral 401 denotes a phase comparison circuit, and 402, a loop filter.
A phase difference between signals is detected, and a voltage value is generated based on the detection result.

Reference numerals 403 and 404 denote delay circuits for generating equal delay values. 405 and 406 are inverting circuits,
7 is an exclusive OR circuit. 408 and 409 are latch circuits. 410 is an address selector, 411 is a latch circuit A, 412 is a latch circuit B, and 413 is an output circuit. 414-1 and 414-2 are phase delay signals, respectively.
It detects a phase difference between two signals input to the phase difference comparison circuit 401 and detects how much the other signal is shifted from the transfer signal 303-1 side.

Reference numeral 415 denotes a bias voltage. The loop filter 414 outputs a phase delay signal 414-1 and a phase advance signal 44-1.
According to 14-2, a bias voltage 415 is generated. 41
6, a delay signal A generated by delaying the transfer signal 303-1 by the delay circuit 403; a delay signal B 417 generated by delaying the delay signal A 416 by the delay circuit 404;
418 is an inverted signal of the delay signal B417. 419 is a latch signal generated by performing an exclusive OR operation on the transfer signal 303-1 and the delay signal A416 by the exclusive OR circuit 407, and 420 is an inverted signal of the latch signal 419. 421, a data latch signal generated by the address selector 410;
During the period when the enable signal 302-1 is valid,
By sequentially shifting the latch signal 419, the data latch signal 421 is generated, and at the same time, all 256 data latch signals (in this case, 86 types because three display data are input at the same time) are generated. Then, the enable signal 302-2 transferred to the next stage is enabled by setting it to a high level. Reference numeral 422 denotes a latch circuit A 411 which displays the display data 30 based on the data latch signal 421.
The latch display data A and 423 obtained by latching 42-2 are output from the latch circuit B 412 based on the output signal 305.
The latch display data A 422 is latch display data B latched, and the output circuit 413 outputs the latch display data 4
A voltage value based on 23 and the inverted signal 305 is selected and generated from the gray scale voltage, and output to the drain line 208.

FIG. 5 is a diagram showing the relationship between the phase comparison circuit 401 and the loop filter 402. The phase of the inverted signal 418 of the delay signal B with respect to the transfer signal 303-1 is advanced, the phase is the same, and the phase is delayed. When the phase lead signal 4
14-1, phase delay signal 414-2 and bias voltage 41
5 shows the relationship of FIG.

FIG. 6 shows a delay circuit 40 composed of CMOS.
3 is an example showing the configuration of 404, where IN is input, OU
T is an output, and according to the voltage level of the bias voltage,
The value of the current flowing through the circuit can be controlled, and the amount of delay is controlled accordingly.

FIG. 7 is a diagram showing the phase relationship between the transfer signal and the input / output of the display data in the case of using this embodiment.

The operation of the present embodiment will be described in detail with reference to the above drawings. First, a method for generating the transfer signal 303-2 from the transfer signal 303-1 will be described with reference to FIGS.
This will be described with reference to FIG.

The transfer signal 303-1 input to the drain driver 207-1 shown in FIG. 4 includes the transfer signal 303-1 by the phase difference comparator 401 and the inverted signal 418 of the delay signal B417 delayed by the delay circuits 403 and 404. And a phase lead signal 414-1 and a phase delay signal 414-2 are generated. The phase advance signal 414-1 and the phase delay signal 414-2 are obtained by calculating the phase difference between two input signals as shown in FIG. The phase lead signal 414-1 and the phase delay signal 414-2 generated in this way.
Based on the bias voltage 415
Generate The bias voltage 415 is the transfer signal 303-1.
When the phase of the signal 418 is delayed, the voltage level is lower than when the phase is advanced.

At the same time, the transfer signal 303-1 is supplied to the delay circuit A4.
03. A delay signal B417 is generated via the delay circuit B404. Here, both the delay circuits A and B are constituted by circuits having the same configuration as shown in FIG. 6, and if the bias voltage 415 is appropriate, the delay circuits A and B become 90% with respect to the input frequency.
It is designed to produce a degree of phase lag. Therefore, for the transfer signal 303-1, the delay signal A416
Is delayed by 90 degrees, the delayed signal B417 is delayed by 180 degrees, and the inverted signal 418 is delayed by 360 degrees in phase, ie, 303-1.
And 418 have no phase difference. Now, it is assumed that the bias voltage is not appropriate and a phase delay of 95 degrees occurs due to a delay circuit. In this case, the delay signal A 416 is delayed by 95 degrees, the delay signal B 417 is delayed by 190 degrees, and the inverted signal 418 is delayed by 370 degrees and delayed by 10 degrees. In this case, the loop filter 402 increases the voltage level of the bias voltage 415 from the output of the phase comparison circuit 401 based on the phase delay signal.
As a result, the gate voltage of the N-MOS of the delay circuit shown in FIG. 6 increases, so that the current value increases, and the phase lag from 95 degrees is optimized to 90 degrees. By performing the above-described feedback operation, the delay signal A416 becomes a signal delayed by 90 degrees from the transfer signal 303-1, and the latch signal 419 obtained by performing an exclusive OR operation of the two signals becomes the transfer signal 303-1. It becomes a signal that is a double of -1.

The latch signal 41 thus generated
9, the subsequent operations are performed. That is, the processing after latching the input display data is the same as in the conventional example.
Also, as shown in FIG. 1, the transfer signal 303-1 is generated by latching the transfer signal 303-1 at the falling edge of the latch signal 419. Similarly, the display data 304-2 is generated by latching the display data 304-1 at the rising edge of the latch signal 419. The transfer signal 303-2 and the display data 304-2 generated as described above.
Is equivalent to the relationship between 303-1 and 304-2, and is a relationship in which the phases of the inputs 303-1 and 304-1 are delayed by 90 degrees.

Next, the effect of the present embodiment when the phase relationship between the transfer signal and the display data is shifted will be described with reference to FIG.

Now, the transfer signal 303-1 is the display data 30
The case where the display data is delayed as shown in FIG. 7 is considered as a place where the rising / falling point should be located at the center in the data defined area 4-1.

At this time, the latch signal 419 becomes the transfer signal 3
Therefore, the change point of the latch signal 419 is approximately 0 degree, 9 degrees with respect to the rising edge of the transfer signal.
They come at 0, 180 and 270 degrees. Here, the transfer signal is the falling of the latch signal 419, that is, 90 degrees and 2
Latching is performed at a position of 70 degrees to generate a transfer signal 303-2, and display data 305-1 is latched at positions of 0 and 180 degrees to obtain display data 305-2. Therefore, if the transfer signal 303-1 and the display data 305-1 can be latched by the latch signal 419, the output can maintain the setup / hold time again, and the delay amount is accumulated every time the signal passes through the drain driver. Never.

(Embodiment 2) Next, as a second embodiment, a method in which a plurality of transfer signals having different phases are used so that the delay amount is not integrated even through a drain driver will be described with reference to FIGS. Will be explained.

FIG. 8 is a diagram showing the configuration of the drain driver in the second embodiment. The entire configuration is the same as that shown in FIG. 2, and the meanings of the subscripts are also the same. 801
Denotes a drain driver, and 802 denotes a power supply voltage always applied via the drain-side FPC, which is a power supply serving as a reference when driving the driver. Reference numeral 803 denotes an enable signal. The enable signal 803 is a signal indicating an input period of display data. When the input enable signal of the drain driver 207 goes to a high level, the capture of display data starts from the next rising edge of the transfer signal. , 25
When the capture of the eight drain lines is completed, the output enable signal is changed from the low level to the high level. 804 is a transfer signal A, 805 is a transfer signal B,
The transfer signal B has the same frequency as the transfer signal A,
It is a signal whose phase is delayed. Reference numeral 806 denotes display data. In this embodiment, a plurality of bits (for example, 6 bits) correspond to data of one drain line, and data of three drain lines are transferred at the same time.
It is also assumed that the data change at 806 occurs at the rise / fall of the transfer signal B 805, and the rise / fall of the transfer signal A 804 occurs at the center of the data change. An inverted signal 807 changes the polarity of the output voltage applied to the drain voltage according to the polarity of the inverted signal. Reference numeral 808 denotes an output signal, and a voltage according to the display data stored at the falling edge of the output signal is applied to the drain line. Reference numeral 809 denotes a gradation voltage, which is constituted by a plurality of voltage lines and determines a voltage value to be applied to the drain voltage 801.

FIG. 9 is a diagram showing the configuration of the drain driver according to the second embodiment. Here, the first drain driver 801-1 is assumed, but the meaning of the subscript is not particularly specified. In the figure, reference numerals 802 to 809 are the same as those shown in FIG. 901 is an exclusive OR circuit, 902 is an inverting circuit, 903 and 904 are latch circuits, 905 is an inverting circuit, and 906 and 907 are latch circuits. 908, a latch signal generated by the exclusive OR circuit 901; 909, an inverted signal of the latch signal; 910, a transfer signal A804-1, latched by the latch circuit 903 based on the inverted signal 909; Are transfer signals B8042 latched based on the latch signal 908.
The other parts are not different from those of the first embodiment, and therefore, will not be described again in this embodiment, and only the transfer of the transfer signal and the display data will be described.

FIG. 10 is a diagram showing transmission timing in the second embodiment.

The operation of this embodiment in the second embodiment will be described in detail with reference to the above drawings. In FIG. 8, a transfer signal A804-
1. The exclusive OR operation is performed on the transfer signal B805-1 in the first stage drain driver 801-1 to generate the latch signal 908. As shown in FIG. 10, the transfer signal A 804-1 and the transfer signal B 805-1 have a 90 degree phase lag with respect to the 804-1 as shown in FIG. Becomes a double frequency which changes at the rise / fall of the signal. The latch signal 910 thus generated is used as a reference clock in the internal circuit of the drain driver. That is, the transfer signal A 804-1 converts the latch signal 910 into the inversion circuit 902.
By latching at the falling edge of the latch signal 910, a signal 911 delayed by 90 degrees is obtained. This signal is inverted by the inverting circuit 905 to obtain a signal delayed by 270 degrees from the transfer signal A804-1, and this signal is referred to as a transfer signal B805-2. Similarly, the transfer signal B805-1 is latched at the rising edge of the latch signal 910 to obtain a signal 912 delayed in phase by 90 degrees.
This is referred to as a transfer signal A804-2. On the other hand, in the display data 806, the phase is delayed by 90 degrees in terms of the transfer signal by latching with the latch signal 910 in the latch circuit 908 first, and the latch signal 91 is inverted by inverting the latch signal in the inversion circuit 907.
Latching is performed at the falling edge of 0, and as a result, the phase is delayed by 180 degrees. That is, each of the phase delays with respect to the transfer signal A804-1 is referred to as the transfer signal A804-1.
2: 90 + 90 degrees = 180 degrees, transfer signal B804-2:
270 degrees, display data: 180 degrees, and the transfer signal A
804-2, transfer signal B805-2, display data 806
The relationship of -2 is as shown in FIG.
1, the transfer signal B805-1 and the display data 806-1 become equal, and the drive can be performed without being aware of the number of stages in which the drain driver is located. Transfer signal A804
-1 becomes the transfer signal B805-2 in the second stage,
Conversely, the transfer signal B805-1 which is the input in the first stage becomes the transfer signal A804-2 in the second stage, that is, the system A and the system B cross each time through the driver. Therefore, it is possible to further cancel the difference between the rising slew rate and the falling slew rate without integrating the difference in the delay amount through the latch circuit.

(Embodiment 3) Next, as a third embodiment, a period in which a transfer signal and display data irrelevant to the drain driver of the succeeding stage and display data are transferred to display data sequentially transferred is provided. A method for reducing power consumption by setting a transfer signal and display data to a high impedance state will be described with reference to FIGS. Note that the connection relationship between the drivers in this embodiment is the same as that in FIG. 8 shown in the second embodiment.

FIG. 11 is a diagram showing the configuration of the drain driver according to the third embodiment.
Are the same as those shown in FIG. 1101 is an exclusive OR circuit, 1102 is an inverting circuit, 1103 and 1104 are latch circuits with a stop signal input terminal, 1105 is an inverting circuit, 1106 is a latch circuit, and 1107 is a latch circuit with a stop signal input terminal. 1108 is a latch signal generated by the exclusive OR circuit 1101, 1109 is an inverted signal of the latch signal 1108, 1110 is a latch circuit 110
The transfer signal A804-1, 1111 latched based on the inverted signal 1109 of the latch signal in step 3 is a latch circuit 1104.
, The transfer signal B8 latched based on the latch signal 1108
05-1. Reference numeral 1112 denotes a latch address selector, which includes an enable signal 803-1 and a latch signal 1108.
Address and output enable signal 803 based on the
Generate 2.

The other parts are not different from those of the first embodiment, and therefore, will not be described again in this embodiment, and only the transfer of the transfer signal and the display data will be described.

FIG. 10 is a diagram showing the transmission timing in the second embodiment.

The third embodiment will be described in detail with reference to the above drawings. Transfer signals A804-1, B805-
2 is subjected to an exclusive OR operation by an exclusive OR circuit 1101 to generate a latch signal 1108. here,
As shown in FIG. 12, the transfer signals A804-1 and B805-2 are input only while the enable signal 803-1 input to the first-stage drain driver is at a high level. Further, the display data 806-1 includes an enable signal 1103-
The first transfer signal A after 1 becomes valid (high level)
At the rise of 804-1, setup / display data D1 to D3 of the column to be fetched first
Satisfy the hold time.

The method of generating the latch signal 1108 from the transfer signal is the same as in the second embodiment.

That is, an exclusive OR operation is performed in the exclusive OR circuit 1101 to generate a latch signal 1108. Display data is captured based on the latch signal 1108 generated in this manner.

Next, generation of the enable signal 803-2 will be described. The address selector 1107 controls the latch signal 110 during the period when the enable signal 803-1 is valid.
8 is counted, and a data latch signal 1110 is generated. Here, the address selector 1107 outputs the enable signal 803
After the circuit is enabled by −1, the latch signal 11
08 for 86 clocks, the next latch signal 10
By raising the enable signal 803-1 at the falling edge of No. 8, the latch circuits 1103 to 1105 are enabled, and the transfer signal A804- to the next-stage drain driver is enabled.
2, B805-2, and display data are transferred.

[0050]

As described above, according to the present invention, the following effects can be obtained.

By adopting the configuration described in the first embodiment, it is possible to generate a doubled reference signal based on one input transfer signal. Therefore, the internal operation is performed based on the reference signal, and the output signal having the frequency corresponding to the display data is output after synchronizing with the reference signal. The difference in the delay time integrated in the driver can be absorbed inside the driver, and the delay amount is not integrated.

Further, by adopting the configuration described in the second embodiment, it is possible to internally generate a multiplied signal of the transfer signal based on the two-input transfer signal, and to reduce the multiplication signal inside the driver. Since synchronization is performed using signals, the difference in delay time accumulated between the driver output of the preceding stage and the driver of the own stage can be absorbed in the driver, as in the first embodiment, and the delay amount is accumulated. I will not go.

By adopting the configuration described in the third embodiment, it is possible to stop data transfer from the control circuit board to the drain driver located at the far end, thereby reducing power consumption. It becomes possible to plan.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating transmission timing according to a first embodiment.

FIG. 2 is a diagram showing a part of a wiring method in the first embodiment.

FIG. 3 is a diagram showing a relationship between drain-side transmission signals in the first embodiment.

FIG. 4 is a diagram illustrating a configuration of a drain driver according to the first embodiment.

FIG. 5 is a diagram illustrating a relationship between a phase comparison circuit and a bias voltage.

FIG. 6 illustrates a configuration of a delay circuit.

FIG. 7 is a diagram showing timing when the phase of an input signal is shifted.

FIG. 8 is a diagram illustrating a relationship between drain-side transmission signals according to the second embodiment.

FIG. 9 is a diagram illustrating a configuration of a drain driver according to a second embodiment.

FIG. 10 is a diagram showing transmission timing in the second embodiment.

FIG. 11 is a diagram illustrating a configuration of a drain driver according to a third embodiment.

FIG. 12 is a diagram showing transmission timing in the third embodiment.

FIG. 13 is a diagram showing an example of a conventional transfer timing.

FIG. 14 is a diagram showing a relationship between a transfer clock and display data.

[Explanation of symbols]

201: liquid crystal module, 202: upper glass surface, 20
3 lower glass surface, 204 control circuit board, 2
05: Drain side FPC, 206: Drain side wiring provided on the lower glass substrate, 207: Drain driver, 208: Drain line, 209: Gate side FPC, 2
10: gate side wiring, 211: gate driver, 212
... Gate line, 301 power supply voltage, 302 enable signal, 303 transfer signal, 304 display data, 305
Inversion signal, 306: output signal, 307: gradation voltage, 40
1: phase comparison circuit, 402: loop filter, 403:
Delay circuit, 404 delay circuit, 405 inversion circuit, 40
6, an inverting circuit, 407, an exclusive OR circuit, 408, a latch circuit, 409, a latch circuit, 410, an address selector, 411, a latch circuit A, 412, a latch circuit B,
413 output circuit, 414-1 phase delay signal, 414
-2: phase lead signal, 415 ... bias voltage, 416 ...
Delay signal A, 417 ... Delay signal B, 418 ... Delay signal B
Inversion signal 417, Latch signal, 420 Latch signal, Inversion signal of 419, 421 Data latch signal, 422 Latch display data A, 423 Latch display data B, 801 Drain driver, 802 Power supply voltage 803: enable signal, 804: transfer signal A, 8
05 ... Transfer signal B, 806 ... Display data, 807 ... Inversion signal, 808 ... Output signal, 809 ... Grayscale voltage, 901 ...
Exclusive OR circuit, 902 inverting circuit, 903 latch circuit, 904 latch circuit, 905 inverting circuit, 906
... inverting circuit, 907 ... inverting circuit, 908 ... latch circuit,
909: latch circuit, 1101: exclusive OR circuit, 1
102: inverting circuit, 1103: latch circuit with input terminal, 1104: latch circuit with input terminal, 1105: latch circuit with input terminal, 1106: inverting circuit, 1107
... Latch circuit, 1108 ... Address selector, 1109
.. Latch signal, 1110 Stop signal, 1111 Data latch signal, 1301 Liquid crystal module, 1302 Upper glass surface, 1303 Lower glass substrate, 1304 Control circuit substrate, 1305 Drain side FPC, 1
306: drain-side wiring provided on the lower glass substrate, 1307: drain driver, 1308: drain line, 1309: gate-side FPC, 1310: gate-side wiring provided on the lower glass substrate, 1311: gate driver , 1312 ... Gate line.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hirofumi Koshi 3300 Hayano, Mobara City, Chiba Prefecture Within Hitachi, Ltd. Display Group (72) Inventor Masaaki Kitajima 3300 Hayano, Mobara City, Chiba Prefecture, Hitachi, Ltd. 72) Inventor Satoru Tsunekawa 5-20-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 2H093 NA51 NC26 NC59 ND39 ND46 ND60 5C006 AA16 AF61 BB16 BF04 BF07 BF14 BF21 BF26 FA37 FA41 FA47 FA51 FA56 GA03 5C080 AA10 BB05 DD22 DD27 FF11 JJ02 JJ04 5C094 AA21 AA22 AA53 AA55 AA56 BA03 BA43 CA19 DA13 DB01 DB02 DB04 EA04 EA10 EB02 FA01 FA02 FB12 FB14 FB15 GA10

Claims (7)

[Claims] An active matrix type liquid crystal display panel in which switching elements and liquid crystals are arranged in a matrix in each pixel portion, display data is input, and a gradation voltage corresponding to the input display data is generated. A plurality of drain electrode driving circuits for applying the display data to the corresponding pixel units in the horizontal direction; and sequentially selecting any one of the pixel units arranged in the vertical direction, and selecting the selected pixel unit. Apply voltage,
A gate electrode driving circuit that applies a non-selection voltage to a pixel unit that is not selected; and a control circuit that generates display data, a control signal, and a gray scale voltage for driving the liquid crystal display panel, The liquid crystal has a common electrode common to the respective pixel units on one side, and when a selection voltage output from the gate electrode driving circuit is applied to the switching element of the pixel unit, the liquid crystal is generated by the drain electrode driving circuit. In a liquid crystal display that applies a gray scale voltage to the liquid crystal and controls display brightness with an effective voltage value of the gray scale voltage with respect to a common electrode, the plurality of drain electrode driving circuits each include at least display data and a control signal. It has an input terminal and an output terminal,
The input terminal of each drain electrode drive circuit is connected to the output terminal of the drain electrode drive circuit including the output terminal of the control circuit, respectively, and the display data and the control signal having a period substantially equal to the display data once in the drain electrode drive circuit. Having a drain electrode driving circuit for latching at least once by a clock of the same signal line so that the phase relationship between output signals from any of the drain electrode driving circuits becomes equal. Display device. 2. The liquid crystal display device according to claim 1, wherein the capture of the display data is determined based on the rise and fall of the transfer signal. 3. The liquid crystal display device according to claim 1, wherein the plurality of drain electrode driving circuits have a delay circuit for a transfer signal, and are determined by an operation result of the transfer signal and a transfer signal delayed by the delay circuit. A liquid crystal display device characterized in that display data is taken in by a given signal. 4. The delay circuit according to claim 3, wherein a phase delay of approximately x degrees is generated with respect to the transfer signal, and a total of approximately xy degrees of phase delay is generated by connecting y number of the delay signals. A liquid crystal display device comprising: comparing a transfer signal with a signal whose phase is delayed by xy degrees with respect to the transfer signal; and setting the delay amount of the delay circuit to 180 degrees or 360 degrees based on the comparison result. . However, it is 360 when xy = 180 or younger. 5. An active matrix type liquid crystal display panel in which switching elements and liquid crystals are arranged in a matrix in each pixel portion, display data is input, and a gradation voltage corresponding to the input display data is generated. A plurality of drain electrode driving circuits for applying the display data to the corresponding pixel units in the horizontal direction; and sequentially selecting any one of the pixel units arranged in the vertical direction, and selecting the selected pixel unit. Apply voltage,
A gate electrode driving circuit that applies a non-selection voltage to a pixel unit that is not selected; and a control circuit that generates display data, a control signal, and a gray scale voltage for driving the liquid crystal display panel, The liquid crystal has a common electrode common to the respective pixel units on one side, and when a selection voltage output from the gate electrode driving circuit is applied to the switching element of the pixel unit, the liquid crystal is generated by the drain electrode driving circuit. In a liquid crystal display that applies a grayscale voltage to the liquid crystal and controls display luminance with an effective voltage value of the grayscale voltage with respect to the common electrode, each of the plurality of drain electrode driving circuits includes at least display data and a control signal. Has an input terminal and an output terminal,
The input terminal of each drain electrode drive circuit is connected to the output terminal of the drain electrode drive circuit including the output terminal of the control circuit, respectively, and has at least two types of signals for taking in display data into the drain electrode drive circuit and determining timing. Characteristic liquid crystal display device. 6. The liquid crystal display device according to claim 5, wherein the signals determining the at least two types of capture timings have substantially the same period and different phases. 7. The liquid crystal display device according to claim 1, wherein, in a display data fetching operation performed sequentially, the drain is electrically connected to a drain electrode driving circuit far from the control circuit. The liquid crystal display device according to claim 1, wherein the transfer of the display data is not performed until the transfer of the display data related to the drain line connected to the electrode driving circuit is performed.