JP2011085663A - Driving circuit and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit capable of more stably controlling a voltage for driving the transistor of a display device. <P>SOLUTION: When a clock signal V<SB>i</SB>becomes high, a transistor T5 is made conductive by an output G<SB>i-4</SB>, thereby setting a potential of one electrode of a capacity C1 high. Hence, a gate potential of the transistor T5 which is the other electrode side is increased by bootstrap, and an output G<SB>i</SB>becomes high. Then, during a writing period after the passage of three horizontal synchronous periods, data signal voltages based on gradation values of respective pixels are applied to data signal lines D<SB>1</SB>to D<SB>m</SB>, and the output G<SB>i</SB>falls to hold the applied voltages based on the gradation values in the pixels. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a drive circuit and a display device using the drive circuit.

  Liquid crystal display devices are widely used as display devices for information communication terminals such as computers and television receivers. An organic EL display device (OLED), a field emission display device (FED), and the like are also known as display devices.

  The liquid crystal display device changes the orientation of the liquid crystal composition enclosed between two substrates by changing the electric field, and controls the degree of transmission of light passing through the two substrates and the liquid crystal composition to display an image. It is a device to display.

  In a display device that applies a voltage corresponding to a predetermined gradation value to each pixel of the screen, including such a liquid crystal display device, a pixel transistor for applying a voltage corresponding to the gradation value is arranged in each pixel. ing. In general, the gate lines of the pixel transistors for one line of the screen are connected to one signal line (referred to as “scanning line”). It is controlled to output an active signal for conducting.

  Patent Document 1 shows an example of such a shift register in which active / inactive of each line is stably controlled.

JP 2007-95190 A

  In a display device such as a liquid crystal display device, one horizontal synchronization period tends to be shortened due to the recent high definition of the screen. For example, in the case of a frame frequency of 60 Hz, the horizontal synchronization period is 20.4 μs in the case of 816 gate lines, but it is 17.1 μs in the case of 976 gate lines. Thus, when the horizontal synchronization period is shorter, one output of the shift register does not have time to make the gate lines of the transistors of all the pixels for one line of the screen have sufficient potential, and remains at insufficient potential. There is a risk of applying a gradation voltage or the like. If a gray scale voltage is applied with an insufficient potential on the gate line, the source and drain are not sufficiently connected, so the potential corresponding to the gray scale value is not transmitted to each pixel, resulting in image quality degradation. Will be invited.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a drive circuit that more stably controls a voltage for driving a pixel transistor of a display device, and a display device using the drive circuit. To do.

  The drive circuit according to the present invention is a drive circuit for a display device that sequentially outputs active signals for conducting transistors to a plurality of signal lines, and includes a plurality of output circuits respectively connected to the plurality of signal lines. Each of the output circuits continues to output the active signal for four horizontal synchronization periods of the display device.

  Here, the active signal means a signal having a potential for conducting between the source and drain of the transistor when inputted to the gate of the transistor. In the case of an NMOS type transistor, the active signal is a signal having a high potential. In the case of a type transistor, it means a signal having a low potential. On the other hand, the negative signal means a gate signal that interrupts between the source and drain of the transistor.

  In the driving circuit according to the present invention, the plurality of output circuits may output one output circuit that is one of the plurality of output circuits, at a timing four horizontal synchronization periods before the output timing of the output circuit. An output of the preceding output circuit is input to the output circuit as a timing signal for outputting the active signal. can do.

  In the driving circuit according to the present invention, the plurality of output circuits may output an output circuit that is one of the plurality of output circuits at a timing four horizontal synchronization periods after the output timing of the output circuit. An output of the subsequent output circuit is input to the output circuit as a timing signal for outputting a negative signal to the output circuit. be able to.

  The drive circuit according to the present invention further includes a plurality of negative signal output circuits arranged opposite to the plurality of output circuits with the display area of the display device interposed therebetween, and connected to the plurality of signal lines, respectively. Each of the plurality of negative signal circuits receives the output of the active signal of the corresponding plurality of output circuits, and outputs a negative signal to the input terminal at a timing four horizontal synchronization periods after the input. , And can be.

  In the driving circuit of the present invention, the potential of the input active signal is held, and applied to the gate of a transistor serving as a switch for outputting the negative signal at the timing of outputting the negative signal. can do.

  A display device of the present invention is a display device having a plurality of pixels on a screen, and is arranged in any one of the drive circuits described above and each of the plurality of pixels, and a voltage based on a gradation value A display device, wherein the output of one of the drive circuits is connected to the gate line of the pixel transistor for one line of the screen. It is.

It is a figure showing roughly about a liquid crystal display concerning one embodiment of the present invention. It is a figure shown about the structure of the liquid crystal display panel of FIG. FIG. 3 is a diagram schematically showing a vertical drive circuit and scanning signal lines. It is a figure shown about the circuit structure of a signal output circuit. 5 is a timing chart of the operation of the signal output circuit of FIG. 6 is a timing chart of the operation of the Low fixed circuit unit in FIG. 4. It is a figure shown about the circuit structure of a Low signal output circuit. 7 is a timing chart of the operation of the Low signal output circuit of FIG. 6. FIG. 3 is a diagram schematically showing a vertical drive circuit and scanning signal lines. It is a figure shown about the circuit structure of a signal output circuit. 10 is a timing chart of the operation of the signal output circuit of FIG. 9.

  Hereinafter, first and second embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or equivalent elements are denoted by the same reference numerals, and redundant description is omitted.

[First Embodiment]
FIG. 1 schematically shows a liquid crystal display device 100 according to an embodiment of the present invention. As shown in this figure, the liquid crystal display device 100 includes a liquid crystal display panel 200 fixed so as to be sandwiched between an upper frame 110 and a lower frame 120, a backlight device (not shown), and the like.

FIG. 2 shows the configuration of the liquid crystal display panel 200 of FIG. The liquid crystal display panel 200 includes two substrates, a TFT (Thin Film Transistor) substrate 230 and a color filter substrate 220, and a liquid crystal composition is sealed between these substrates. On the TFT substrate 230, scanning signal lines G _{1 to} G _n controlled by the vertical driving circuit 240 and data signal lines D _{1 to} D _m controlled by a driving IC (Integrated Circuit) 250 are stretched. The signal line forms a pixel of the liquid crystal display device 100. Note that the liquid crystal display panel 200 has a number of pixels corresponding to the resolution of the display, but is simplified in FIG. 2 in order to avoid a complicated drawing.

FIG. 3 is a diagram schematically showing the vertical drive circuit 240 and the scanning signal lines G _{1 to} G _n driven by the vertical drive circuit 240. The vertical drive circuit 240 is provided at two locations across the display area 260, and has a signal output circuit 241 and a low signal output circuit 242, respectively. The signal output circuit 241 on one side of the display area 260 is connected to the low signal output circuit 242 on the other side via the scanning signal line G _i (i = 1 to n).

  FIG. 4 is a diagram showing a circuit configuration of the signal output circuit 241, and FIG. 5 is a timing chart of the operation of the signal output circuit 241 in FIG. As shown in FIG. 4, the signal output circuit 241 is divided into a main drive circuit unit 241A and a low fixed circuit unit 241B.

The operation of the main drive circuit unit 241A will be described. Here, _{V i} is the clock signal, VST denotes a start signal, the potential of VGPL is fixed to Low, VGPH is fixed to High. All of these signals are input from the outside. Further, time t in FIG. 5 is written every 4H (four horizontal synchronization periods).

Main drive circuit section 241A, first, at the timing of time t2 in FIG. 5, when the output is pre-4 horizontal drive period of the output _{G i} output _{G i-4} is High, the output _{G i-4} are transistors T7A Since the transistor T7A is turned on, the node N2 is connected to VGPL and becomes Low. Further, since this output Gi _-4 is also input to the diode-connected transistor T1, the node N1 connected thereto becomes High, causing a potential difference in the capacitor C1 and making the transistor T5 conductive. Since the node N1 is also a gate signal of the transistor T4, the node N2 is also connected to VGPL by the transistor T4 and becomes Low.

Next, at time t3, the clock signal V _i is High, the potential of one electrode of the capacitor C1 since the transistor T5 is conducting the next High, the transistor T5, which is the other electrode side by a so-called bootstrap The gate potential is pushed up more. Accordingly, High Output _{G i} is determined. The write period W of 3H (3 horizontal synchronization period) has elapsed from time t3, the data on the signal line D ₁ to D _m is the data signal voltage based on the gradation value of each pixel is applied, the output G of the time t4 to be described later Due to the fall of _i , a voltage based on the applied gradation value is held in the pixel. Therefore, the gate voltage can be sufficiently increased during a charging period of 3H (3 horizontal synchronization periods).

When the clock signal V _i becomes low at time t4, the output G _i also becomes low. To determine this, the output G _{i + 4} that has become high at the same time t4 is input to the gates of the transistor TG and the transistor T9. Te, made conductive transistor TG and the transistor T9, and connect the output _{G i} and node N1 VGPL respectively, are both the Low output _{G i} and node N1.

On the other hand, a clock signal V _{i + 4} that goes High at the same time t4 is input to the gate of the transistor T3, and the transistor T3 is turned on, whereby the node N2 is connected to VGPH and the node N2 is High. The high level of the node N2 is input to the low fixed circuit unit 241B described later.

As will be described later, AC signals VGL_AC1, VGL_AC1B, VGL_AC2, and VGL_AC2B that are inverted at 2V (two vertical synchronization periods) are input to the Low fixed circuit unit 241B. In the timing chart of FIG. 5, VGL_AC1 is High. And a partial period in 2V (2 vertical synchronization periods) in which VGL_AC2 is Low is shown. In FIG. 5, the transistors TA1 and TA4 that receive a high gate signal are turned on, and the transistors TA3 and TA2 that receive a low gate signal are turned off. Here, the signal of the node N2 that is High at the time t4 passes through the transistor TA1 that is turned on, and is input to the gates of the transistors T2 and T6, thereby turning on these transistors. The transistor T2 and the transistor T6 includes a VGL_AC2 a Low signal, connects the node N1 and the output _{G i,} respectively.

FIG. 6 shows a timing chart of the operation of the Low fixed circuit unit 241B. As shown in FIG. 6, AC signals VGL_AC1, VGL_AC1B, VGL_AC2 and VGL_AC2B that are inverted at 2 V (2 vertical synchronization periods) are input to the Low fixed circuit unit 241B, and VGL_AC2 is an inverted signal of VGL_AC1, and VGL_AC2B Is an inverted signal of VGL_AC1B. The timing of the switching is so shifted a little at a time as shown in FIG. 6, it continues to be connected to the node N1 and the output _{G i} to Low fixed signal (VGL_AC1 etc.). In this way, by shifting the transistors that are kept conductive between the transistors T2 and T2A or by switching between the transistors T6 and T6A, the threshold voltage shift of the transistors can be reduced.

7 is a diagram showing a circuit configuration of the Low signal output circuit 242, and FIG. 8 is a diagram showing a timing chart of the operation of the Low signal output circuit 242 in FIG. In Low signal output circuit 242 on the side opposite to the signal output circuit 241 via the display region 260, when the output _{G i} by a signal output circuit 241 is set to High, the output _{G i} is input to the transistor TC1 diode-connected The node NC1 is set to High and a potential difference is generated in the capacitor C4. Subsequently, at the timing when the clock V _{i + 4} becomes High, the transistor TC3 in which the clock V _{i + 4} is input to the gate signal is turned on, and the node NC2 becomes High. When the node NC2 is High, the transistor TC2 is conductive, is connected to VGL which is the output _{G i} and Low signals, Low is output to the output _{G i.} After that, when the clock V _{i + 8} becomes High, the transistor TC4 and the transistor TC5 to which the clock V _{i + 8} is input are turned on, the node NC1 and the node NC2 are connected to VGL which is the Low signal, and the transistor TC2 is turned off. Become.

  As described above, according to the present embodiment, the period during which the node N1 conducts the transistor T5 is set to 4H (four horizontal synchronization periods), and therefore the gate of each pixel transistor is set at the gray voltage write timing. The potential is set to a sufficiently high potential, and the gate voltage of each pixel transistor can be controlled more stably. Thereby, an appropriate gradation voltage can be applied to each pixel, and display quality can be improved.

Further, according to the present embodiment, three types of clocks V _i−4 , V _i and V _{i + 4} are used in one side circuit of the display area, and the clock V _{i− 2} , Since three types of clocks V _{i + 2} and V _{i + 6} are used, a total of six types of clock wirings can be reduced.

  Further, according to this embodiment, since the circuit for setting the gate potential of each pixel transistor to Low from both sides of the display region is provided, the signal potential is reduced and the gate potential of each pixel transistor can be lowered without delay. it can. Thereby, the input source-drain potential can be determined at an appropriate timing, and the display quality can be improved.

  Further, according to the Low signal output circuit of this embodiment, since the input High signal is used as the gate signal of the transistor that outputs the Low signal, power consumption can be suppressed.

[Second Embodiment]
A second embodiment which is an embodiment of the present invention will be described. The configuration of the liquid crystal display device and the liquid crystal display panel according to the second embodiment is the same as that of the liquid crystal display device 100 of FIG. 1 and FIG. 2 except that the vertical drive circuit 240 is a vertical drive circuit 340. Since it is the same as that of the liquid crystal display panel 200, overlapping description is omitted.

FIG. 9 is a diagram schematically showing the vertical drive circuit 340 and the scanning signal lines G _{1 to} G _n driven by the vertical drive circuit 340. Similar to the vertical drive circuit 240 of the first embodiment, the vertical drive circuit 340 is provided at two locations across the display area 260, and the signal output circuit 341 and the Low signal output circuit, which are the same circuits as those of the first embodiment, respectively. 242. The signal output circuit 341 on one side of the display area 260 is connected to the Low signal output circuit 242 on the other side via the scanning signal line G _i (i = 1 to n).

FIG. 10 is a diagram showing a circuit configuration of the signal output circuit 341, and FIG. 11 is a timing chart of the operation of the signal output circuit 341 in FIG. First, the operation of the signal output circuit 341 will be described. Here, as in the first embodiment, _{V i} is the clock signal, VST denotes a start signal, the potential of VGPL is fixed to Low, VGPH is fixed to High. All of these signals are input from the outside. Also, time t in FIG. 11 is written every 4H (4 horizontal synchronization periods).

Signal output circuit 341, first, at the timing of time t2 in FIG. 11, the output is pre-4 horizontal drive period of the output _{G i} output _{G i-4} is the High, the output _{G i-4} are transistors T7A Since the signal is input to the gate, the node N2 is connected to VGPL and becomes Low when the transistor T7A is turned on. Further, since this output Gi _-4 is also input to the diode-connected transistor T1, the node N1 connected thereto becomes High, causing a potential difference in the capacitor C1 and making the transistor T5 conductive. Since the node N1 is also a gate signal of the transistor T4, the node N2 is also connected to VGPL by the transistor T4 and set to Low.

Next, at time t3, the clock signal V _i is High, the potential of one electrode of the capacitor C1 since the transistor T5 is conducting the next High, the transistor T5, which is the other electrode side by a so-called bootstrap The gate potential is pushed up more. Accordingly, High Output _{G i} is determined. This 3H (3 horizontal synchronization period) of time t3 write period W after elapse, the data signal voltage based on the gradation value of each pixel to the data signal lines D ₁ to D _m is applied, G _i at time t4, which will be described later The voltage based on the applied gradation value is held in the pixel by the falling edge. Therefore, the gate voltage can be sufficiently increased during a charging period of 3H (3 horizontal synchronization periods).

When the clock signal V _i becomes low at time t4, the output G _i also becomes low. To determine this, the output G _{i + 4} that has become high at the same time t4 is input to the gates of the transistor TG and the transistor T9. Te, made conductive transistor TG and the transistor T9, and connect the output _{G i} and node N1 VGPL respectively, are both the Low output _{G i} and node N1.

On the other hand, a clock signal V _{i + 4} that goes High at the same time t4 is input to the gate of the transistor T3, and the transistor T3 is turned on, whereby the node N2 is connected to VGPH and the node N2 is High. Node N2 is inputted to the gate of the transistor T6, by conducting the transistor T6, to connect the output is _{G i} and the Low signal VGPL.

  The Low signal output circuit 242 is the same as the Low signal output circuit 242 of the first embodiment shown in FIG.

  As described above, according to the present embodiment, similarly to the first embodiment, the period during which the node N1 conducts the transistor T5 is set to 4H (four horizontal synchronization periods), so that the gradation voltage is written. At the timing, the gate potential of each pixel transistor is set to a sufficiently high potential, and the gate voltage of each pixel transistor can be controlled more stably. Thereby, an appropriate gradation voltage can be applied to each pixel, and display quality can be improved.

Further, according to the present embodiment, as in the first embodiment, one side circuit of the display area uses three types of clocks of clocks V _i−4 , V _i and V _{i + 4} , and the other one side circuit. Thus, since three types of clocks, ie, clocks V _i−2 , V _{i + 2} and V _{i + 6} , are used, a total of six types of clock wirings can be reduced.

  Further, according to the present embodiment, as in the first embodiment, since the circuit for setting the gate potential of each pixel transistor to Low from both sides of the display region is provided, each pixel has less signal rounding and no delay. The gate potential of the transistor can be lowered. Thereby, the input source-drain potential can be determined at an appropriate timing, and the display quality can be improved.

  In each of the above-described embodiments, an NMOS transistor in which the source and the drain are made conductive by inputting the High signal as an active signal to the gate is used. However, the Low signal is input to the gate as an active signal. Thus, a PMOS transistor in which the source and the drain are electrically connected may be used.

  In addition, the liquid crystal display device of each of the above-described embodiments may be applied to any liquid crystal display device of an IPS (In-Plane Switching) method, a VA (Vertically Aligned) method, or a TN (Twisted Nematic) method. Can do. Further, not only a liquid crystal display device but also an organic EL display device, a field emission display device (FED), and other display devices using a shift register as a driver circuit can be used.

  100 liquid crystal display device, 110 upper frame, 120 lower frame, 200 liquid crystal display panel, 220 color filter substrate, 230 TFT substrate, 240 vertical drive circuit, 241 signal output circuit, 241A main drive circuit unit, 241B Low fixed circuit unit, 242 Low signal output circuit, 250 drive IC, 260 display area, 340 vertical drive circuit, 341 signal output circuit.

Claims (6)

A drive circuit for a display device that sequentially outputs an active signal for conducting a transistor to a plurality of signal lines,
A plurality of output circuits respectively connected to the plurality of signal lines;
The plurality of output circuits each continue to output the active signal during four horizontal synchronization periods of the display device. The plurality of output circuits are:
One output circuit which is one of the plurality of output circuits;
A preceding output circuit that outputs at a timing 4 horizontal synchronization periods before the output timing of the output circuit,
2. The drive circuit according to claim 1, wherein an output of the preceding output circuit is input to the output circuit as a timing signal for outputting the active signal. The plurality of output circuits are:
One output circuit which is one of the plurality of output circuits;
A subsequent output circuit that outputs at a timing four horizontal synchronization periods after the output timing of the output circuit,
The drive circuit according to claim 1, wherein an output of the subsequent output circuit is input to the output circuit as a timing signal for outputting a negative signal from the output of the output circuit. A plurality of negative signal output circuits arranged opposite to each other across the display area of the display device with respect to the plurality of output circuits, respectively connected to the plurality of signal lines;
The plurality of negative signal circuits each receive the output of the active signal from the corresponding plurality of output circuits, and output a negative signal to the input terminal at a timing after four horizontal synchronization periods from the input. The drive circuit according to claim 1.   The potential of the input active signal is held and applied to a gate of a transistor serving as a switch for outputting the negative signal at a timing of outputting the negative signal. Drive circuit. A display device having a plurality of pixels on a screen,
The drive circuit according to any one of claims 1 to 4,
A pixel transistor disposed in each of the plurality of pixels and guiding a voltage based on a gradation value to each of the plurality of pixels;
One output of the driving circuit is connected to the gate line of the pixel transistor for one line of the screen.

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