JP2001160287A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an integrated circuit which is operated with low power consumption and in which memory cells are arranged in high density. SOLUTION: Each stage B1-B4 in which word drivers are arranged dividing to plural stages is made a unit block controlling a sub-threshold current of a word driver. Each unit block is provided with a current control means respectively, when one block is controlled so as to restrict a sub-threshold current, the other block is controlled so as to permit that a sub-threshold current flows.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit composed of fine MOS transistors, and more particularly to a circuit suitable for high-speed and low-power operation.

[0002]

[Background Art] 1989 International Symposium on VSI Technology, Systems and Applications, Proceedings of Technical Papers (1989
(May) Pages 188 to 192 (1989 International
Symposium on VLSI Technology, Systems and Applicat
ions, Proceedings of Technical Papers, pp.188-192
(May 1989)), as the MOS transistor is miniaturized, its breakdown voltage decreases, so that its operating voltage must be lowered. In this case,
In order to maintain the high-speed operation, it is necessary to lower the threshold voltage (V _T ) of the MOS transistor in accordance with the lowering of the operating voltage. This operating speed, the effective gate voltage of the MOS transistor, that is, ruled by a value obtained by subtracting the V _T from the operating voltage is because fast as this value is larger. For example, a 16 gigabit D is expected to have an effective channel length of 0.15 μm or less, a standard operating voltage inside the chip of 1 V, and a boosted word line voltage of about 1.75 V.
In RAM, V _T of the transistors (channel width [mu] m, defined by the drain current 10 nA, standard conditions of junction temperature 25 ° C., showing V _T of the PMOS transistor for simplicity inverts the sign) is also -0.04V . However, the operating voltage is below about 2V, when not forced to the V _T below about 0.4V, as described below, MOS
Due to the sub-threshold characteristic (tailing characteristic) of the transistor, the transistor can no longer be completely turned off, and a phenomenon occurs in which a direct current flows.

A conventional CMOS inverter shown in FIG. 6 will be described. Ideally, when the input signal IN is at a low level (= V _SS ), the N-channel MOS transistor _MN is off, and when the input signal IN is at a high level (= V _CC ), the P-channel MOS transistor _MN is turned off.
When the S transistor M _P is turned off and the output voltage is determined in any case, no current flows. However, when the V _T of the MOS transistor is lowered, it becomes impossible to ignore the subthreshold characteristic.

As shown in FIG. 7, a drain current I _DS in a subthreshold region is proportional to an exponential function of a gate-source voltage V _GS and is expressed by the following equation.

[0005]

(Equation 1)

[0006] However, W is the channel width of the MOS transistor, I _0, W ₀ is the current value and the channel width in defining the V _T, S is tailing factor (inverse of the slope of V _GS -log I _DS characteristics) is there. Therefore, even if V _GS = 0, the subthreshold current

[0007]

(Equation 2)

Flows. Since the transistor in the off state in the CMOS inverter of FIG. 6 has V _GS = 0, the above-mentioned current _IL flows from the high power supply voltage V _CC to the low power supply voltage V _SS which is the ground potential during non-operation. Become. The subthreshold current, as shown in FIG. 7, 'Lowering the, I _L from I _L' V _T the threshold voltage from V _T exponentially increases in the. As is apparent from the above equation, in order to reduce the subthreshold current, V _T
May be increased or S may be decreased. However, the former causes a reduction in speed due to a reduction in the effective gate voltage. In particular,
If the operating voltage is lowered along with the miniaturization from the viewpoint of the withstand voltage, the speed drop becomes remarkable, and the advantage of the miniaturization cannot be utilized, which is not preferable. The latter is difficult for the following reasons, as long as it is operated at room temperature. Tailing factor S is the capacitance C _D of the depletion layer capacitance C _OX and under the gate of the gate insulating film is represented as follows.

[0009]

(Equation 3)

Here, k is Boltzmann's constant, T is absolute temperature, and q is elementary charge. As is clear from the above equation, C _OX
And C _D are Notwithstanding the how S ≧ kT ln 10 / q of, it is difficult to below 60mV at room temperature.

[0011]

Due to the phenomena described above, the substantial DC current of a semiconductor integrated circuit composed of a large number of MOS transistors significantly increases. In particular, at the time of high-temperature operation, since _VT is low and S is large, this problem becomes more serious. In the era of downsizing such as computers where low voltage operation and low power are important, or in the era of battery operation which is essential for portable devices, this increase in subthreshold current is an essential problem. .

This problem will be further described with reference to a memory which is a typical semiconductor integrated circuit. Memory LSI, for example, a dynamic random access memory (DRA)
M), as shown in FIG. 8, a row line (word line W) is used to select an arbitrary memory cell MC in the memory array MA.
X) for selecting and driving L), a word driver (WD), a sense amplifier (SA) for amplifying a signal of a column line (data line D), and a sense amplifier driving circuit (SAD) for driving the sense amplifier. ) And a Y decoder (YDEC) for selecting a column line. Further, a peripheral circuit (PR) for controlling these circuits is built in. The main part of these circuits has a circuit configuration based on the above-described CMOS logic circuit in order to reduce power consumption during operation, standby, battery backup, and the like. However, the threshold voltage V of the transistor
_T (Hereinafter, for simplicity, PMOS transistor and NMO
The absolute value of the S transistor is equal, it is assumed that V _T. )
Decreases, the through current increases drastically for the above-mentioned reason. This is particularly noticeable in the decoder and driver or peripheral circuit section. This is because the number of circuits constituting these is overwhelmingly large and has special functions. For example, regarding a decoder or a driver, a small number of specific circuits are selected and driven from a large number of circuits of the same type by an address signal. If V _T is large enough, many non-selection circuits are completely cut, that is, this selection / driving is performed while the through current is substantially zero. In general, as the storage capacity of the memory increases, the number of decoders and drivers increases. However, as long as the through current does not flow through the non-selection circuit, the total current does not increase even if the storage capacity increases. However, this is only possible when _VT is large, and as described above, the through current will increase sharply. Similarly, when the entire chip is not selected (standby state), conventionally, most of the circuits in the chip were turned off to reduce the power supply current as much as possible, but this is no longer possible. This problem is not limited to the memory LSI, but is common to all semiconductor integrated circuits based on a CMOS logic circuit incorporating a memory.

Therefore, an object of the present invention is to provide an MO
It is an object of the present invention to provide a high-speed and low-power semiconductor integrated circuit device even if the S transistor is miniaturized, and to reduce a through current of a word driver, a decoder, and the like which is a problem particularly in a memory or a semiconductor integrated circuit device incorporating a memory. .

[0014]

In order to achieve the above-mentioned object, a plurality of circuits of the same kind are constituted, and only a small number of circuits selectively operate in a desired time zone, and the rest are in a non-selected state. In such a semiconductor integrated circuit, a large number of circuits are formed into at least one or more blocks, and a power supply line is provided corresponding to the block, and a desired operation voltage is selectively applied to the power supply line. The selection function is realized by an address signal, a signal designating an operation mode such as active and standby, a signal designating a specific time zone in the active time zone, or a combination thereof.

[0015] Even if the threshold voltage of the transistor is low,
Through current flowing to the non-selection circuit can be minimized.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an example in which the present invention is applied to a word driver (WD in FIG. 8) of a DRAM will be described. If desired word voltage V _CH word line is selected takes a state after being applied to the word line as an example, in the conventional structure shown in FIG. 9, if V _T is even located high enough, all the CMOS driver Does not flow through. But V
_{When T} becomes as low as about 0.4 V or less, a through current flows through the word driver, the capacity increases, the number of word drivers (r) increases, and this size cannot be ignored. The total I _A of this through current is

[0017]

(Equation 4)

## EQU1 ## Here, as shown in FIG. 2 V _T
Is a threshold voltage defined by the current value I ₀ , and S is a tailing coefficient. Since the word driver power supply V _CH usually provided by boosting the external power supply inside the chip, the current driving capability is limited, it can not be processed and I _A increases. As a method for solving this, (1) a method of applying a required voltage to a power supply line of a word driver for a desired period,
(2) A method in which a group of word drivers is divided into a number of blocks including a plurality of drivers, and a required voltage is applied only to a specific block to be selected, and (3) a method in which both are combined.

FIG. 10 shows an embodiment in which a required voltage is applied to a power supply line of a word driver only for a desired period and the time during which a subthreshold current flows is limited. It is characterized in that a required word voltage is supplied to the common power supply line of the block after the logic input of the driver is determined. According to the operation timing shown in FIG.
The operation will be described focusing on the voltage relationship of the S transistor. In the case of a well-known DRAM memory cell composed of an NMOS transistor and a capacitor (storage capacitor), the voltage of all non-selected word lines must be V _SS (0 V), and therefore includes a word driver to be selected. The gate voltage of the PMOS transistor in all word drivers is V _CH . Next, when the selection operation starts, only the gate N _X1 of the PMOS transistor of the selection driver (# 1) becomes 0V. At this time, V _CH remains at the other word drivers (# 2 to #r), and the gate voltages of the PMOS transistors of all the word drivers are determined. Now, before the gate voltage of the PMOS transistor is determined, the voltage of the common power supply line P _B to which the source of the PMOS transistor is connected is set higher than V _CH so that the sub-threshold current of the PMOS transistor can be ignored. Low below a certain voltage, 0V in extreme cases
Set to. Here, the certain voltage, with respect to V _T of the PMOS transistor, V _CH - is about (0.4V-V _T). Because, to make the subthreshold current of the PMOS transistor small enough to be ignored,
Gate - effective gate voltage minus V _T from the voltage between the source, because we need about 0.4V as described above.
For example, the 16 gigabit DRAM, V _CH = 1.75V As described above, since the order of V _T = -0.04V, the voltage is referred to here is about 1.31V. Increasing the common feeder line P _B after the gate voltage decision to V _CH, the voltage of V _CH is applied from a PMOS transistor corresponding to the selected word line. After applying the desired time period, the gate voltage of the PMOS transistor in all of the word driver to V _CH, discharged to 0V is selected word line by the corresponding NMOS transistor. Thereafter, the voltage of the common power supply line P _B is reduced again to a certain voltage or lower. With such a driving method, there is a problem that the sub-threshold current still flows in the PMOS transistor of the non-selected word driver during the period when V _CH is applied to the common drive line. There is no external current flowing through the. Even if the logic input of the driver is determined after applying the required word voltage to the common feed line,
A normal voltage is obtained on the word line. In this case, during the period from when the word voltage is applied to the power supply line to when the logical input of the driver is determined, a subthreshold current flows in all word drivers uselessly. On the other hand, in the method in which the word voltage is applied to the common power supply line after the logic input is determined, useless current during this period can be reduced. However, the operation is slightly slower. This is because the large parasitic capacitance of the common power supply line requires a long rise time in this portion, and the access time is correspondingly delayed.

FIGS. 12 and 13 show a conceptual embodiment for solving the above-mentioned problem. The word driver group is divided into a large number of blocks composed of a plurality of drivers, and the subthreshold current is limited to only selected blocks. There is a feature in doing. That is, the current can be reduced in inverse proportion to the number of divisions. FIG. 12 shows a one-dimensional arrangement of m blocks of n word drivers (where mn =
In r), the subthreshold current can be reduced by 1 / m as compared with the embodiment shown in FIG. FIG. 13 shows a block composed of 1 (lowercase letter) word drivers k
(Not Boltzmann's constant in the following)
In addition, j pieces are two-dimensionally (matrix) arranged in the column direction (however, j · k · l = r). In this configuration,
The subthreshold current can be reduced by 1 / (j · k) as compared with the embodiment shown in FIG. Since the one-dimensional arrangement in FIG. 12 is obvious from the description of the two-dimensional arrangement in FIG. 13, the two-dimensional arrangement will be described in detail below with reference to some embodiments.

FIG. 14 shows an embodiment of a typical selection method of a two-dimensional arrangement, and FIG. 15 is an operation timing chart thereof. A required word voltage _VCH is applied to a row line (P _S1 ) corresponding to a block to be selected, for example, B _1,1 , and a corresponding column line (Φ _B1 ) is applied.
Is applied with 0V. The block selection PMOS transistor Q _1,1 is turned on, and the power supply line (P _1,1 ) belonging to B _1,1
Is charged to V _CH . Since the gate voltage of the PMOS transistor constituting the word driver belonging to B _1,1 has already been determined, V _CH is applied to the word line selected accordingly.
Is applied. Of course, as described above, P _1,1 is V _CH
, The word line can be normally driven even if the gate voltage is determined. After applying for a desired period, P ₁₁
Is discharged to 0 V by an NMOS transistor connected to it. The feed line belonging to the unselected block remains at 0V. Here, for simplicity, block select PMOS
Transistor as well as sufficiently high the V _T of the power supply line discharge for the NMOS transistor consider the case where (0.4V or so) chosen. Since the power supply line of the unselected block is always 0 V, no subthreshold current flows through the word driver in the unselected block. Therefore, the entire through current can be significantly reduced to almost only the through current of one word driver in the selected block. In addition, since the power supply line is divided and the divided power supply line having a small parasitic capacitance may be driven, FIG.
0 can be operated at a higher speed than the embodiment shown in FIG.

FIG. 1 shows another embodiment of the two-dimensional arrangement selection method. As in the embodiment shown in FIG. 14, only the block at the intersection between the power supply line (for example, P _S1 ) and the column control line (for example, Φ _B1 ) is selected. The differences from the embodiment shown in FIG. 4 are as follows. In FIG. 4, the voltage of the power supply line of each block in a non-selected state is 0 V, and the power supply lines of the non-selected blocks are all 0 V even after the block selecting operation is started. When any one block is selected, the voltage of the power supply line must be charged from 0 V to V _CH, so that there is a disadvantage that the current is low and the transient current is large. In order to solve this, when a certain block is changed from the non-selected state to the selected state, the voltage change of the power supply line is as small as possible, and the sub-threshold current of the other non-selected blocks is suppressed to be negligible. It is desirable. The embodiment shown in FIG. 1 realizes this, and has the following two features. (1) Hierarchical power supply line in which drivers are divided into blocks: j · k blocks each consisting of l word drivers are provided and arranged in a matrix. These are divided into k sectors, and j sectors are set. Power supply line P _{B1 of} each block
P _Bk is connected to the feeder line of the sector (for example, P _S1 ) via the block selection transistors Q _{B1 to} Q _Bk . Also,
The power supply lines P _{S1 to} P _Sj of each sector are connected to the power supply line P via the sector selection transistors QS _{1 to} QS _j . further,
P is a transistor Q for selecting an operation mode and a standby mode.
Through the power supply line of the word voltage _VCH . (2) Hierarchical gate width setting: The gate width (d · W) of the block selection transistor is selected to be sufficiently smaller than the total (l · W) of the gate widths of the word driver transistors in the block (d≪). l). In addition, the gate width (eW) of the sector selection transistor is selected to be sufficiently smaller than the sum (kdW) of the gate widths of the block selection transistors in the sector (e≪kd). Further, the gate width (f · W) of Q is selected to be sufficiently smaller than the sum (j · e · W) of the gate widths of all the sector select transistors (f≪j · e).

In operation, Q, Q _S1 and Q _B1 are turned on, and V is applied to the power supply lines P _B1 and P _S1 corresponding to the sector S ₁ including the blocks B ₁ and B ₁ including the selected word driver (# 1). Supply _CH . Where V _{T of} all transistors
Assume the same low value. With this configuration, the entire through current of each of the non-selected sectors (S _{2 to} S _j ) becomes equal to the sub-threshold current of one corresponding sector selection transistor (Q _{S2 to} Q _Sj ). In addition, the selected sector (S
The through current of each of the unselected blocks (B _{2 to} B _k ) in ₁ ) is determined by the corresponding block selection transistors (Q _{B2 to} Q _Bk ).
It is equal to one subthreshold current. Because the sub-threshold current is proportional to the gate width of the transistor, for example, even if a current of l · i tries to flow in a non-selected block in S ₁ , the entire through current eventually becomes the sub-threshold of the block selection transistor. This is because the current is limited to the current (d · i). Therefore,
All through current I _A is substantially as shown in Table 1 (l + k · d
+ J · e) i. In order to reduce I _A , it is preferable to set l and (k · d) and (j · e) to the same value. Here, if d, e, and f are set to about 4, the influence on the speed and the chip area of the series transistors (Q, Q _S1 , Q _B1 ) can be reduced.

For example, during standby, Q, Q _{1 to} Q _k are all turned off. The total through current I _S becomes equal to the sub-threshold current of Q, and f /
j · k · l. The voltage of the power supply line of the block is lowered from V _CH by ΔV which is determined by the ratio and tailing coefficient j · k · l · W and f · W, as shown in FIG.

Table 1 shows 16 gigabit D as a numerical example.
The current value obtained assuming the RAM is also shown. The parameter used therefor is that the threshold voltage V _T defined by the voltage at which a current of 10 nA flows with a gate width of 5 μm is −0.12.
V, tailing coefficient S is 97 mV / dec. The junction temperature T is 75 ° C., the effective gate length L _eff is 0.15 μm, the gate oxide film thickness T _OX is 4 nm, and the word voltage V _CH is 1.75.
V and the power supply voltage V _CC are 1V. According to the present invention, the subthreshold current is reduced from about 700 mA in the related art to about 2 mA, about 1/350 in operation, and about 3300 in standby.
It can be reduced to about 20 μA, which is 1/0.

[0026]

[Table 1]

FIG. 3 is a schematic diagram of an operation waveform. During standby (Φ, Φ _{S1 to} Φ _Sj , Φ _{B1 to} Φ _Bk : V _CH ), Q and Q _S1
Since to Q _Sj and Q _B1 to Q _Bk is turned almost off, P is are lower voltage V _CH - [Delta] V "than V _CH, P _S1 ~P _Sj is lower voltage V _CH - [Delta] V ' , P _B1 ~
P _Bk is at a lower voltage V _CH -ΔV. All word lines are fixed at V _SS irrespective of the voltages of P _{B1 to} P _Bk . When the external clock signal / RAS (where “/” indicates a bar signal) is turned on, first, Φ
To turn on Q, charge the parasitic capacitance C of P for t _1
CH . Next, Q _S1 is turned on at Φ _S1 , and the parasitic capacitance C _S1 of P _S1 is charged to V _CH for t ₂ hours. Also, Q in Φ _B1
B1 is turned on, and the parasitic capacitance C _B1 of P _B1 is charged for t ₃ hours to V _CH . At this time, Q _{S2 to} Q _Sj and Q _{B2 to} Q _Bk remain almost off. Thereafter, the word driver # 1 is selected by the X decoder output signals X _1, the word line is driven. When / RAS is off, Q and Q _S1 and Q
_B1 turns off. P, P _S1 , and P _B1 become V _CH −ΔV ″, V _CH −ΔV ′, and V _CH −ΔV, respectively, after a long time. Here, the power supply lines (P, P ₁ ) can be charged to V _CH because, even if C is large, ΔV "is as small as several hundred mV and / RAS
This is because a sufficient charge time (t ₁ ) of P can be taken immediately after the switch is turned on. In addition, since it is divided into sectors and blocks, C _S1 and C _B1 are relatively small, so that the charging time (t ₂ , t ₃ ) of P _S1 and P _B1 can be shortened.

[0028] In the above description, although not touch the connection of the substrate of the transistor (substrate), to connect the substrate of the PMOS transistor to all V _CH is preferable. In this case, the charge required for charging the power supply line is smaller and the charging time is shorter than when the substrate is also connected to the power supply line connecting the drain. This is because the threshold voltage of the PMOS transistor in the non-selected block increases due to the substrate bias effect when the power supply line of the non-selected block drops by ΔV from V _CH as described above. Since the source has a lower voltage than the gate and a higher threshold voltage, the same current reduction effect can be obtained with a smaller ΔV than when the substrate has the same voltage as the drain.

Since the word voltage V _CH is boosted from the power supply voltage V _CC, a voltage having a larger amplitude than the other circuits is input to the gate of the MOS transistor of the word driver. Therefore, it is also possible to further lower current by increasing the amount corresponding V _T. However, there is a disadvantage that the operation speed is slightly reduced.

This disadvantage is alleviated by lowering the threshold voltage of the transistor in the word driver and increasing the threshold voltage of the transistor used as a switch. For example, Q and Q _{S1 to} Q _Sj and Q in FIG.
The threshold voltage of _B1 to Q _Bk higher than transistors in the word driver, d, e, by setting a large f, while preventing the operating speed of deterioration due to the on resistance of the switch, further reducing the through current it can. The off-state subthreshold current affects exponentially,
This is because the ON resistance is affected only by a linear function. Even if the gate capacitance increases with the gate width, if the charging times t ₁ , t ₂ , and t ₃ in FIG. 3 can be secured, there is no problem in terms of operating speed. Therefore, the through current can be further reduced without deteriorating the operation speed. In terms of layout area, there is no problem because the number is relatively small. In some cases, using a transistor having a high threshold voltage only for Q is effective in reducing the standby current.

In this embodiment, one PM is used as a switch.
Although an OS transistor is used, various elements or circuits can be considered as long as the following two conditions are satisfied. (1) When a switch is selected: Assuming that the switch is short-circuited, an operating current (a sub-threshold current and a selected threshold current flowing through a load of the switch (eg, one word driver in a block selection switch)) The current driving capability of the switch is greater than the charging current of the word line. (2) When the switch is not selected: The current supply capability of the switch is smaller than the standby current (subthreshold current) flowing through the load when the switch is assumed to be short-circuited. It suffices if the impedance can be varied between small and large at the time of selection and at the time of non-selection so as to satisfy these two conditions.

In the operation shown in FIG. 3, during the active period when / RAS is 0 V, Φ, Φ _S1 , Φ _B1 are kept low, and Q, Q _S1 , Q _B1 are kept on. Was. this is,
/ Controls [Phi by a signal for designating the operation mode of the standby at the time of activity that is generated by the RAS, [Phi _S1 by the combination signal of the signal and the address signal is achieved by controlling the [Phi _B1. Further, after the word line is driven, Φ, Φ _S1 , Φ _B1 are set to V _CH and Q, Q _S1 , Q _B1 are used after the word line driving by using a signal designating a period from the fall of / RAS to the end of the word line driving. It is also possible to turn off. Thereby a through current after the word line driving, even during active can be reduced to the same extent as standby current I _S. This effect is
The longer the active period in which AS is 0 V, the greater the value. However, in this case, / R
It is necessary to lower Φ, Φ _S1 , Φ _B1 and turn on Q, Q _S1 , Q _B1 for a certain period from the rise of AS.

FIG. 4 shows an example in which 512 word drivers are divided into four blocks. 512 per data line pair
Memory cells (MC _{1 to} MC ₅₁₂ ) are provided and 512
Selected by one word line. In order to arrange the memory cells with high density, the line width and interval of the word lines are almost equal to the minimum processing size. Therefore, the word drivers cannot be laid out at the same pitch as the word lines, and are generally laid out in about four stages. FIG. 4 shows that each stage on the layout is directly used as a word driver block (B _{1 to} B ₄ ), and the layout area does not increase by separating the power supply line of each block. Thus, the value of 1 can be made smaller than the number of memory cells per data pair line. On the contrary, it is obvious that the value can be increased, and the degree of freedom of the value of l is large. Therefore, the through current I _A during operation and l so becomes minimum (k ·
d) and (j · e) can be set.

The embodiment in which the present invention is applied to the word driver has been described above. However, as long as the spirit of the present invention is not deviated,
It is not limited to this. The following modifications are also possible.

FIG. 5 shows an example in which the hierarchical feed line system of FIG. 1 is applied to a decoder. C of NAND circuit and inverter
This is an example of an AND circuit composed of two stages of MOS logic circuits, and is characterized in that a hierarchical feed line is used on both sides of V _CC and V _SS . The NAND circuits all output V _CC during standby and a few output 0 V during operation. Through current is V
Since it defined by _SS of the NMOS transistor, using hierarchical feed line to the V _SS side. Conversely, the inverters all output 0 V during standby and a few output V _CC during operation. Since the through current is determined by the PMOS transistor, V
_A hierarchical feeder is used on the _CC side. Thus, V _CC and V _SS
By using the hierarchical power supply lines on both sides of the circuit, the through current can be reduced without making the operation unstable even in a multi-stage logic circuit. Note that any of the methods shown in FIGS. 10 to 15 can be similarly applied to a multi-stage circuit such as a decoder.

In a circuit such as a sense amplifier driving circuit that operates around V _CC / 2, the through current can be reduced by applying the present invention to both sides of V _CC and V _SS . The present invention can be applied to any circuit group that outputs the same voltage during standby and operates a small number during operation. At that time, not all circuits need to have the same transistor size, and the configurations may be different. Further, the number of circuits in a block or the number of blocks in a sector may be different.

When a plurality of circuits operate simultaneously, a plurality of circuits may be operated in one block or a plurality of blocks may be simultaneously selected. Further, the transistor operating as a switch may be divided into a plurality of transistors. In that case, the effect of wiring resistance can be reduced by shortening the power supply line,
The power supply line of the selected block can be charged in a short time.

The present invention can be applied not only to a DRAM but also to a memory such as a static random access memory (SRAM), a read-only memory (ROM) or a flash memory, and a memory built-in logic LSI. Further, the present invention can be applied to a logic circuit other than the CMOS such as an NMOS logic circuit. According to the present invention, the lower the threshold voltage is, the larger the effect is.
In I, the effect is remarkable. In particular, when the operating voltage is about 2 V or less, a threshold voltage of about 0.2 V is required from the viewpoint of the operating speed, or when the gate length is about 0.2 μm or less, the threshold voltage becomes about 0.2 V due to the scaling law.
Such an LSI is very effective, and it is possible to operate a battery for the first time.

[0039]

As is clear from the embodiments described above,
According to the present invention, a through current can be reduced without impairing the operation speed, and a semiconductor device which operates at high speed with low power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment applied to a word driver.

FIG. 2 is a diagram showing operating points of PMOS transistors of a word driver.

FIG. 3 is an operation timing chart of the embodiment shown in FIG. 1;

FIG. 4 is a diagram showing an example in which 512 word drivers are divided into four blocks.

FIG. 5 is an embodiment applied to a decoder.

FIG. 6 is a circuit diagram of a conventional CMOS inverter.

FIG. 7 is a diagram showing sub-threshold characteristics of a transistor.

FIG. 8 is a block diagram of a memory.

FIG. 9 is a diagram showing a conventional power supply line of a word driver.

FIG. 10 is a diagram showing an embodiment in which the time during which a subthreshold current flows is limited.

11 is a control timing chart of the embodiment shown in FIG.

FIG. 12 is a diagram showing an embodiment in which blocks are arranged one-dimensionally.

FIG. 13 is a diagram showing an embodiment in which blocks are two-dimensionally arranged.

FIG. 14 is an example of a typical selection scheme of a two-dimensional arrangement.

FIG. 15 is a control timing chart of the embodiment shown in FIG.

[Explanation of symbols]

WD: Word driver, WL: Word line, XDEC: X
Decoder, D: data line, SA: sense amplifier, YDE
C: Y decoder, SAD: Sense amplifier drive circuit, MC
... memory cells, MA ... memory arrays, PR ... peripheral circuits,
V _CH ... word voltage, V _CC ... supply voltage, V _SS ... ground voltage _{(0V), S 1 ~S j} ... sector, B ₁ ~B _k ... block, j
... number of sectors, k ... number of blocks per sector, l ...
Number of circuits per block, P: power supply line, Q: transistors for selecting operation mode and standby mode, P _{S1 to} P _Sk
... sector of feeders, Q _S1 to Q _Sj ... sector selection transistor, the power supply line of the P _B1 to P _Bk ... block, Q _B1 to Q _Bk ... block selection transistor.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 16/06 G11C 11/34 354D 354F 17/00 633Z

Claims (3)

[Claims] A semiconductor integrated circuit comprising: a plurality of word lines; a data line intersecting the plurality of word lines; and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of data lines. A semiconductor integrated circuit in which a word driver group for selecting a plurality of word lines is composed of a plurality of stages, and a word driver of each stage is a unit for controlling a subthreshold current of a MOS transistor constituting the word driver. 2. A semiconductor integrated circuit comprising: a plurality of word lines; a data line intersecting the plurality of word lines; and a plurality of memory cells disposed at intersections of the plurality of word lines and the plurality of data lines. A first node and a second node for supplying an operating voltage,
A plurality of word drivers for selecting any of the plurality of word lines, wherein the plurality of word drivers are constituted by a plurality of blocks, and are connected between the first node and each of the plurality of blocks. One block and another block included in the plurality of blocks are configured to limit a subthreshold current of the MOS transistor of the word driver by the current control unit corresponding to the one block. The other block is controlled by the corresponding current limiting means to allow the sub-threshold current of the MOS transistor of the word driver to flow, and drives the first word line. And a second word line disposed adjacent to the first word line and the block to which the first word driver belongs. The semiconductor integrated circuit of different blocks from the blocks belong second word driver for driving a word line. 3. The semiconductor integrated circuit according to claim 2, wherein a block to which a word driver for driving said first word line belongs and a block to which a word driver for driving said second word line belongs are arranged adjacently. Integrated circuit.