JP2001159927A5 - - Google Patents

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Publication number
JP2001159927A5
JP2001159927A5 JP2000297985A JP2000297985A JP2001159927A5 JP 2001159927 A5 JP2001159927 A5 JP 2001159927A5 JP 2000297985 A JP2000297985 A JP 2000297985A JP 2000297985 A JP2000297985 A JP 2000297985A JP 2001159927 A5 JP2001159927 A5 JP 2001159927A5
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JP
Japan
Prior art keywords
coefficient
input
input bit
bit set
subset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000297985A
Other languages
English (en)
Japanese (ja)
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JP2001159927A (ja
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Publication date
Priority claimed from US09/410,409 external-priority patent/US6549924B1/en
Application filed filed Critical
Publication of JP2001159927A publication Critical patent/JP2001159927A/ja
Publication of JP2001159927A5 publication Critical patent/JP2001159927A5/ja
Pending legal-status Critical Current

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JP2000297985A 1999-10-01 2000-09-29 補間方法および補間装置 Pending JP2001159927A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US410409 1999-10-01
US09/410,409 US6549924B1 (en) 1999-10-01 1999-10-01 Function generating interpolation method and apparatus

Publications (2)

Publication Number Publication Date
JP2001159927A JP2001159927A (ja) 2001-06-12
JP2001159927A5 true JP2001159927A5 (https=) 2005-07-07

Family

ID=23624595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000297985A Pending JP2001159927A (ja) 1999-10-01 2000-09-29 補間方法および補間装置

Country Status (5)

Country Link
US (1) US6549924B1 (https=)
EP (1) EP1089227A3 (https=)
JP (1) JP2001159927A (https=)
KR (1) KR20010067226A (https=)
TW (1) TW484091B (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6963895B1 (en) * 2000-05-01 2005-11-08 Raza Microelectronics, Inc. Floating point pipeline method and circuit for fast inverse square root calculations
US7266576B2 (en) * 2002-12-24 2007-09-04 Lockheed Martin Corporation Circuits and methods for implementing approximations to logarithms
JP3845636B2 (ja) * 2004-01-21 2006-11-15 株式会社東芝 関数近似値の演算器
US8346831B1 (en) * 2006-07-25 2013-01-01 Vivante Corporation Systems and methods for computing mathematical functions
CN114326922A (zh) * 2021-11-23 2022-04-12 极芯通讯技术(南京)有限公司 一种数据处理方法及装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5184317A (en) * 1989-06-14 1993-02-02 Pickett Lester C Method and apparatus for generating mathematical functions
US5175701A (en) * 1989-07-25 1992-12-29 Eastman Kodak Company System for performing linear interpolation
US5177698A (en) * 1990-07-09 1993-01-05 Eastman Kodak Company Selectable power of two coefficient signal combining circuit
WO1994018632A1 (en) * 1993-02-01 1994-08-18 Lester Caryl Pickett Low latency function generating apparatus and method
US5604691A (en) * 1995-01-31 1997-02-18 Motorola, Inc. Logarithm/inverse-logarithm converter utilizing a truncated Taylor series and method of use thereof
US6349319B1 (en) * 1999-01-29 2002-02-19 Sun Microsystems, Inc. Floating point square root and reciprocal square root computation unit in a processor

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