JP2001156056A - Apparatus for preventing plasma damage to wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an apparatus for preventing plasma-induced damages to a wafer. SOLUTION: This apparatus is suited for use with a plasma deposition apparatus for forming dielectric layers. The invented apparatus comprises a screen grid 302 having a region slightly greater than the region size of the wafer 300 under processing, the screen grid 302 is disposed just above the wafer, and a negative bias is applied to the screen grid in the initial stage of a process of forming the dielectric layer, thereby filtering positive ions of the plasma in the deposition apparatus. In the initial stage of a plasma deposition process, an electron flat gun 304 neutralizes electric charges on the wafer to form a non-plasma-ion-damage liner layer on the wafer surface before surely depositing the dielectric layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus for preventing plasma damage on a wafer. More specifically, the present invention relates to a high-density plasma-enhanced chemical vapor deposition (HD)
The present invention relates to an apparatus for preventing plasma damage of a wafer in a process.

[0002]

2. Description of the Related Art A trend in semiconductor manufacturing is miniaturization of devices. Various manufacturing techniques have been developed to miniaturize devices. For example, HDPCV
D technology was developed with good gap filling properties and is now the most common technology for forming shallow trench isolation (STI) or intermetal dielectric layers (IMD).

The above-described HDPCVD technique generally uses two mechanisms, chemical vapor deposition and physical impact etching by cations, and the impact etching mechanism uses a wafer having a higher energy plasma. Impact, thereby damaging the wafer. Furthermore, an antenna effect is also induced.

FIG. 1 illustrates a conventional structure. FIG. 1 schematically shows a cross-sectional structure of a general semiconductor device having a multi-level interconnect. More specifically, a semiconductor device is formed on a substrate 100, and an interconnect line 10 is formed on the device.
8a and 108b are formed. These interconnect lines 108a and 108b are connected to the conductive region 100 via the interconnect lines 104 and the contact plugs 106.
a, 100b. Gate electrode 10
2 are disposed on the substrate 100 between the conductive regions 100a and 100b.

[0005] Interconnect lines 108a, 108b
Is formed, a dielectric layer is deposited by an HDPCVD process to form interconnect lines 108a, 1a.
08b must be filled. This H
In the DPCVD process, when the density of the plasma is not uniform, the interconnect lines 108a, 108
8b will receive different amounts of positive charge.
As a result, a potential difference occurs between the interconnect lines 108a and 108b.

The interconnect lines 108a, 108
8b denotes an interconnect line 104 and a contact plug 10
6 are electrically coupled to the conductive regions 100a and 100b through the interconnect lines 108a and 10b.
The potential difference between 8b also reflects the potential difference between the conductive regions 100a and 100b. This potential difference affects the gate dielectric layer 102a, which causes plasma induced damage (plasma induced damage PID). This significantly reduces the properties of the gate dielectric layer 102.

[0007]

As described above, plasma damage in a wafer is a problem in the prior art, and it is an object of the present invention to prevent this plasma damage.

[0008]

SUMMARY OF THE INVENTION The present invention is directed to an apparatus for solving the above-mentioned problems, that is, being induced at an early stage in a plasma process by filtering or neutralizing plasma cations. An object of the present invention is to provide an apparatus for preventing occurrence of plasma-induced damage in a wafer, and to solve the above-mentioned problem. The invention at least
Plasma induced damage in the device when the dielectric layer is deposited in a plasma process can be effectively eliminated.

As described above, the present invention provides an apparatus for preventing the occurrence of plasma-induced damage in a wafer. This device is suitable for use in a plasma deposition device for depositing a dielectric layer.
The apparatus includes a screen grid having an area slightly larger than the area size of the wafer to be processed. This screen grid is set immediately above the wafer. At an early stage of the plasma deposition process, the screen grid is negatively biased,
This is to filter positive ions of plasma in the deposition apparatus. The apparatus further includes, for example, an electronic flood gun located directly above the wafer. During an early stage of the plasma deposition process, an electron flood gun neutralizes the charge on the wafer, forming a liner free of plasma ion damage to the wafer before the dielectric layer is reliably deposited.

The plasma deposition process is, for example, a process for forming a dielectric layer between interconnect lines or forming an STI structure. The plasma deposition apparatus includes, for example, an HDPC
VD equipment, transformer coupled plasma (TCP) chemical vapor deposition (CVD) equipment or inductively coupled plasma (ICP)
A CVD device is included.

The present invention includes a screen grid or an electron flood gun having at least a negative bias, which is incorporated in a plasma deposition apparatus and is disposed or installed immediately above a wafer to be processed. . The screen grid completely filters the cations in the plasma, and the electron flood gun neutralizes the charge stored on the wafer. As a result, the wafer can be prevented from being bombarded by cations in the initial stage of depositing the dielectric layer. Thus, a liner without plasma ion damage can be formed, thus ensuring that the dielectric layer is deposited.

According to the present invention, since the screen grid adsorbs the cations, only neutral radical particles can reach the wafer surface, and an antenna effect is induced even if the plasma density is not uniform. Never.

[0013] An electronic flood gun can also neutralize the wafer, thereby effectively preventing the antenna effect.

Hereinafter, the present invention will be described in detail with reference to embodiments and drawings.

[0015]

FIG. 2 shows a preferred embodiment of the present invention.
This will be described below. As shown in FIG. 2, an interconnect line 202 is formed on a substrate 200 (also referred to as a wafer).
a, 202b are formed. A liner layer 204 having no plasma ion damage (non-plasma-ion-damage) (hereinafter referred to as NPID) is formed over the substrate 200 by the operation and effect of the present invention. Then, a dielectric layer 206 is formed on the NPID liner layer 204, and the NPID layer is formed by, for example, an HDPCVD process.

FIG. 3 is a schematic cross-sectional view of an HDPCVD apparatus according to a preferred embodiment of the present invention. As shown in FIGS. 2 and 3, the NPID liner layer 204 includes, for example,
It is formed at an early stage of a dielectric deposition process such as an HDPCVD process. The screen grid 302 is slightly larger in size than the area size of the wafer 300, and as shown in FIG.
It is installed just above 00. Screen grid 30
2 is negatively biased. The size of the grid is, for example, about 3 × 3 mm ² to about 10 × 10 mm ² as shown in FIG.

Since a negative bias is applied to the screen grid 302, plasma cations are adsorbed to the grid. As a result, only the neutral radical particles reach the wafer 300. Thus, the NPID liner layer 204 can be formed at an early stage of the HDPCVD process. This N
As a result of the formation of the PID liner layer 204, the interconnect lines 202a and 202b are not impacted by charged ions. In this way, even if the plasma density is non-uniform, especially in the early stages of the process, the interconnect lines 202a, 2
02b is not charged. Therefore, no potential difference occurs. Furthermore, the interconnect lines 202a, 202
02b can be effectively prevented.

Once the NPID liner layer 204 has been deposited to a predetermined thickness, the negative bias on the screen grid 302 is turned off. Then HDPC
The VD process is performed as usual to form the dielectric layer 206.

The interconnect lines 202a and 202b
Is covered by the NPID liner layer 204, so that even if the charged ions bombard the wafer 300 during the deposition of the dielectric layer 206, they are covered by the NPID liner layer 204, thereby forming the interconnect line 202a. , 202b are not damaged. More particularly, even after the dielectric layer 206 has been formed, the interconnect lines 202a, 202b remain uncharged, which does not induce an antenna effect.

In the embodiment shown in FIGS. 2 and 3, a negative voltage is applied and the NPID liner layer is formed using a screen grid whose area is slightly larger than the wafer area. In the present invention,
The method is not limited to only the method using the screen grid 302. An alternative is to use an electronic flood gun 304, which is widely used in ion implanters. The electronic flood gun 304 is also a wafer 300
Placed directly above. In the initial stage of the deposition, the electronic flood gun 304 is operated to activate the wafer 3.
The NPID liner layer 204 is formed by neutralizing the positive charges stored in the NPID. Similarly, the interconnect lines 202a, 202b are not charged and no antenna effect is induced.

The operation of the electronic flood gun 304 is stopped after depositing the NPID liner layer 204 until the thickness becomes a predetermined thickness. The HDPCVD process is then performed as usual to form the dielectric layer 206.

Interconnect lines 202a, 202b
Is covered by the NPID liner layer 204, so that even if the charged ions bombard the wafer 300 during the deposition of the dielectric layer 206, they are covered by the NPID liner layer 204, thereby forming the interconnect line 202a. , 202b are not damaged. More particularly, even after the dielectric layer 206 has been formed, the interconnect lines 202a, 202b remain uncharged, which does not induce an antenna effect.

FIG. 3 also shows other elements of the deposition apparatus, such as a reaction chamber dome 306, an electrostatic chuck (ESC) 308, a turbo pump 310,
A high conductance chamber 312, a hemispherical induction coil 314, and the like are included. However, since these elements are conventional, description thereof will be omitted.

Although the device of the present invention is primarily used for forming intermetal dielectric layers, it can be used in other similar manufacturing processes including, for example, forming shallow trench isolation (STI) structures. Can also be used widely.

Further, the apparatus according to the present invention is provided with an HDPC
There is no necessity to be limited only to the combination with the VD device,
For example, a transformer coupled plasma (TCP) CV
D (chemical vapor deposition) or inductively coupled plasma (ICP) CVD
Can also be used.

As mentioned above, the apparatus of the present invention includes a screen grid or electron flood gun with at least a negative bias, which is incorporated into the plasma deposition apparatus and placed directly above the wafer to be processed. Or is installed. The screen grid completely filters the cations in the plasma, and the electron flood gun neutralizes the charge stored on the wafer. As a result, the wafer can be prevented from being bombarded by cations in the initial stage of depositing the dielectric layer. Thus, a liner without plasma ion damage can be formed, thus ensuring that the dielectric layer is deposited.

The embodiments described above are not intended to limit the invention, and numerous modifications and variations can be made without departing from the scope or spirit of the invention. It is intended to broadly cover the technical scope described in the claims.

[0028]

According to the present invention, since the screen grid adsorbs the cations, only neutral radical particles can reach the wafer surface, and the antenna effect is induced even if the plasma density is not uniform. It will not be done.

Further, the electron flood gun neutralizes the wafer and effectively prevents the antenna effect from being induced.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor structure of a typical semiconductor device having a multi-level interconnect.

FIG. 2 is a schematic cross-sectional view of a semiconductor structure having an intermetal dielectric layer in a preferred embodiment of the present invention.

FIG. 3 shows an HDPC in a preferred embodiment of the present invention.
FIG. 2 is a schematic sectional view of a VD device.

FIG. 4 is a perspective view of a screen grid in a preferred embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 200 substrate 202a, 202b interconnect line 204 liner layer without plasma ion damage 206 dielectric layer 300 wafer 302 screen grid 304 electron flood gun

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4K030 CA12 FA01 FA04 KA20 KA30 KA49 LA01 5F045 AA08 BB16 EH06 EH11 EH20 EM05

Claims (19)

[Claims] An apparatus for preventing plasma damage on a substrate suitable for use in a process of forming a dielectric layer in a plasma apparatus, comprising: an apparatus having an area slightly larger than an area size of a wafer to be processed; With a screen grid, this screen grid is placed directly above the wafer, and is initially negatively biased and filtered at least in the plasma cations to provide a negative Screen grid that allows for the formation of a plasma ion free (non-plasma-ion-damaged) liner layer before the dielectric layer is deposited by blocking the bias. 2. The method of claim 1, wherein the step of depositing the dielectric layer is included in a manufacturing process selected from a group consisting of a process of forming an intermetal dielectric layer and a process of forming the device having a shallow trench isolation structure.
Equipment. 3. The apparatus of claim 1, wherein said plasma device is one selected from the group consisting of a high density plasma chemical vapor deposition device, a transformer coupled plasma device and an inductively coupled plasma device. 4. The apparatus of claim 1, wherein said screen grid has a grid size from about 3 × 3 mm ² to about 10 × 10 mm ² . 5. The apparatus of claim 1, wherein said plasma device is a high density plasma chemical vapor deposition device. 6. The step of depositing the dielectric layer,
6. The apparatus of claim 5, wherein the apparatus is included in a manufacturing process selected from the group consisting of a process of forming an intermetal dielectric layer and a process of forming a shallow trench isolation structure. 7. The apparatus of claim 6, wherein said screen grid has a grid size from about 3 × 3 mm ² to about 10 × 10 mm ² . 8. An apparatus for preventing plasma damage on a substrate suitable for use in a process of forming a dielectric layer in a plasma device, comprising: an electron flood gun disposed directly above a substrate in a plasma device. Operating during the early stages of depositing the dielectric layer to neutralize the charge stored on the wafer before the dielectric flood gun is stopped to ensure that the dielectric layer is deposited. An electron flood gun that neutralizes the charge and forms a liner on the wafer without plasma ion damage. 9. The manufacturing process selected from the group consisting of a process of forming an intermetal dielectric layer and a process of forming the device having a shallow trench isolation structure, wherein the step of depositing the dielectric layer is included.
Equipment. 10. The apparatus of claim 8, wherein said plasma device is one selected from the group consisting of a high-density plasma chemical vapor deposition device, a transformer coupled plasma device and an inductively coupled plasma device. 11. The apparatus of claim 8, wherein said plasma device is a high density plasma chemical vapor deposition device. 12. The step of depositing said dielectric layer comprises:
12. The apparatus of claim 11, wherein the apparatus is included in a manufacturing process selected from the group consisting of a process of forming an intermetal dielectric layer and a process of forming a shallow trench isolation structure. 13. An apparatus for preventing plasma damage on a substrate suitable for use in a process of forming a dielectric layer in a plasma apparatus, comprising: an area slightly larger than an area size of a wafer to be processed; The screen grid is placed directly above the wafer and is initially negatively biased and filtered at least during the initial step of depositing the dielectric layer by filtering out plasma cations. An initial stage of the position process, a screen grid that is negatively biased and filters the cations of the plasma; and an electron flood gun positioned directly above the substrate in a plasma device, depositing said dielectric layer. Operating during the early stages of the process, stopping the electronic flood gun ensures that the dielectric layer is Providing an electron flood gun to neutralize the charge stored on the wafer prior to being deposited, thereby forming a liner free of plasma ion damage during an early stage of depositing the dielectric layer; The dielectric layer is normally deposited by applying the negative bias and stopping the electron flood gun. 14. The method of claim 1, wherein the step of depositing the dielectric layer is included in a manufacturing process selected from the group consisting of a process of forming an intermetal dielectric layer and a process of forming the device having a shallow trench isolation structure.
The device of 3. 15. The apparatus of claim 13, wherein said plasma device is one selected from the group consisting of a high-density plasma chemical vapor deposition device, a transformer coupled plasma device and an inductively coupled plasma device. 16. The apparatus of claim 13, wherein said screen grid has a grid size from about 3 × 3 mm ² to about 10 × 10 mm ² . 17. The apparatus of claim 13, wherein said plasma device is a high density plasma chemical vapor deposition device. 18. The step of depositing said dielectric layer comprises:
18. The apparatus of claim 17, wherein the apparatus is included in a manufacturing process selected from the group consisting of a process of forming an intermetal dielectric layer and a process of forming a shallow trench isolation structure. 19. The apparatus of claim 17, wherein said screen grid has a grid size from about 3 × 3 mm ² to about 10 × 10 mm ² .