TWI467650B - Plasma etch methods and computer-readable memory media - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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Description
本發明關於,對基板上形成之氧化膜介由遮罩層進行電漿蝕刻的電漿蝕刻方法及記憶執行該電漿蝕刻方法的控制程式之電腦可讀取之記憶媒體。The present invention relates to a plasma etching method for plasma etching an oxide film formed on a substrate through a mask layer, and a computer readable memory medium for memorizing a control program for performing the plasma etching method.
於半導體裝置製程中,對被處理基板之半導體晶圓,藉由微影成像技術工程形成光阻圖案,以其作為遮罩而進行蝕刻。In the semiconductor device process, a photoresist pattern is formed on a semiconductor wafer of a substrate to be processed by a lithography imaging technique, and is etched as a mask.
近年來隨半導體裝置之微細化而對於蝕刻益加要求微細加工。對應於該微細化,遮罩使用之光阻之膜厚變薄,使用之光阻之亦由K rF光阻(亦即以K rF氣體為發光源之雷射光進行曝光的光阻)移行至可形成約0.13 μm以下圖案開口的ArF光阻(亦即以ArF氣體為發光源之更短波長雷射光進行曝光的光阻)。In recent years, with the miniaturization of semiconductor devices, fine processing has been required for etching. Corresponding to the miniaturization, the film thickness of the photoresist used for the mask is thinned, and the photoresist used is also moved by the KrF photoresist (that is, the photoresist exposed by the laser light using the K rF gas as the light source) to An ArF photoresist having a pattern opening of about 0.13 μm or less (that is, a photoresist that is exposed by a shorter-wavelength laser light having an ArF gas as a light source) can be formed.
但是ArF光阻之抗蝕刻性低,因此於K rF光阻幾乎未曾發生之蝕刻中途之表面粗糙度會產生。因此,於開口部內壁面會存在縱條紋,而產生開口部擴大(CD之擴大)之問題,再加上光阻膜厚之變薄,導致於產生無法以良好蝕刻選擇比形成蝕刻通孔之不良情況。However, since the ArF photoresist has low etching resistance, surface roughness in the middle of etching in which the K rF photoresist hardly occurs is generated. Therefore, there is a problem that the vertical stripe is formed on the inner wall surface of the opening, and the opening portion is enlarged (the expansion of the CD), and the thickness of the photoresist film is thinned, resulting in a failure to form an etched via hole with a good etching selectivity. Happening.
針對此問題,專利文獻1揭示以下技術:於被蝕刻層上形成非晶質碳膜作為犧牲硬質遮罩,於其上形成圖案化之光阻膜,以光阻圖案作為遮罩蝕刻非晶質碳膜,至少以非晶質碳膜作為蝕刻遮罩藉由通常使用之CF系氣體進行被蝕刻層之蝕刻。藉由該技術可以某種程度解消蝕刻選擇性及形狀性之問題。To solve this problem, Patent Document 1 discloses a technique of forming an amorphous carbon film on an etched layer as a sacrificial hard mask, forming a patterned photoresist film thereon, and etching the amorphous film with a photoresist pattern as a mask. In the carbon film, at least the amorphous carbon film is used as an etching mask to etch the layer to be etched by a commonly used CF-based gas. The problem of etching selectivity and shape can be solved to some extent by this technique.
但是,例如DRAM之容量蝕刻中要求將開口為80nm、深度2 μm之極高深寬比(aspect ratio)之通孔(hole)形成於氧化膜,次一世代要求68nm、次次一世代要求58nm等益加變窄之區間口,上述專利文獻1之技術,對於此種尺寸之通孔,難以具有充分之蝕刻選擇性、於未產生弓形度(bowing,形狀異常)等之良好形狀性下予以形成。However, for example, in the capacity etching of a DRAM, a hole having an opening ratio of 80 nm and a depth of 2 μm is required to be formed in an oxide film, which requires 68 nm for the next generation and 58 nm for the next generation. In the section of the above-mentioned Patent Document 1, it is difficult for the through hole of such a size to have sufficient etching selectivity and to form a good shape such as bowing (shape abnormality). .
專利文獻1:特開2006-41486號公報Patent Document 1: JP-A-2006-41486
本發明有鑑於上述習知問題,目的在於提供一種電漿蝕刻方法,其對氧化膜蝕刻形成微細、且高深寬比之通孔時,可以兼顧良好蝕刻選擇性及形狀性。The present invention has been made in view of the above conventional problems, and it is an object of the invention to provide a plasma etching method which can achieve both good etching selectivity and shape when etching an oxide film to form a fine via having a high aspect ratio.
又,本發明目的在於提供一種電腦可讀取之記憶媒體,其記憶有執行該電漿蝕刻方法之程式。Further, it is an object of the present invention to provide a computer readable memory medium having a program for performing the plasma etching method.
為解決上述問題,本發明第1觀點提供之電漿蝕刻方法,係使用電漿蝕刻裝置對基板上形成之氧化膜介由硬質遮罩進行電漿蝕刻者,該電漿蝕刻裝置為,在內部可真空排氣之處理容器內設置下部電極作為基板載置台之功能,及和下部電極呈對向形成之上部電極,於上述上部電極或下部電極施加電漿產生用之相對高頻之高頻電力,於上述下部電極施加偏壓用之相對低頻之高頻電力,於上述上部電極施加直流電壓,使供給至上述處理容器內之處理氣體電漿化而進行電漿蝕刻者;其特徵為具備以下工程:於上述處理容器內搬入依序被形成有蝕刻對象之氧化膜、硬質遮罩層、圖案化之光阻的基板,使其載置於上述下部電極的工程;對上述處理容器內供給含有Cx Fy (其中x為3以下之整數,y為8以下之整數)、C4 F8 、稀有氣體、O2之處理氣體的工程;於上述上部電極或上述下部電極施加高頻電力而產生上述處理氣體之電漿的工程;於上述下部電極施加偏壓用高頻電力的工程;及於上述上部電極施加直流電壓的工程。In order to solve the above problems, a plasma etching method according to a first aspect of the present invention provides a plasma etching method in which an oxide film formed on a substrate is plasma-etched through a hard mask using a plasma etching apparatus. The lower electrode is provided as a substrate mounting table in the vacuum evacuation processing container, and the upper electrode is formed opposite to the lower electrode, and a relatively high frequency high frequency power for generating plasma is applied to the upper electrode or the lower electrode. Applying a relatively low frequency high frequency power to the lower electrode, applying a DC voltage to the upper electrode, and plasma-treating the processing gas supplied into the processing container to perform plasma etching; In the processing container, a substrate in which an oxide film to be etched, a hard mask layer, and a patterned photoresist are sequentially placed in the processing container to be placed on the lower electrode, and the inside of the processing container is supplied C x F y (where x is an integer below 3, y is an integer less than 8), C 4 F 8 , rare gas, O 2 processing gas; A process of applying a high-frequency power to the lower electrode or a plasma of the processing gas; applying a high-frequency power for biasing to the lower electrode; and applying a DC voltage to the upper electrode.
本發明第2觀點提供之電漿蝕刻方法,係使用電漿蝕刻裝置者,該電漿蝕刻裝置為,在內部可真空排氣之處理容器內設置下部電極作為基板載置台之功能,及和下部電極呈對向形成之上部電極,於上述下部電極施加兼作為電漿產生用與偏壓用之高頻電力,於上述上部電極施加直流電壓,使供給至上述處理容器內之處理氣體電漿化而進行電漿蝕刻者;其特徵為具備以下工程:於上述處理容器內搬入依序被形成有蝕刻對象之氧化膜、硬質遮罩層、圖案化之光阻的基板,使其載置於上述下部電極的工程;對上述處理容器內供給含有Cx Fy (其中x為3以下之整數,y為8以下之整數)、C4 F8 、稀有氣體、O2 之處理氣體的工程;於上述下部電極施加兼作為電漿產生用與偏壓用之高頻電力而產生上述處理氣體之電漿之同時,施加偏壓的工程;及於上述上部電極施加直流電壓的工程。According to a second aspect of the present invention, in a plasma etching method, a plasma etching apparatus is provided, wherein the plasma etching apparatus has a function of providing a lower electrode as a substrate mounting table in a processing chamber capable of evacuating inside, and a lower portion The electrode is formed to face the upper electrode, and the high-frequency electric power for generating plasma and bias is applied to the lower electrode, and a DC voltage is applied to the upper electrode to plasma the processing gas supplied into the processing container. In the plasma etching apparatus, the substrate is provided with a substrate in which an etching film, a hard mask layer, and a patterned photoresist are sequentially formed in the processing container, and is placed on the substrate. Engineering of the lower electrode; a process for supplying a processing gas containing C x F y (where x is an integer of 3 or less, y is an integer of 8 or less), C 4 F 8 , a rare gas, or O 2 in the processing container; The lower electrode applies a process of applying a bias voltage while generating a plasma of the processing gas as a plasma generating and high-frequency power for biasing, and applying a bias to the upper electrode. Project voltage.
於上述第1或第2觀點,上述硬質遮罩層較好是可使用非晶質碳膜。上述Cx Fy 較好是C3 F8 或CF4 。上述Cx Fy 使用C3 F8 時較好是其流量為上述C4 F8 之流量以上。上述直流電壓之絕對值較好是為800~1200V。上述稀有氣體較好是使用Ar或Xe。In the first or second aspect, the hard mask layer is preferably an amorphous carbon film. The above C x F y is preferably C 3 F 8 or CF 4 . Above using C x F y C 3 F 8 flow rate is better when the above-mentioned C 4 F 8 flow rate of the above. The absolute value of the above DC voltage is preferably 800 to 1200V. The above rare gas is preferably Ar or Xe.
本發明之電漿蝕刻方法,形成區間口為70~90nm、深寬比為1:15~1:25之通孔時特別有效。The plasma etching method of the present invention is particularly effective when forming a via hole having a section opening of 70 to 90 nm and an aspect ratio of 1:15 to 1:25.
本發明第3觀點提供之電腦可讀取之記憶媒體,係記憶有控制程式,該控制程式,係於電腦上動作而控制電漿蝕刻裝置者,該電漿蝕刻裝置為,在內部可真空排氣之處理容器內設置下部電極作為基板載置台之功能,及和下部電極呈對向形成之上部電極,於上述上部電極或下部電極施加電漿產生用之相對高頻之高頻電力,而且,於上述下部電極施加偏壓用之相對低頻之高頻電力、或於上述下部電極施加兼作為電漿產生用與偏壓用之高頻電力,於上述上部電極施加直流電壓,使供給至上述處理容器內之處理氣體電漿化而進行電漿蝕刻者;其特徵為:上述控制程式,執行時使申請專利範圍第1至14項中任一項之電漿蝕刻方法被進行而使電腦控制上述電漿蝕刻裝置。According to a third aspect of the present invention, a computer-readable memory medium is a memory control program, and the control program is controlled by a computer to control a plasma etching device, and the plasma etching device is internally vacuum-dischargeable. a lower electrode is provided in the gas processing container as a substrate mounting table, and an upper electrode is formed opposite to the lower electrode, and a relatively high frequency high frequency power for generating plasma is applied to the upper electrode or the lower electrode. Applying a relatively low-frequency high-frequency power for biasing the lower electrode or applying high-frequency power for plasma generation and biasing to the lower electrode, applying a DC voltage to the upper electrode, and supplying the same to the processing A plasma etching process is performed by plasma-treating a processing gas in the container; wherein the control program is executed, and the plasma etching method according to any one of claims 1 to 14 is performed to cause the computer to control the above Plasma etching device.
以下參照圖面說明本發明具體之實施形態。Specific embodiments of the present invention will be described below with reference to the drawings.
圖1為本發明之實施使用之電漿蝕刻裝置之一例之概略斷面圖。Fig. 1 is a schematic cross-sectional view showing an example of a plasma etching apparatus used in the practice of the present invention.
該電漿蝕刻裝置構成為容量耦合型平行平板電漿蝕刻裝置,具有例如表面施予陽極氧化處理的鋁構成之大略圓筒狀腔室(處理容器)10。該腔室(處理容器)10被安全接地。The plasma etching apparatus is configured as a capacity coupling type parallel plate plasma etching apparatus, and has, for example, a substantially cylindrical chamber (processing container) 10 made of aluminum surface-anodic-treated. The chamber (processing vessel) 10 is safely grounded.
於腔室10之底部,介由陶瓷等構成之絕緣板12配置圓柱狀承受器支撐台14。於承受器支撐台14之上設置例如鋁構成之承受器16。承受器16構成下部電極,於其上載置被處理基板之半導體晶圓W。At the bottom of the chamber 10, a cylindrical susceptor support 14 is disposed through an insulating plate 12 made of ceramic or the like. A susceptor 16 made of, for example, aluminum is placed above the susceptor support table 14. The susceptor 16 constitutes a lower electrode on which the semiconductor wafer W on which the substrate to be processed is placed.
於承受器16之上面設置靜電夾頭18可以靜電力吸附保持半導體晶圓W。該靜電夾頭18,具有使導電膜構成電極20以一對絕緣層或絕緣薄板挾持之構造,於電極20電連接直流電源22。藉由直流電源22之直流電壓產生之庫侖力等靜電力使半導體晶圓W被吸附保持於靜電夾頭18。An electrostatic chuck 18 is disposed on the top of the susceptor 16 to electrostatically attract and hold the semiconductor wafer W. The electrostatic chuck 18 has a structure in which the conductive film constituent electrode 20 is held by a pair of insulating layers or insulating sheets, and the electrode 20 is electrically connected to the DC power source 22. The semiconductor wafer W is adsorbed and held by the electrostatic chuck 18 by an electrostatic force such as a Coulomb force generated by a DC voltage of the DC power source 22.
於靜電夾頭(半導體晶圓W)18周圍、在承受器16之上面設置例如矽構成之導電性聚磁環(補正環)24用於補正蝕刻之均勻性。於承受器16及承受器支撐台14之側面設置例如石英構成之圓筒狀內壁構件26。A conductive magnetic collecting ring (correcting ring) 24 made of, for example, tantalum is provided around the electrostatic chuck (semiconductor wafer W) 18 on the upper surface of the susceptor 16 for correcting the uniformity of etching. A cylindrical inner wall member 26 made of, for example, quartz is provided on the side surface of the susceptor 16 and the susceptor support table 14.
於承受器支撐台14之內部、例如於圓周上設置冷媒室28。於該冷媒室28,藉由外部設置之冷卻單元(未圖示)介由配管30a、30b被循環供給特定溫度之冷媒例如冷卻水,藉由冷媒之溫度可控制承受器16上之半導體晶圓W之處理溫度。A refrigerant chamber 28 is provided inside the susceptor support table 14, for example, on the circumference. In the refrigerant chamber 28, a cooling medium (not shown) provided outside is circulated to supply a specific temperature refrigerant such as cooling water through the pipes 30a and 30b, and the semiconductor wafer on the susceptor 16 can be controlled by the temperature of the refrigerant. W processing temperature.
另外,來自導熱氣體供給機構(未圖示)之導熱氣體例如He氣體介由氣體供給管32被供給至靜電夾頭18之上面與半導體晶圓W之背面之間。Further, a heat transfer gas such as He gas from a heat transfer gas supply means (not shown) is supplied between the upper surface of the electrostatic chuck 18 and the back surface of the semiconductor wafer W via the gas supply pipe 32.
於承受器16之上方、和承受器16呈對向平行設置上部電極34。上部電極34與下部電極16之間的空間成為電漿產生空間。上部電極34,係和下部電極之承受器16上之半導體晶圓W呈對向,而形成和電漿產生空間接觸之面、亦即對向面。The upper electrode 34 is disposed in parallel with the susceptor 16 above the susceptor 16. The space between the upper electrode 34 and the lower electrode 16 becomes a plasma generating space. The upper electrode 34 is opposed to the semiconductor wafer W on the susceptor 16 of the lower electrode to form a surface in contact with the plasma, that is, the opposite surface.
上部電極34,係介由絕緣性遮蔽構件42被支撐於腔室10之上部,由以下構成:形成和承受器16間之對向面、且具有多數噴出孔37的電極板36;及可裝拆自如地支撐該電極板36,由導電性材料、例如表面施予陽極氧化處理的鋁構成之水冷構造之電極支撐體38。電極板36,較好是焦耳熱少的低電阻導電體或半導體,又,如後述說明,就阻劑強化觀點而言較好是含矽物質。由此一觀點而言電極板36較好是以矽或SiC構成。於電極支撐體38內部設置氣體擴散室40,由該氣體擴散室40使連通於噴出孔37之多數氣體流通孔41朝下方延伸。The upper electrode 34 is supported by the insulating shielding member 42 on the upper portion of the chamber 10, and is configured to form an electrode plate 36 having a plurality of ejection holes 37 opposite to the opposing surface between the susceptor 16 and The electrode support 36 is detachably supported, and an electrode support 38 of a water-cooling structure composed of an electrically conductive material, for example, anodized aluminum is applied to the surface. The electrode plate 36 is preferably a low-resistance conductor or a semiconductor having less Joule heat, and as described later, it is preferably a ruthenium-containing substance from the viewpoint of resist reinforcement. From this point of view, the electrode plate 36 is preferably made of tantalum or SiC. A gas diffusion chamber 40 is provided inside the electrode support body 38, and the gas diffusion chamber 40 extends a plurality of gas flow holes 41 that communicate with the discharge holes 37 downward.
於電極支撐體38形成氣體導入口62用於對氣體擴散室40導入處理氣體,於該氣體導入口62連接氣體供給管64,於該氣體供給管64連接處理氣體供給源66。於該氣體供給管64,由上流側起依序設置MFC(mass flow controller,流量控制器)68及開關閥70(亦可取代MFC改用FCS)。由處理氣體供給源66,作為蝕刻用處理氣體,使含有Cx Fy (其中x為3以下之整數,y為8以下之整數)、C4 F8 、稀有氣體、O2 之處理氣體,由氣體供給管64至氣體擴散室40,介由氣體流通孔41及噴出孔37以噴氣狀被噴出至電漿產生空間。亦即上部電極34作為供給處理氣體的噴氣頭之功能。A gas introduction port 62 is formed in the electrode support body 38 for introducing a processing gas into the gas diffusion chamber 40, and a gas supply pipe 64 is connected to the gas introduction port 62. The gas supply pipe 64 is connected to the gas supply pipe 64. In the gas supply pipe 64, an MFC (mass flow controller) 68 and an on-off valve 70 are provided in order from the upstream side (the FFC can also be used instead of the MFC). The processing gas supply source 66 is a processing gas for etching, and contains a processing gas containing C x F y (where x is an integer of 3 or less, y is an integer of 8 or less), C 4 F 8 , a rare gas, and O 2 . The gas supply pipe 64 to the gas diffusion chamber 40 are ejected into the plasma generation space in a jet shape through the gas circulation holes 41 and the discharge holes 37. That is, the upper electrode 34 functions as a jet head that supplies a process gas.
於上部電極34,介由匹配器46及供電棒44電連接第1高頻電源48。第1高頻電源48輸出10MHz以上之頻率例如60MHz之高頻電力。匹配器46用於整合第1高頻電源48之內部(或輸出)阻抗與負荷阻抗,具有在腔室10內產生電漿時使第1高頻電源48之輸出阻抗與負荷阻抗成為一致之功能。匹配器46之輸出端子連接於供電棒44之上端。The first high frequency power source 48 is electrically connected to the upper electrode 34 via the matching unit 46 and the power supply rod 44. The first high-frequency power source 48 outputs a high-frequency power of a frequency of 10 MHz or more, for example, 60 MHz. The matching unit 46 is for integrating the internal (or output) impedance and the load impedance of the first high-frequency power source 48, and has a function of matching the output impedance of the first high-frequency power source 48 with the load impedance when plasma is generated in the chamber 10. . The output terminal of the matcher 46 is connected to the upper end of the power supply rod 44.
另外,於上部電極34,除第1高頻電源48以外,電連接可變直流電源50。可變直流電源50亦可為雙極性電源。具體言之為,該可變直流電源50介由匹配器46及供電棒44連接上部電極34,藉由ON(導通)/OFF(切斷)開關52可進行供電。可變直流電源時序產生器50之極性、電流、電壓及ON/OFF開關52之ON/OFF係由控制器51控制。Further, the upper electrode 34 is electrically connected to the variable DC power source 50 in addition to the first high frequency power source 48. The variable DC power source 50 can also be a bipolar power source. Specifically, the variable DC power supply 50 is connected to the upper electrode 34 via the matching unit 46 and the power supply rod 44, and is powered by the ON/OFF switch 52. The polarity, current, voltage of the variable DC power supply timing generator 50 and ON/OFF of the ON/OFF switch 52 are controlled by the controller 51.
如圖2所示,匹配器46具有:由第1高頻電源48之供電線49分支設置之第1可變電容器54,及設置於供電線49之分支點下流側的第2可變電容器56,藉由彼等發揮上述功能。於匹配器46設置陷波用濾波器58,使來自第1高頻電源48之高頻(例如60MHz),及來自後述第2高頻電源之高頻(例如2MHz)被陷波,而將直流電壓電流(以下單稱為直流電壓)有效供給至上部電極34。亦即,來自可變直流電源50之直流電流介由濾波器58被連接於供電線49。濾波器58由線圈59及電容器60構成,藉由彼等使來自第1高頻電源48之高頻及來自後述第2高頻電源之高頻被陷波。As shown in FIG. 2, the matching unit 46 has a first variable capacitor 54 branched from the power supply line 49 of the first high-frequency power source 48, and a second variable capacitor 56 provided on the downstream side of the branch point of the power supply line 49. By playing the above functions. The notch filter 58 is provided in the matching unit 46, so that a high frequency (for example, 60 MHz) from the first high-frequency power source 48 and a high frequency (for example, 2 MHz) from a second high-frequency power source to be described later are trapped, and DC is applied. A voltage current (hereinafter simply referred to as a direct current voltage) is effectively supplied to the upper electrode 34. That is, the direct current from the variable DC power source 50 is connected to the power supply line 49 via the filter 58. The filter 58 is composed of a coil 59 and a capacitor 60, and the high frequency from the first high-frequency power source 48 and the high-frequency power source from the second high-frequency power source described later are trapped.
以自腔室10之側壁起延伸至較上部電極34之高度位置更上方的方式設置圓筒狀接地導體10a,該圓筒狀接地導體10a之天壁部分藉由筒狀絕緣構件44a而由上部供電棒44。The cylindrical ground conductor 10a is provided so as to extend from the side wall of the chamber 10 to a position higher than the height of the upper electrode 34, and the wall portion of the cylindrical ground conductor 10a is upper by the cylindrical insulating member 44a. Power supply rod 44.
於下部電極之承受器16,介由匹配器88電連接第2高頻電源90。由第2高頻電源90對下部電極之承受器16供給高頻電力而使離子被引入半導體晶圓W側。第2高頻電源90,係輸出300kHz~13.56MHz範圍內之頻率、例如2MHz之高頻電力。匹配器88用於整合第2高頻電源90之內部(或輸出)阻抗與負荷阻抗,具有在腔室10內產生電漿時使第2高頻電源90之輸出阻抗與負荷阻抗成為一致之功能。匹配器46之輸出端子連接於供電棒44之上端。The second high frequency power supply 90 is electrically connected to the susceptor 16 of the lower electrode via a matching unit 88. The second high-frequency power source 90 supplies high-frequency power to the susceptor 16 of the lower electrode to introduce ions into the semiconductor wafer W side. The second high-frequency power supply 90 outputs a high-frequency power of a frequency in the range of 300 kHz to 13.56 MHz, for example, 2 MHz. The matching unit 88 is for integrating the internal (or output) impedance and the load impedance of the second high-frequency power source 90, and has a function of matching the output impedance of the second high-frequency power source 90 with the load impedance when plasma is generated in the chamber 10. . The output terminal of the matcher 46 is connected to the upper end of the power supply rod 44.
另外,於上部電極34,電連接低通濾波器(LPF)92,可以在不通過來自第1高頻電源48之高頻(例如60MHz)情況下,使來自第2高頻電源90之高頻(例如2MHz)通往接地。低通濾波器(LPF)92,較好是由LR濾波器或LC濾波器構成,但僅以1條導線亦可對來自第1高頻電源48之高頻(例如60MHz)提供足夠大之電抗,因此亦可以使用。另外,於下部電極之承受器16電連接高通濾波器(HPF)94,可以使來自第1高頻電源48之高頻通往接地。Further, the upper electrode 34 is electrically connected to the low pass filter (LPF) 92, and the high frequency from the second high frequency power supply 90 can be made without passing through the high frequency (for example, 60 MHz) from the first high frequency power supply 48. (eg 2MHz) to ground. The low pass filter (LPF) 92 is preferably composed of an LR filter or an LC filter, but can provide a sufficiently large reactance to a high frequency (for example, 60 MHz) from the first high frequency power supply 48 by only one wire. Therefore, it can also be used. Further, the high-pass filter (HPF) 94 is electrically connected to the susceptor 16 of the lower electrode, so that the high frequency from the first high-frequency power source 48 can be grounded.
於腔室10之底部設置排氣口80,於該排氣口80介由排氣管82連接排氣裝置84。排氣裝置84具有渦旋分子泵等之真空泵,可將腔室10內減壓至所要真空度。又,於腔室10之側壁設置半導體晶圓W之搬出入口85,該搬出入口85可藉由柵閥86進行開/閉。又,沿著腔室10之內壁裝拆自如地設置沈積物防止構件11,可防止蝕刻副生成物(沈積物)附著於腔室10。亦即沈積物防止構件11構成腔室壁。又,沈積物防止構件11亦設於內壁構件26外周。於腔室10之底部之腔室壁側之沈積物防止構件11與內壁構件26側之沈積物防止構件11之間設置排氣板83。沈積物防止構件11及排氣板83可使用於鋁構件覆蓋Y2 O3 等之陶瓷者。An exhaust port 80 is provided at the bottom of the chamber 10, and the exhaust port 84 is connected to the exhaust device 84 via the exhaust pipe 82. The venting device 84 has a vacuum pump such as a vortex molecular pump, and can depressurize the inside of the chamber 10 to a desired degree of vacuum. Further, a carry-out port 85 of the semiconductor wafer W is provided on the side wall of the chamber 10, and the carry-out port 85 can be opened/closed by the gate valve 86. Moreover, the deposit preventing member 11 is detachably provided along the inner wall of the chamber 10, and the etching by-product (deposit) can be prevented from adhering to the chamber 10. That is, the deposit preventing member 11 constitutes a chamber wall. Further, the deposit preventing member 11 is also provided on the outer circumference of the inner wall member 26. An exhaust plate 83 is provided between the deposit preventing member 11 on the chamber wall side of the bottom of the chamber 10 and the deposit preventing member 11 on the inner wall member 26 side. The deposit preventing member 11 and the exhaust plate 83 can be used for a ceramic member in which an aluminum member covers Y 2 O 3 or the like.
在和構成沈積物防止構件11之腔室內壁的部分之晶圓W大略同一高度的部分,設置以DC的方式連接於接地的導電性構件(GND塊)91,如此則可發揮異常放電之防止效果。The portion of the wafer W constituting the inner wall of the chamber of the deposit preventing member 11 is disposed at substantially the same height, and is electrically connected to the grounded conductive member (GND block) 91 in a DC manner, thereby preventing abnormal discharge. effect.
電漿處理裝置之各構成部,係被連接於控制部(全體控制裝置)95而被控制。於控制部95連接有工程管理者管理電漿蝕刻裝置而進行指令之輸入操作的鍵盤、使電漿蝕刻裝置之稼動狀態可視化予以顯示的顯示器等構成之使用者介面96。Each component of the plasma processing apparatus is controlled by being connected to a control unit (all control unit) 95. The control unit 95 is connected to a user interface 96 including a keyboard that the engineering manager manages the plasma etching apparatus to input the command, and a display that visually displays the state of the plasma etching apparatus.
於控制部95連接記憶部97,用於儲存控制程式,其可使電漿處理裝置執行之各種處理於控制部95之控制下被實現,或程式(程序,recipe),其可依據處理條件使電漿處理裝置之各構成部執行處理。程序,可記憶於硬碟或半導體記憶體,或在收容於CDROM、DVD等可攜帶型電腦可讀取之記憶媒體狀態下被設定於記憶部97之特定位置亦可。The control unit 95 is connected to the storage unit 97 for storing a control program, which can be implemented under the control of the control unit 95, or a program (recipe), which can be made according to processing conditions. Each component of the plasma processing apparatus performs processing. The program may be stored in a hard disk or a semiconductor memory, or may be set to a specific position of the memory unit 97 in a state of being stored in a portable medium readable by a portable computer such as a CDROM or a DVD.
必要時可依據使用者介面96之指示等,由記憶部97叫出任意程序於控制部95執行,於控制部95控制下進行電漿處理裝置之所要處理。If necessary, the memory unit 97 may call any program to be executed by the control unit 95 in accordance with the instruction of the user interface 96, and the processing of the plasma processing apparatus may be performed under the control of the control unit 95.
以下說明上述構成之電漿蝕刻裝置實施之本實施形態之一實施形態之電漿蝕刻方法。Hereinafter, a plasma etching method according to an embodiment of the embodiment of the plasma etching apparatus configured as described above will be described.
其中,作為被處理體之半導體晶圓W,係如圖3所示使用於矽基板101上依序形成阻蝕膜102、蝕刻對象之氧化膜103、硬質遮罩層104、抗反射膜(BARC)105、光阻膜106之後,於光阻膜106形成特定圖案者。首先,以光阻膜106為遮罩蝕刻硬質遮罩層104,之後,進行蝕刻對象之氧化膜103之蝕刻。In the semiconductor wafer W as the object to be processed, the resist film 102, the oxide film 103 to be etched, the hard mask layer 104, and the anti-reflection film (BARC) are sequentially formed on the ruthenium substrate 101 as shown in FIG. After the photoresist film 106 is formed, a specific pattern is formed on the photoresist film 106. First, the hard mask layer 104 is etched by using the photoresist film 106 as a mask, and then the etching of the oxide film 103 to be etched is performed.
作為本實施形態之蝕刻對象之氧化膜103,可使用例如以TEOS為原料而成膜者,或玻璃膜(BPSG或PSG)等。氧化膜103之厚度可適當設定,作為DRAM之電容器使用時約為1.5~3.0 μm。As the oxide film 103 to be etched in the present embodiment, for example, a film formed of TEOS or a glass film (BPSG or PSG) can be used. The thickness of the oxide film 103 can be appropriately set, and is about 1.5 to 3.0 μm when used as a capacitor for a DRAM.
作為硬質遮罩層104,可使用非晶質碳膜。非晶質碳膜,係和通常作為硬質遮罩層使用之SiN或SiC具有同等之抗電漿性,而且便宜。亦可,使用之TiN或SiN等通常使用之材料。硬質遮罩層104之厚度約為500~900nm。As the hard mask layer 104, an amorphous carbon film can be used. The amorphous carbon film is equivalent to SiN or SiC which is generally used as a hard mask layer, and is inexpensive, and is inexpensive. It is also possible to use a material such as TiN or SiN which is usually used. The thickness of the hard mask layer 104 is about 500 to 900 nm.
阻蝕膜102,係由SiCN等之SiC系材料構成,其厚度約為20~100nm。抗反射膜105可使用SiON或有機系,其厚度約為20~100nm。光阻膜106,典型為ArF阻劑,其厚度約為100~400nm。The resist film 102 is made of a SiC-based material such as SiCN, and has a thickness of about 20 to 100 nm. The antireflection film 105 may be made of SiON or organic, and has a thickness of about 20 to 100 nm. The photoresist film 106, typically an ArF resist, has a thickness of about 100 to 400 nm.
於蝕刻處理時,首先設定柵閥86為開放狀態,介由搬出入口85將具有上述構造之晶圓W搬入腔室10內,載置於承受器16上。之後,由處理氣體供給源66以特定流量將蝕刻用處理氣體供給至氣體擴散室40,介由氣體流通孔41及噴出孔37供給至腔室10內之同時,藉由排氣裝置84進行腔室10內之排氣,使其中之壓力設為例如20~30Pa範圍內之設定值。承受器16溫度設為約20~50℃。At the time of the etching process, first, the gate valve 86 is set to be in an open state, and the wafer W having the above-described structure is carried into the chamber 10 via the carry-out port 85, and placed on the susceptor 16. Thereafter, the processing gas supply source 66 supplies the etching processing gas to the gas diffusion chamber 40 at a specific flow rate, and is supplied into the chamber 10 through the gas circulation hole 41 and the discharge hole 37, and the chamber is exhausted by the exhaust device 84. The exhaust gas in the chamber 10 is set to a set value in the range of, for example, 20 to 30 Pa. The temperature of the susceptor 16 is set to be about 20 to 50 °C.
氧化膜103之蝕刻用處理氣體,係使用含有Cx Fy (其中x為3以下之整數,y為8以下之整數)、C4 F8 、稀有氣體、O2 之處理氣體,亦可含有其他氣體,但較好是使用僅由Cx Fy 、C4 F8 、稀有氣體、O2 之4種構成者。C4 F8 發揮使遮罩形狀成為垂直之功能,為獲得良好蝕刻形狀之重要氣體。但是僅將C4 F8 以可獲得充分之蝕刻速率的流量供給時,於區間口會產生沈積物,於後續蝕刻將容易產生弓形度等之形狀不良。於此,藉由Cx Fy 、其中x為3以下之整數,y為8以下之整數之較C4 F8 少相當於1分子之C量者之使用可減少此種沈積物。欲有效減少開口之沈積物時,較好是另外提升下部電極之承受器16之溫度至約50℃。The processing gas for etching the oxide film 103 is a processing gas containing C x F y (where x is an integer of 3 or less, y is an integer of 8 or less), C 4 F 8 , a rare gas, or O 2 , and may contain Other gases are preferably composed of only four types of C x F y , C 4 F 8 , rare gases, and O 2 . C 4 F 8 functions to make the shape of the mask vertical, and is an important gas for obtaining a good etching shape. However, when only C 4 F 8 is supplied at a flow rate at which a sufficient etching rate can be obtained, deposits are generated at the intervals, and subsequent etching causes a shape defect such as bowing degree. Here, the use of C x F y , wherein x is an integer of 3 or less, and y is an integer of 8 or less, which is less than C 4 F 8 and equivalent to 1 molecule of C, can reduce such deposits. In order to effectively reduce the deposit of the opening, it is preferred to additionally raise the temperature of the susceptor 16 of the lower electrode to about 50 °C.
Cx Fy 可使用C3 F8 或CF4 。其中較好是C3 F8 。C3 F8 具有提升蝕刻速率之作用。使用C3 F8 時,其流量較好是C4 F8 之流量以上。如此則,可有效消除開口之沈積物。更好是C3 F8 之流量:C4 F8 之流量為約1:1~1.5:1。具體之流量較好是C3 F8 之流量為20~60mL/min(換算為標準狀態之流量(sccm)),C4 F8 之流量為20~40mL/min(sccm)。C 3 F 8 or CF 4 can be used for C x F y . Of these, C 3 F 8 is preferred. C 3 F 8 has the effect of increasing the etch rate. When C 3 F 8 is used, the flow rate is preferably more than the flow rate of C 4 F 8 . In this way, the deposit of the opening can be effectively eliminated. More preferably, the flow rate of C 3 F 8 : the flow rate of C 4 F 8 is about 1:1 to 1.5:1. The specific flow rate is preferably a flow rate of C 3 F 8 of 20 to 60 mL/min (converted to a standard flow rate (sccm)), and a flow rate of C 4 F 8 of 20 to 40 mL/min (sccm).
O2 氣體之添加,係為確保蝕刻通孔之穿洞性,獲取蝕刻通孔之較寬之底部CD(Critical Dimention),以及處理氣體之平衡而添加者,較好是以流量比為處理氣體全體之2.5~3.5%添加。具體之流量較好是20~30mL/min(sccm)。The addition of O 2 gas is to ensure the hole penetration of the etched through hole, to obtain a wide bottom CD (Critical Dimention) of the etched through hole, and to add the balance of the processing gas, preferably by using a flow rate ratio as the processing gas. 2.5~3.5% of the total is added. The specific flow rate is preferably 20 to 30 mL/min (sccm).
稀有氣體,係為確保蝕刻通孔之穿洞性,而且稀釋CF系氣體獲取處理氣體之平衡,控制沈積物或F而添加者,較好是以流量比為處理氣體全體之85~90%添加。具體之流量較好是600~900mL/min(sccm)。但是,稀有氣體之流量依硬質遮罩層104之材料而部而不同,硬質遮罩層104為非晶質碳膜時較好是800mL/min(sccm)以上。而使用Poly Mask(多晶矽遮罩)材料時較好是設為300mL/min(sccm)以下。The rare gas is to ensure the penetration of the through hole, and to dilute the CF system gas to obtain the balance of the processing gas, and to control the deposit or F to be added, preferably the flow ratio is 85 to 90% of the total processing gas. . The specific flow rate is preferably 600 to 900 mL/min (sccm). However, the flow rate of the rare gas varies depending on the material of the hard mask layer 104, and when the hard mask layer 104 is an amorphous carbon film, it is preferably 800 mL/min or more. When a Poly Mask (polysilicon mask) material is used, it is preferably set to 300 mL/min (sccm) or less.
稀有氣體可使用Ar及Xe,特別是藉由稀有氣體之使用Xe,可提升作為C之載體之功能,可提升蝕刻之直信號線性,可構成良好之硬質遮罩層104之蝕刻形狀及氧化膜103之蝕刻形狀。The rare gas can use Ar and Xe, especially the Xe used by the rare gas, which can enhance the function as the carrier of C, can improve the linearity of the straight signal of the etching, and can form the etching shape and oxide film of the good hard mask layer 104. 103 etching shape.
在先於氧化膜103被進行之硬質遮罩層104之蝕刻中,係於通常條件下進行蝕刻。例如硬質遮罩層104為非晶質碳膜時可為C4 F6 +稀有氣體(Ar)+O2 之例。In the etching of the hard mask layer 104 before the oxide film 103 is performed, etching is performed under normal conditions. For example, when the hard mask layer 104 is an amorphous carbon film, it may be an example of C 4 F 6 + rare gas (Ar) + O 2 .
如上述說明,於腔室10內導入蝕刻用處理氣體狀態下,由第1高頻電源48將特定功率之電漿產生用高頻電力施加於上部電極34之同時,由第2高頻電源90將特定功率之離子引入用高頻施加於下部電極之承受器16。之後,由可變直流電源50將特定之直流電壓施加於上部電極34。再由靜電夾頭18用之直流電源22將直流電壓施加於靜電夾頭18之電極20,使晶圓W固定於承受器16。As described above, in the state where the etching processing gas is introduced into the chamber 10, the high-frequency power for generating plasma of a specific power is applied to the upper electrode 34 by the first high-frequency power source 48, and the second high-frequency power source 90 is provided. The ion of a specific power is introduced into the susceptor 16 of the lower electrode with a high frequency. Thereafter, a specific DC voltage is applied to the upper electrode 34 by the variable DC power source 50. Further, a DC voltage is applied from the DC power source 22 for the electrostatic chuck 18 to the electrode 20 of the electrostatic chuck 18 to fix the wafer W to the susceptor 16.
由上部電極34之電極板36上形成之氣體噴出孔37噴出之處理氣體,係於藉由高頻電力產生之上部電極34與下部電極之承受器16間之庫侖放電中被電漿化,藉由該電漿產生之自由基或離子,首先,如圖4(a)所示,以光阻膜106為遮罩使硬質遮罩層104被蝕刻,阻劑圖案被轉印,之後,如圖4(b)所示,以硬質遮罩層104為遮罩使氧化膜103被蝕刻而形成通孔107。The processing gas ejected from the gas ejection hole 37 formed on the electrode plate 36 of the upper electrode 34 is plasma-charged in a coulomb discharge between the upper electrode 34 and the lower electrode receiver 16 by high-frequency power generation. The radical or ion generated by the plasma, first, as shown in FIG. 4(a), the hard mask layer 104 is etched by using the photoresist film 106 as a mask, and the resist pattern is transferred, and then, as shown in FIG. As shown in FIG. 4(b), the oxide film 103 is etched by the hard mask layer 104 as a mask to form the via hole 107.
於上部電極34被供給高頻帶域(例如10MHz以上)之高頻電力,可使電漿構成為良好狀態之高密度化,於更低壓條件下亦能形成高密度電漿。When the upper electrode 34 is supplied with high-frequency power in a high-frequency band (for example, 10 MHz or more), the plasma can be made into a high-density state in a good state, and a high-density plasma can be formed under a lower-pressure condition.
但是僅施加上述高頻電力,使用上述處理氣體蝕刻氧化膜時,雖可確保蝕刻之形狀性,但對於硬質遮罩層104之蝕刻選擇比低,如圖5所示,於氧化膜103之蝕刻結束前硬質遮罩層104會消失。However, when only the high-frequency power is applied and the oxide film is etched using the processing gas, the shape of the etching can be ensured, but the etching selectivity of the hard mask layer 104 is low, as shown in FIG. 5, the etching of the oxide film 103 is performed. The hard mask layer 104 will disappear before the end.
因此,本實施形態中,如上述形成電漿時,由可變直流電源50對上部電極34施加特定極性及大小之直流電壓。藉由調整此時施加之直流電壓,可以設定對硬質遮罩層104之蝕刻選擇比成為良好狀態,如圖6所示,可於硬質遮罩層104殘存狀態下以良好形狀性蝕刻氧化膜103,此時之直流電壓較好是800~1200V。Therefore, in the present embodiment, when the plasma is formed as described above, the variable DC power supply 50 applies a DC voltage of a specific polarity and magnitude to the upper electrode 34. By adjusting the DC voltage applied at this time, it is possible to set the etching selectivity ratio to the hard mask layer 104 to be in a good state. As shown in FIG. 6, the oxide film 103 can be etched in a good shape in the remaining state of the hard mask layer 104. At this time, the DC voltage is preferably 800 to 1200V.
以下更具體說明。More specific description below.
於上部電極34,藉由習知蝕刻製程、特別是對上部電極34之高頻電力小的蝕刻製程而附著聚合物。進行蝕刻處理時,於上部電極34施加適當之直流電壓,則如圖7所示,可加深上部電極34之自偏壓Vdc,亦即可加大上部電極34表面之Vdc之絕對值。因此附著於上部電極34之聚合物被施加之直流電壓濺鍍供給至半導體晶圓W而附著於硬質遮罩層104之上。如此則,硬質遮罩層104便為難以被蝕刻,可以高選擇比進行氧化膜103之蝕刻。The upper electrode 34 is adhered to the polymer by a conventional etching process, particularly an etching process in which the high frequency power of the upper electrode 34 is small. When an etching process is performed, an appropriate DC voltage is applied to the upper electrode 34, and as shown in FIG. 7, the self-bias voltage Vdc of the upper electrode 34 can be deepened, and the absolute value of Vdc on the surface of the upper electrode 34 can be increased. Therefore, the polymer attached to the upper electrode 34 is supplied to the semiconductor wafer W by DC voltage sputtering applied thereto and adhered to the hard mask layer 104. As a result, the hard mask layer 104 is difficult to be etched, and the etching of the oxide film 103 can be performed at a high selectivity.
又,進行氧化膜103之蝕刻時,如上述說明,於上部電極34施加直流電壓時,電漿形成時上部電極34附近產生之電子被往處理空間之垂直方向加速,藉由適當控制此時之直流電壓等,可使電子到達孔(via)之內部,可抑制屏蔽(shading)效應,可使通孔形狀成為良好。When the etching of the oxide film 103 is performed, as described above, when a DC voltage is applied to the upper electrode 34, electrons generated in the vicinity of the upper electrode 34 during plasma formation are accelerated in the vertical direction of the processing space, and are appropriately controlled at this time. The DC voltage or the like allows the electrons to reach the inside of the via, suppressing the shading effect, and making the shape of the via hole good.
又,形成電漿時,於上部電極34施加直流電壓時,雖可提升電漿擴散用之比較中心部之電漿密度,但腔室10內之壓力較高、且使用CF系氣體之負性氣體作為處理氣體時,腔室10內之中心部之電漿密度有變低之傾向,藉由施加直流電壓,藉由提升中心部之電漿密度,可獲得均勻之電漿密度。Further, when a plasma is formed, when a DC voltage is applied to the upper electrode 34, the plasma density of the center portion for plasma diffusion can be increased, but the pressure in the chamber 10 is high, and the negative polarity of the CF-based gas is used. When the gas is used as the processing gas, the plasma density at the central portion in the chamber 10 tends to be low, and by applying a direct current voltage, a uniform plasma density can be obtained by raising the plasma density of the central portion.
又,藉由直流電壓之施加,選擇更富有沈積物之條件,不使用硬質遮罩層僅以光阻膜雖可確保蝕刻選擇比,但此情況下會有沈積物附著於區間口而產生弓形度或前端變細等不良。因此,必須使用硬質遮罩層104。Moreover, the condition of richer deposits is selected by the application of a DC voltage, and the etching selectivity can be ensured only by the photoresist film without using a hard mask layer. However, in this case, deposits may adhere to the section opening to form a bow shape. Poor degree or thinning of the front end. Therefore, a hard mask layer 104 must be used.
以下說明實際確認本發明電漿蝕刻方法之效果的實驗結果。The experimental results of actually confirming the effects of the plasma etching method of the present invention will be described below.
於矽基板上形成厚度50nm之SiN膜作為阻蝕膜102,於其上形成厚度1500nm之BPSG膜(下層)與TEOS膜(上層)之積層2層膜作為蝕刻對象之氧化膜103,於其上形成厚度500nm之非晶質碳膜作為硬質遮罩層104,於其上形成厚度60nm之SiON膜作為抗反射膜(BARC)105,再於其上形成厚度200nm之ArF阻劑作為光阻膜106,製作具有圖3構造之樣本,藉由如圖1所示裝置蝕刻硬質遮罩層104之後,以光阻膜106之殘存部份及硬質遮罩層104作為蝕刻遮罩,於各種條件下進行蝕刻對象之氧化膜103之蝕刻。於此,進行孔徑為90nm之圓形通孔之蝕刻。氧化物之蝕刻時,設定腔室內壓力為2.7Pa,上部高頻功率為1200W,下部高頻功率為3800W,直流電壓為-1000V,溫度為上部電極:95℃,下部電極:10℃,處理氣體使用C3 F8 、C4 F8 、Ar、O2 ,變化彼等之流量而進行蝕刻。An SiN film having a thickness of 50 nm is formed on the germanium substrate as the resist film 102, and a two-layer film of a BPSG film (lower layer) having a thickness of 1500 nm and a TEOS film (upper layer) is formed thereon as an oxide film 103 to be etched. An amorphous carbon film having a thickness of 500 nm was formed as the hard mask layer 104, and a SiON film having a thickness of 60 nm was formed thereon as an anti-reflection film (BARC) 105, and an ArF resist having a thickness of 200 nm was formed thereon as a photoresist film 106. A sample having the structure of FIG. 3 is fabricated, and after the hard mask layer 104 is etched by the device as shown in FIG. 1, the remaining portion of the photoresist film 106 and the hard mask layer 104 are used as an etch mask, under various conditions. Etching of the oxide film 103 of the etching target. Here, etching of a circular via having a hole diameter of 90 nm was performed. When the oxide is etched, the chamber pressure is set to 2.7 Pa, the upper high frequency power is 1200 W, the lower high frequency power is 3800 W, the DC voltage is -1000 V, the temperature is the upper electrode: 95 ° C, the lower electrode: 10 ° C, the processing gas Etching is performed using C 3 F 8 , C 4 F 8 , Ar, O 2 , and varying the flow rates thereof.
首先,固定Ar之流量為800mL/min(sccm)、O2 之流量為250mL/min(sccm),變化C4 F8 /C3 F8 而進行蝕刻。此時之蝕刻形狀如圖8所示,圖8A所示係設定為C4 F8 :35mL/min(sccm)及C3 F8 :30mL/min(sccm),圖8B所示係設定為C4 F8 :30mL/min(sccm)及C3 F8 :35mL/min(sccm),圖8C所示係設定為C4 F8 :25mL/min(sccm)及C3 F8 :40mL/min(sccm),圖8D所示係設定為C4 F8 :20mL/min(sccm)及C3 F8 :45mL/min(sccm)。如該圖所示,C為開口之肩部部分之形狀最佳者。First, the flow rate of the fixed Ar was 800 mL/min (sccm), the flow rate of O 2 was 250 mL/min (sccm), and etching was performed by changing C 4 F 8 /C 3 F 8 . The etching shape at this time is as shown in Fig. 8, and is set to C 4 F 8 : 35 mL/min (sccm) and C 3 F 8 : 30 mL/min (sccm) as shown in Fig. 8B, and is set to C as shown in Fig. 8B. 4 F 8 : 30 mL/min (sccm) and C 3 F 8 : 35 mL/min (sccm), as shown in Fig. 8C, C 4 F 8 : 25 mL/min (sccm) and C 3 F 8 : 40 mL/min (sccm), as shown in Fig. 8D, was set to C 4 F 8 : 20 mL/min (sccm) and C 3 F 8 : 45 mL/min (sccm). As shown in the figure, C is the shape of the shoulder portion of the opening which is the best.
之後,將C4 F8 /C3 F8 固定為上述C之組成,變化Ar與O2 之流量,其他條件和上述實驗同樣而進行蝕刻。此時之蝕刻形狀如圖9所示,圖9E所示係設定為Ar:500mL/min(sccm)及O2 :34mL/min(sccm),圖9F所示係設定為Ar:700mL/min(sccm)及O2 :32mL/min(sccm),圖9G所示係設定為Ar:900mL/min(sccm)及O2 :30mL/min(sccm),圖9H所示係設定為Ar:1100mL/min(sccm)及O2 :28mL/min(sccm)。其中,G為開口之肩部部分有改善,形狀最佳者。另外,變化氣體比成為中央較多而進行製程調整。結果,獲得如圖10所示未產生弓形度之良好形狀,此時之頂部CD、未產生弓形度之中間之CD、底部CD,於半導體晶圓中心分別為89nm、89nm、74nm,中間分別為91nm、93nm、75 nm,邊緣分別為85nm、87nm、73 nm之良好值。Thereafter, C 4 F 8 /C 3 F 8 was fixed to the composition of C described above, and the flow rates of Ar and O 2 were changed, and other conditions were etched in the same manner as in the above experiment. The etching shape at this time is as shown in Fig. 9, and is set to Ar: 500 mL/min (sccm) and O 2 : 34 mL/min (sccm) as shown in Fig. 9E, and is set to Ar: 700 mL/min as shown in Fig. 9F ( Sccm) and O 2 : 32 mL/min (sccm), as shown in Fig. 9G, Ar: 900 mL/min (sccm) and O 2 : 30 mL/min (sccm), and Fig. 9H is set to Ar: 1100 mL/ Min (sccm) and O 2 : 28 mL/min (sccm). Among them, G is an improvement in the shoulder portion of the opening, and the shape is the best. In addition, the process change is performed by changing the gas ratio to a larger number of centers. As a result, a good shape in which no bowing degree is generated as shown in FIG. 10 is obtained. At this time, the top CD, the CD in the middle of the bowlessness, and the bottom CD are 89 nm, 89 nm, and 74 nm in the center of the semiconductor wafer, respectively. 91 nm, 93 nm, and 75 nm, and the edges are good values of 85 nm, 87 nm, and 73 nm, respectively.
由上述可確認C3 F8 較多、Ar較多之特定條件下蝕刻之形狀性成為良好。From the above, it was confirmed that the shape of etching under a specific condition in which C 3 F 8 is large and Ar is large is good.
製作和實驗1同樣構造之樣本,藉由如圖1所示裝置蝕刻硬質遮罩層104之後,以光阻膜106之殘存部份及硬質遮罩層104作為蝕刻遮罩,進行氧化膜103之蝕刻。於此,設定壓力為2.7Pa,溫度為上部電極:95℃,下部電極:10℃之固定條件,於條件I設定:上部高頻功率為1200W,下部高頻功率為3800W,直流電壓為-1000V,C4 F8 :40mL/min(sccm),C3 F8 :25mL/min(sccm),Ar:900mL/min(sccm)、O2 :30mL/min(sccm),於條件J設定:上部高頻功率為1200W,下部高頻功率為3800W,直流電壓為-1000V,C4 F8 :25mL/min(sccm),C3 F8 :40mL/min(sccm),Ar:1000mL/min(sccm)、O2 :28mL/min(sccm),於條件K設定:上部高頻功率為1500W,下部高頻功率為4500W,直流電壓為-1100V,C4 F8 :25mL/min(sccm),C3 F8 :40mL/min(sccm),Ar:1000mL/min(sccm)、O2 :25mL/min(sccm),而進行蝕刻。其結果如圖11所示,如條件I→條件J所示,相對於C4 F8 ,隨C3 F8 之量變多,形狀變為良好,如條件J→條件K所示,藉由上升上部高頻功率及下部高頻功率,上升直流電壓,減少O2 ,則CD更加收縮,可獲得更良好之蝕刻形狀。A sample having the same structure as that of Experiment 1 was fabricated, and after the hard mask layer 104 was etched by the apparatus shown in FIG. 1, the remaining portion of the photoresist film 106 and the hard mask layer 104 were used as an etch mask to perform the oxide film 103. Etching. Here, the set pressure is 2.7 Pa, the temperature is the upper electrode: 95 ° C, and the lower electrode: 10 ° C is fixed. The condition I is set: the upper high frequency power is 1200 W, the lower high frequency power is 3800 W, and the direct current voltage is -1000 V. , C 4 F 8 : 40 mL/min (sccm), C 3 F 8 : 25 mL/min (sccm), Ar: 900 mL/min (sccm), O 2 : 30 mL/min (sccm), set under Condition J: Upper The high frequency power is 1200W, the lower high frequency power is 3800W, the DC voltage is -1000V, C 4 F 8 :25mL/min (sccm), C 3 F 8 :40mL/min (sccm), Ar: 1000mL/min (sccm ), O 2 : 28mL/min (sccm), set under condition K: upper high frequency power is 1500W, lower high frequency power is 4500W, DC voltage is -1100V, C 4 F 8 : 25mL/min (sccm), C 3 F 8 : 40 mL/min (sccm), Ar: 1000 mL/min (sccm), O 2 : 25 mL/min (sccm), and etching was performed. The results are shown in Figure 11, as shown in the condition I → J conditions, with respect to the C 4 F 8, C 3 F 8 with the amount of more shape becomes good condition as the condition J → K shown by increased The upper high-frequency power and the lower high-frequency power increase the DC voltage and reduce O 2 , so that the CD shrinks more and a better etching shape can be obtained.
於矽基板101上形成厚度40nm之SiN膜作為阻蝕膜102,於其上形成厚度2.0 μm之PSG膜作為蝕刻對象之氧化膜103,於其上形成厚度400nm之非晶質碳膜作為硬質遮罩層104,於其上形成厚度60nm之SiON膜作為抗反射膜(BARC)105,再於其上形成厚度200nm之ArF阻劑作為光阻膜106,製作具有圖3構造之樣本,藉由如圖1所示裝置蝕刻硬質遮罩層104之後,以光阻膜106之殘存部份及硬質遮罩層104作為蝕刻遮罩,於各種條件下進行蝕刻對象之氧化膜103之蝕刻。於此,進行長徑為160nm、短徑為80nm之橢圓形、深寬比為25之通孔之蝕刻。氧化物之蝕刻時,設定腔室內壓力為3.3Pa,上部高頻功率為1000W,下部高頻功率為4500W,直流電壓為-500V,溫度為上部電極:95℃,下部電極:50℃,處理氣體使用C3 F8 、C4 F8 、Xe、O2 ,Xe之流量固定為400mL/min(sccm),變化其他。於條件L設定:C4 F8 :20mL/min(sccm),C3 F8 :20mL/min(sccm),O2 :12.5mL/min(sccm)(C3 F8 /C4 F8 =1),於條件M設定:C4 F8 :10mL/min(sccm),C3 F8 :30mL/min(sccm),O2 :10mL/min(sccm)(C3 F8 /C4 F8 =3),於條件N設定:C4 F8 :6.7mL/min(sccm),C3 F8 :33.3mL/min(sccm),O2 :7.5mL/min(sccm)(C3 F8 /C4 F8 =5),而進行蝕刻。其結果如圖12所示,如C3 F8 /C4 F8 由1至3所示,邊緣側之弓形度顯著改善,C3 F8 /C4 F8 =5時邊緣側之弓形度幾乎消失,但中心之區間口擴散變為顯著之傾向存在。又,藉由上升C3 F8 之比率可確認蝕刻選擇比降低。如上述說明,隨C3 F8 之比率上升,而呈現弓形度→無弓形度→區間口擴散之變化。考慮中心及邊緣之形狀差、選擇比時,可以確認C3 F8 /C4 F8 =3為最適當值。但是弓形度被改善之C3 F8 /C4 F8 比係隨硬質遮罩層厚度、硬度、氧化膜硬度、通孔之短軸/長軸比而呈現不同。A SiN film having a thickness of 40 nm is formed as a resist film 102 on the germanium substrate 101, and a PSG film having a thickness of 2.0 μm is formed thereon as an oxide film 103 to be etched, and an amorphous carbon film having a thickness of 400 nm is formed thereon as a hard mask. The cap layer 104 is formed with a SiON film having a thickness of 60 nm as an anti-reflection film (BARC) 105, and an ArF resist having a thickness of 200 nm is formed thereon as a photoresist film 106, and a sample having the structure of FIG. 3 is produced by, for example, After the hard mask layer 104 is etched by the device shown in FIG. 1, the remaining portion of the photoresist film 106 and the hard mask layer 104 are used as etching masks, and the etching of the oxide film 103 to be etched is performed under various conditions. Here, etching of an elliptical shape having a long diameter of 160 nm and a short diameter of 80 nm and a via having an aspect ratio of 25 was performed. When the oxide is etched, the chamber pressure is set to 3.3 Pa, the upper high frequency power is 1000 W, the lower high frequency power is 4500 W, the DC voltage is -500 V, the temperature is the upper electrode: 95 ° C, the lower electrode: 50 ° C, the processing gas The flow rate of C 3 F 8 , C 4 F 8 , Xe, O 2 , and Xe was fixed to 400 mL/min (sccm), and the others were changed. Set under condition L: C 4 F 8 : 20 mL/min (sccm), C 3 F 8 : 20 mL/min (sccm), O 2 : 12.5 mL/min (sccm) (C 3 F 8 /C 4 F 8 = 1), set under condition M: C 4 F 8 : 10 mL/min (sccm), C 3 F 8 : 30 mL/min (sccm), O 2 : 10 mL/min (sccm) (C 3 F 8 /C 4 F 8 = 3), set under condition N: C 4 F 8 : 6.7 mL/min (sccm), C 3 F 8 : 33.3 mL/min (sccm), O 2 : 7.5 mL/min (sccm) (C 3 F 8 / C 4 F 8 = 5), and etching is performed. The result is shown in Fig. 12. As C 3 F 8 / C 4 F 8 is shown by 1 to 3, the bowing degree at the edge side is remarkably improved, and the bowing degree at the edge side when C 3 F 8 / C 4 F 8 = 5 It almost disappeared, but the spread of the mouth of the center became a significant tendency. Further, it can be confirmed that the etching selectivity ratio is lowered by increasing the ratio of C 3 F 8 . As explained above, as the ratio of C 3 F 8 rises, there is a change in bowing degree → no bow angle → interval mouth diffusion. Considering the shape difference between the center and the edge and the selection ratio, it can be confirmed that C 3 F 8 /C 4 F 8 =3 is the most appropriate value. However, the C 3 F 8 /C 4 F 8 ratio which is improved in bowing degree differs depending on the thickness of the hard mask layer, the hardness, the hardness of the oxide film, and the short axis/long axis ratio of the through holes.
於此確認DC施加引起之蝕刻均勻性。Here, the etching uniformity caused by DC application was confirmed.
於矽基板101上形成厚度60nm之SiN膜作為阻蝕膜102,於其上形成厚度2000nm之BPSG膜作為蝕刻對象之氧化膜103,於其上形成厚度60nm之SiON膜作為抗反射膜(BARC)105,再於其上形成厚度650nm之ArF阻劑作為光阻膜106,製作具有由圖3除去硬質遮罩層104之構造之樣本,藉由如圖1所示裝置,以光阻膜106作為蝕刻遮罩,於各種條件下進行蝕刻對象之氧化膜103之蝕刻。處理氣體使用C4 F6 、CF4 、Ar、O2 ,設定:C4 F6 :40mL/min(sccm),CF4 :60mL/min(sccm),Ar:350mL/min(sccm),O2 :45mL/min(sccm),設定壓力為2.67Pa(20mTorr),變化上部高頻功率與直流電壓,計算蝕刻速率及選擇比。其結果如圖13所示,由該圖可知,上升直流電壓時中心之通孔蝕刻速率會上升,上升上部高頻功率時邊緣之通孔蝕刻速率會上升。由此可確認,藉由對上部電極施加之直流電壓或上部高頻功率可控制面內蝕刻速率。另外,中心/邊緣之蝕刻速率之逆轉亦容易進行。A SiN film having a thickness of 60 nm is formed as a resist film 102 on the germanium substrate 101, and a BPSG film having a thickness of 2000 nm is formed thereon as an oxide film 103 to be etched, and a SiON film having a thickness of 60 nm is formed thereon as an anti-reflection film (BARC). 105, further forming an ArF resist having a thickness of 650 nm as the photoresist film 106, and preparing a sample having a structure in which the hard mask layer 104 is removed from FIG. 3, and using the photoresist film 106 as a device as shown in FIG. The mask is etched, and etching of the oxide film 103 to be etched is performed under various conditions. The treatment gas used C 4 F 6 , CF 4 , Ar, O 2 , setting: C 4 F 6 : 40 mL/min (sccm), CF 4 : 60 mL/min (sccm), Ar: 350 mL/min (sccm), O 2 : 45 mL/min (sccm), the set pressure was 2.67 Pa (20 mTorr), the upper high frequency power and the direct current voltage were changed, and the etching rate and the selection ratio were calculated. As a result, as shown in FIG. 13, it can be seen from the figure that the through-hole etching rate of the center rises when the DC voltage is raised, and the via etching rate of the edge increases when the upper high-frequency power is raised. From this, it was confirmed that the in-plane etching rate can be controlled by the direct current voltage applied to the upper electrode or the upper high frequency power. In addition, the reversal of the center/edge etch rate is also easy.
又,本發明不限定於上述實施形態,可做各種變更實施。例如上述實施形態中說明使用非晶質碳膜作為硬質遮罩層之例,但亦可使用其他習知使用之硬質遮罩材料。另外,氧化膜雖以TEOS為原料形成者或以BPSG、PSG為例說明,但不限定於此。Further, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, an amorphous carbon film is used as the hard mask layer, but other conventionally used hard mask materials may be used. Further, the oxide film is described by using TEOS as a raw material or BPSG or PSG as an example, but is not limited thereto.
又,本發明適用之裝置不限定於圖1所示者,可使用以下各種。例如可使用以上部電極2分割中心與周邊而分別可調整高頻施加功率之形態者。另外,如圖14所示,於下部電極之承受器16由第1高頻電源48’施加電漿產生用之例如40MHz之高頻電力之同時,由第2高頻電源90’施加離子引入用之例如2MHz之高頻電力,的下部2頻率施加形態之電漿蝕刻裝置亦可適用。如圖所示,於上部電極234連接可變直流電源166施加特定之直流電壓,亦可獲得和上述實施形態同樣效果。Further, the device to which the present invention is applied is not limited to those shown in Fig. 1, and the following various types can be used. For example, the upper electrode 2 can be used to divide the center and the periphery to adjust the form of the high-frequency applied power. Further, as shown in FIG. 14, the receiver 16 of the lower electrode is applied with a high-frequency power of, for example, 40 MHz for plasma generation by the first high-frequency power source 48', and ion introduction is applied by the second high-frequency power source 90'. For example, a plasma etching apparatus of a lower 2 frequency application type of high frequency power of 2 MHz may be applied. As shown in the figure, a specific DC voltage is applied to the upper electrode 234 via the variable DC power supply 166, and the same effects as in the above embodiment can be obtained.
另外,如圖15所示,取代於圖14中連接於下部電極之承受器16的第1高頻電源48’及第2高頻電源90’,改為連接高頻電源170,由高頻電源170施加兼作為電漿產生用與偏壓形成用之例如40MHz之高頻電力,的形態之電漿蝕刻裝置亦可適用。此情況下,亦和圖4同樣,藉由在上部電極234連接可變直流電源166施加特定之直流電壓,而可獲得和上述實施形態同樣效果。Further, as shown in FIG. 15, instead of the first high-frequency power source 48' and the second high-frequency power source 90' connected to the susceptor 16 of the lower electrode in FIG. 14, the high-frequency power source 170 is connected, and the high-frequency power source is connected. A plasma etching apparatus in which a high-frequency power of, for example, 40 MHz for plasma generation and bias formation is applied is also applied. Also in this case, similarly to Fig. 4, by applying a specific DC voltage to the upper DC electrode 234 via the variable DC power supply 166, the same effects as in the above embodiment can be obtained.
依據本發明,對依序被形成有蝕刻對象之氧化膜、硬質遮罩層、圖案化光阻的基板,使用含有Cx Fy (其中x為3以下之整數,y為8以下之整數)、C4 F8 、稀有氣體、O2 之處理氣體進行電漿蝕刻,因此即使窄區間口、高深寬比之通孔,亦可以具實用性蝕刻速率、且無弓形度(bowing)等之具有良好形狀性而進行蝕刻。又,此種氣體系,於通常製程無法獲得充分之蝕刻選擇比,於蝕刻結束前遮罩層有可能消失,但是本發明中,於上部電極或下部電極之任一施加電漿產生用高頻電力而產生電漿時,係於上部電極施加直流電壓,因此可由上部電極對硬質遮罩層供給聚合物,使硬質遮罩層之抗電漿性上升,可提升蝕刻選擇比,即使於上述氣體系,硬質遮罩層亦不會消失,可進行良好之蝕刻。According to the present invention, a substrate having an oxide film, a hard mask layer, and a patterned photoresist which are sequentially formed is used, and C x F y (where x is an integer of 3 or less, and y is an integer of 8 or less) is used. The processing gas of C 4 F 8 , rare gas and O 2 is plasma-etched. Therefore, even a narrow-port, high aspect ratio through-hole can have a practical etching rate and no bowing. Etching is performed with good shape. Moreover, in such a gas system, a sufficient etching selectivity cannot be obtained in a usual process, and the mask layer may disappear before the end of etching. However, in the present invention, a high frequency for plasma generation is applied to either the upper electrode or the lower electrode. When electricity is generated and plasma is generated, a DC voltage is applied to the upper electrode. Therefore, the polymer can be supplied to the hard mask layer by the upper electrode, so that the resistance of the hard mask layer is increased, and the etching selectivity can be improved even in the above gas. The hard mask layer will not disappear and good etching can be performed.
10...腔室(處理容器)10. . . Chamber (processing vessel)
16...下部電極之承受器16. . . Lower electrode receiver
34...上部電極34. . . Upper electrode
44...供電棒44. . . Power supply rod
46、88...匹配器46, 88. . . Matcher
48...第1高頻電源48. . . First high frequency power supply
50...可變直流電源50. . . Variable DC power supply
51...控制器51. . . Controller
52...ON/OFF開關52. . . ON/OFF switch
66...處理氣體供給源66. . . Process gas supply
84...排氣裝置84. . . Exhaust
90...第2高頻電源90. . . Second high frequency power supply
91...GND塊91. . . GND block
101...矽基板101. . .矽 substrate
102...阻蝕膜102. . . Corrosion film
103...氧化膜103. . . Oxide film
104...硬質遮罩層104. . . Hard mask layer
105...抗反射膜(BARC)105. . . Anti-reflective film (BARC)
106...光阻膜106. . . Photoresist film
W...半導體晶圓(被處理基板)W. . . Semiconductor wafer (processed substrate)
圖1為本發明之實施使用之電漿蝕刻裝置之一例之概略斷面圖。Fig. 1 is a schematic cross-sectional view showing an example of a plasma etching apparatus used in the practice of the present invention.
圖2為圖1之電漿蝕刻裝置之中,連接於第1高頻電源之匹配器構造圖。Fig. 2 is a structural view showing a matching device connected to a first high-frequency power source in the plasma etching apparatus of Fig. 1;
圖3為本發明之一實施形態之實施使用之半導體晶圓W之構造斷面圖。Fig. 3 is a cross-sectional view showing the structure of a semiconductor wafer W used in an embodiment of the present invention.
圖4為圖3之構造被蝕刻的狀態說明之模式圖。Fig. 4 is a schematic view showing a state in which the structure of Fig. 3 is etched.
圖5為氧化膜之蝕刻中途硬質遮罩層消失的狀態之模式圖。Fig. 5 is a schematic view showing a state in which the hard mask layer disappears in the middle of etching of the oxide film.
圖6為藉由本實施形態蝕刻氧化膜時的狀態之模式圖。Fig. 6 is a schematic view showing a state in which an oxide film is etched by this embodiment.
圖7為於圖1之電漿處理裝置,對上部電極施加與不施加直流電壓時之電漿狀態之比較圖。Fig. 7 is a view showing the comparison of the state of the plasma when the upper electrode is applied and the DC voltage is not applied to the plasma processing apparatus of Fig. 1.
圖8為實驗1之結果。Figure 8 shows the results of Experiment 1.
圖9為實驗1之結果。Figure 9 shows the results of Experiment 1.
圖10為實驗1之結果。Figure 10 shows the results of Experiment 1.
圖11為實驗2之結果。Figure 11 shows the results of Experiment 2.
圖12為實驗3之結果。Figure 12 shows the results of Experiment 3.
圖13為實驗4之結果。Figure 13 shows the results of Experiment 4.
圖14為本發明之實施適用之另一形態之電漿蝕刻裝置之例之概略圖。Fig. 14 is a schematic view showing an example of a plasma etching apparatus according to another embodiment of the present invention.
圖15為本發明之實施適用之另一形態之電漿蝕刻裝置之例之概略圖。Fig. 15 is a schematic view showing an example of a plasma etching apparatus according to another embodiment of the present invention.
10...腔室(處理容器)10. . . Chamber (processing vessel)
10a...圓筒狀接地導體10a. . . Cylindrical ground conductor
11...沈積物防止構件11. . . Sediment prevention member
12...絕緣板12. . . Insulation board
14...承受器支撐台14. . . Receptor support
16...下部電極之承受器16. . . Lower electrode receiver
18...靜電夾頭18. . . Electrostatic chuck
20...電極20. . . electrode
22...直流電源twenty two. . . DC power supply
24...聚磁環twenty four. . . Polymagnetic ring
26...內壁構件26. . . Inner wall member
28...冷媒室28. . . Refrigerant room
30a:30b...配管30a: 30b. . . Piping
32...氣體供給管32. . . Gas supply pipe
34...上部電極34. . . Upper electrode
36...電極板36. . . Electrode plate
37...噴出孔37. . . Spout hole
38...電極支撐體38. . . Electrode support
40...氣體擴散室40. . . Gas diffusion chamber
41...氣體流通孔41. . . Gas circulation hole
42...絕緣性遮蔽構件42. . . Insulating shielding member
44...供電棒44. . . Power supply rod
46、88...匹配器46, 88. . . Matcher
48...第1高頻電源48. . . First high frequency power supply
50...可變直流電源50. . . Variable DC power supply
51...控制器51. . . Controller
52...ON/OFF開關52. . . ON/OFF switch
62...氣體導入口62. . . Gas inlet
64...氣體供給管64. . . Gas supply pipe
66...處理氣體供給源66. . . Process gas supply
70...開關閥70. . . Switch valve
80...排氣口80. . . exhaust vent
82...排氣管82. . . exhaust pipe
83...排氣板83. . . Exhaust plate
84...排氣裝置84. . . Exhaust
86...柵閥86. . . Gate valve
90...第2高頻電源90. . . Second high frequency power supply
91...GND塊91. . . GND block
92...低通濾波器92. . . Low pass filter
94...高通濾波器94. . . High pass filter
95...控制部95. . . Control department
96...使用者介面96. . . user interface
97...記憶部97. . . Memory department
Claims (15)
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JP2006196927A JP2008028022A (en) | 2006-07-19 | 2006-07-19 | Plasma etching method and computer readable storage medium |
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KR (1) | KR100861260B1 (en) |
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TW (1) | TWI467650B (en) |
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JP5231038B2 (en) * | 2008-02-18 | 2013-07-10 | 東京エレクトロン株式会社 | Plasma processing apparatus, plasma processing method, and storage medium |
JP2009239012A (en) * | 2008-03-27 | 2009-10-15 | Tokyo Electron Ltd | Plasma processing device and method of plasma etching |
CN101764040B (en) * | 2008-12-23 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Control method for plasma etching |
JP5171683B2 (en) * | 2009-02-18 | 2013-03-27 | 東京エレクトロン株式会社 | Plasma processing method |
JP4855506B2 (en) * | 2009-09-15 | 2012-01-18 | 住友精密工業株式会社 | Plasma etching equipment |
WO2011066668A1 (en) * | 2009-12-02 | 2011-06-09 | C Sun Mfg. Ltd. | Method of etching features into substrate |
JP5640361B2 (en) * | 2009-12-03 | 2014-12-17 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
JP5606060B2 (en) * | 2009-12-24 | 2014-10-15 | 東京エレクトロン株式会社 | Etching method and etching processing apparatus |
CN101777493A (en) * | 2010-01-28 | 2010-07-14 | 上海宏力半导体制造有限公司 | Hard mask layer etching method |
JP5568340B2 (en) * | 2010-03-12 | 2014-08-06 | 東京エレクトロン株式会社 | Plasma etching method and plasma etching apparatus |
CN102270600B (en) * | 2010-06-04 | 2013-09-25 | 中芯国际集成电路制造(北京)有限公司 | Forming method of through hole |
US8420545B2 (en) * | 2011-05-23 | 2013-04-16 | Nanya Technology Corporation | Plasma etching method and plasma etching apparatus for preparing high-aspect-ratio structures |
JP6035117B2 (en) * | 2012-11-09 | 2016-11-30 | 東京エレクトロン株式会社 | Plasma etching method and plasma etching apparatus |
US8871108B2 (en) * | 2013-01-22 | 2014-10-28 | Tel Fsi, Inc. | Process for removing carbon material from substrates |
JP6356516B2 (en) * | 2014-07-22 | 2018-07-11 | 東芝メモリ株式会社 | Plasma processing apparatus and plasma processing method |
JP6329839B2 (en) | 2014-07-29 | 2018-05-23 | 東京エレクトロン株式会社 | Plasma processing apparatus and plasma processing method |
JP6498022B2 (en) * | 2015-04-22 | 2019-04-10 | 東京エレクトロン株式会社 | Etching method |
KR101913684B1 (en) * | 2016-10-21 | 2018-11-01 | 주식회사 볼트크리에이션 | Appratus for dry etching and method for controlling the same |
JP7203531B2 (en) * | 2018-08-08 | 2023-01-13 | 東京エレクトロン株式会社 | Plasma processing method and plasma processing apparatus |
TW202425048A (en) * | 2022-08-05 | 2024-06-16 | 日商東京威力科創股份有限公司 | Substrate processing system and substrate processing method |
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KR20080008226A (en) | 2008-01-23 |
CN101110361A (en) | 2008-01-23 |
JP2008028022A (en) | 2008-02-07 |
TW200814188A (en) | 2008-03-16 |
CN100541734C (en) | 2009-09-16 |
KR100861260B1 (en) | 2008-10-01 |
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