43469b Λ7 5l46twf.d〇c/008 B7 五、發明說明（f ) y 本發明是有關於一種防止晶片遭受電漿損傷（Plasma Damage)的裝置’且特別是有關於一種防止晶片於進行高 密度電漿化學氣相沉積（High Density Plasma chemical Vapor Deposition，HDP-CVD)期間遭受電漿損傷的裝置。 尺寸縮小是半導體兀件的製造趨勢，爲符合此製造 趨勢’許多更具小尺寸製程能力的製程技術不斷地被開 發出來，舉例而言，高密度電漿化學氣相沉積技術由於 具備良好的塡隙（Gap-Fill)能力’因此成了目前淺溝渠隔 離結構（Shallow Trench Isolation，STI)與金屬間介電層 (Inter-Metal Dielectrics ’ IMD)製作時，最主要的技術。 一般而言，高密度電漿化學氣相沉積技術主要是利 用化學氣相沉積與正離子物理轟擊蝕刻（P〇sitive Ion Physical Bombardment Etch)兩種機構，其中，正離子物 理轟擊蝕刻機構牽涉到高能量電漿對晶片的撞擊，因此 易對晶片造成損傷，導致天線效應（Antenna、Effect)的產 生。 第1圖係繪示完成部分多重金屬連線（Multilevel Interconnects)製程的半導體元件之結構剖面示意圖。 請參照第1圖’當半導體元件完成金屬導線l〇8a 與108b的製作時’金屬導線108a與i〇8b藉由接觸窗106 及金屬導線104’分別與基底100中之導電區i〇〇a及i〇〇b 形成電性連接，而閘極102則位於導電區i〇〇a及i〇〇b 之間。 接著’利用高密度電漿化學氣相沉積技術，以在金 3 (請先間讀背面之注意事項再填寫本黃) -裝 -----11 訂 --------0 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中囹國家標準（CNS)A4規格（210 X 297公釐） 434695 5146twf.d〇c/008 A7 B7 五、發明說明（π ) 屬導線108a與108b之間塡入金屬間介電層，若當此製 程進行時，發生電漿均勻度（Uniformity)不佳的現象，則 金屬導線l〇8a與108b將會因此接受到不同的正電荷數， 而導致金屬導線l〇8a與108b具有電位差。 然而，金屬導線l〇8a與108b係藉由接觸窗1〇6及 金屬導線104，分别與基底1〇〇中之導電區100a及100b 形成電性連接，因此金屬導線l〇8a與l〇8b所具有的電 位差，亦即代表位於閘極102兩側之導電區l〇〇a及100b 所具有的電位差，此電位差會對閘極102中之閘極介電 層102a有所影響，進而可能造成電漿誘導損傷（Plasma Induce Damage，PID)產生，而使閛極介電層102a的特 性發生嚴重退化（Degraded)。 因此本發明提供一種防止晶片遭受電漿損傷的裝 置，藉由將使用電漿設備形成介電層的初期之正離子濾 除或中和，以解決使用電漿設備形成介電層時，易發生 晶片遭電漿損傷的缺點。 本發明提出一種防止晶片遭受電漿損傷的裝置’適 用於在一晶片表面形成一介電層的過程中’牽渉到一電 漿產生的一沉積設備，包括一尺寸約略大於晶片大小的 篩網（Screen)，置於晶片的上方，並於形成介電層的過程 初期，被施以一負偏壓（Bias)，以濾除沉積設備之電漿的 正離子，或一電子流槍（Electron Flooding Gun)，置於晶 片的上方，並於形成介電層的過程初期被開啓’以中和 晶片的電性，使晶片表面先形成一無電漿離子損傷(Non_ 4 (請先閱讀背面之注意事項再填寫本頁) • · 11 1 I I I 1 訂 I — 11 1!—^ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（匚~5)六4規格（2】0>< 297公釐） 434695 Λ7 5l46twf.doc/0〇8 uj 五、發明說明（々）43469b Λ7 5l46twf.doc / 008 B7 V. Description of the invention (f) y The present invention relates to a device for preventing wafer damage from plasma damage, and in particular to a device for preventing wafers from being subjected to high-density electricity. A device that suffers from plasma damage during High Density Plasma chemical Vapor Deposition (HDP-CVD). Size reduction is the manufacturing trend of semiconductor components. In order to meet this manufacturing trend, many process technologies with more small-sized process capabilities have been continuously developed. For example, high-density plasma chemical vapor deposition technology Therefore, the Gap-Fill capability has become the most important technology in the production of Shallow Trench Isolation (STI) and Inter-Metal Dielectrics (IMD). Generally speaking, high-density plasma chemical vapor deposition technology mainly uses chemical vapor deposition and positive ion physical bombardment etching (Positive Ion Physical Bombardment Etch). Among them, the positive ion physical bombardment etching mechanism involves high The impact of the energy plasma on the wafer is easy to cause damage to the wafer, resulting in the generation of antenna effects (Antenna, Effect). FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device that has completed part of the Multilevel Interconnects process. Please refer to FIG. 1 'when the semiconductor element has completed the fabrication of the metal wires 108a and 108b', the metal wires 108a and 108b are connected to the conductive region i00a in the substrate 100 through the contact window 106 and the metal wire 104 ', respectively. And i00b form an electrical connection, and the gate electrode 102 is located between the conductive regions i00a and i00b. Then 'use high-density plasma chemical vapor deposition technology to gold 3 (please read the precautions on the back before filling in this yellow)-equipment ----- 11 order -------- 0 economy Printed by the Employees' Cooperatives of the Ministry of Intellectual Property Bureau, the paper size is in accordance with the China National Standard (CNS) A4 (210 X 297 mm) 434695 5146twf.d0c / 008 A7 B7 V. Description of the invention (π) The wires 108a and An intermetallic dielectric layer is inserted between 108b. If the uniformity of the plasma is poor when this process is performed, the metal wires 108a and 108b will receive different numbers of positive charges. As a result, the metal wires 108a and 108b have a potential difference. However, the metal wires 108a and 108b are electrically connected to the conductive areas 100a and 100b in the substrate 100 through the contact windows 106 and the metal wires 104, respectively. Therefore, the metal wires 108a and 108b The potential difference means the potential difference between the conductive regions 100a and 100b located on both sides of the gate 102. This potential difference will affect the gate dielectric layer 102a in the gate 102, which may cause Plasma Induce Damage (PID) occurs, and the characteristics of the dynode dielectric layer 102a are severely degraded. Therefore, the present invention provides a device for preventing a wafer from being damaged by a plasma. By filtering or neutralizing the positive ions in the initial stage of forming a dielectric layer using a plasma device, it is easy to occur when a dielectric layer is formed using a plasma device. The disadvantage that the wafer is damaged by the plasma. The invention proposes a device for preventing a wafer from being damaged by a plasma. The device is suitable for a deposition device that involves the generation of a plasma during the formation of a dielectric layer on a wafer surface. The device includes a screen with a size slightly larger than the size of the wafer. (Screen), which is placed above the wafer and is applied with a negative bias (Bias) at the beginning of the process of forming the dielectric layer to filter out positive ions from the plasma of the deposition equipment, or an electron flow gun (Electron Flooding Gun), placed on the top of the wafer, and turned on at the beginning of the process of forming the dielectric layer to neutralize the electrical properties of the wafer, so that the surface of the wafer first forms a plasma-free ion damage (Non_ 4 (Please read the note on the back first) Please fill in this page for matters) • · 11 1 III 1 Order I — 11 1! — ^ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives This paper is printed in accordance with Chinese National Standards (匚 ~ 5), 6 and 4 specifications (2) 0 > < 297 mm) 434695 Λ7 5l46twf.doc / 0〇8 uj 5. Description of the invention (々)
Plasma-Ion-Damage)之介電襯層（Liner)，再形成介電層。 其中晶片所正在進行的製程爲形成金屬間介電層的 製程或形成淺溝渠隔絕結構的製程，而沉積設備包括高 密度電漿化學氣相沉積設備、變壓耦式電漿（Transformer Coupled Plasma，TCP)化學氣相沉積設備與電感耦式電 槳（Inductively Coupled Plasma，ICP)化學氣相沉積設備。 本發明係在介電層形成過程牽涉到電漿產生的設備 中，裝置一施有負偏壓的篩網，或一可中和晶片電性的 電子流槍，於欲形成介電層的晶片上方，以在介電層形 成初期，防止帶有正電荷的離子撞擊到晶片表面，而可 形成一無電漿離子損傷之介電襯層，然後再形成介電層。 本發明所揭露之尺寸約略大於晶片尺寸之施有負偏 壓的篩網，會吸引正電荷之離子，只剩下電性爲中性的 粒子會到達晶片表面，因此即使發生電漿不均勻的現象， 天線效應不會產生。 本發明所揭露之電子流槍，會使因電漿而帶有正電 的晶片達到電性中和，因此晶片不會產生天線效應。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第1圖係繪示完成部分多重金屬連線的半導體元件 之結構剖面示意圖； 第2圖係繪示依據本發明較佳實施例之一種形成金 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注項再填寫本頁) ' ---I I I I 1 --I---I I I I ^ 經濟部智慧財產局員工消費合作杜印製 434695 A7 5i46twf.doc/008 Π7 經濟部智慧財產局具工消費合作社印製 五、發明說明（屮） 屬間介電層之結構剖面示意圖； 第3圖係繪示依據本發明較佳實施例之一種高密度 電漿化學氣相沉積設備之結構示意圖；以及 第4圖係繪示依據本發明較佳實施例之一種篩網結 構示意圖。 圖式之標記說明： 100、200 :基底 100a、100b :導電區 102 :閘極 102a :聞極介電層 104、108a、108b、202a、202b :金屬導線 106 :接觸窗 110、206 :介電層 204 :無電漿離子損傷之介電襯層 300 :晶片 302 :篩網 304 :電子流槍 306 :反應室覆蓋 308 :靜電晶片座 310 :渦輪式幫浦 312 :高電導反應室 314 :半球形感應線圈 富施例 第2圖係繪示依據本發明較佳實施例之一種形成金 6 (請先閱讀背面之;i意事項再填寫本頁) — — — — — — I— ^ « — I!— — — — — 本纸張尺度適用中國國家標準（CNS)A4規格（210x 297公餐） 經濟部智慧財產局員工消費合作社印製 .346 95 A7 514 6twf. doc/008 取 五、發明說明（ξ：) 屬間介電層之結構剖面示意圖。 請參照第2圖，一已形成金屬導線202a與202b的 基底2〇〇表面，形成有一無電漿離子損傷之介電襯層 204，與一介電層206。 其中，此無電漿離子損傷之介電襯層204與介電層 206譬如是利用高密度電漿化學氣相沉積技術所完成的。 第3圖係繪示依據本發明較佳實施例之一種高密度 電漿化學氣相沉積設備之結構示意圖。 請同時參照第2與3圖，此無電漿離子損傷之介電 襯層204的形成，譬如是在進行高密度電漿化學氣相沉 積的初期，在晶片300的上方放置一尺寸約略大於晶片 3 00大小之篩網302，而此篩網302被施以一負偏壓，其 中此篩網302的網目（Grid)大小譬如約略是3x3至10x10 平方公釐，如第4圖所示。 由於此篩網302被施以一負偏壓，因此在無電漿離 子損傷之介電襯層204的形成過程中，帶正電荷之離子 會被此篩網302所吸引，只剩下.電性爲中性的粒子 r (Radical)會到達晶片300表面。 如此，金屬導線202a與202b在進行高密度電漿化 學氣相沉積的初期，即使發生電漿不均勻的現象，金屬 導線202a與202b都將不會接受到帶有電性之離子的碰 撞，因此金屬導線202a與202b將不會帶有電荷，當然 不會具有電位差，天線效應因而不會產生。 然後，當無電漿離子損傷之介電襯層形成至一 7 (請先閱讀背面之注意事項再填寫本頁)Plasma-Ion-Damage), and then a dielectric layer is formed. The process that the wafer is undergoing is a process of forming an intermetallic dielectric layer or a process of forming a shallow trench isolation structure, and the deposition equipment includes a high-density plasma chemical vapor deposition equipment, a Transformer Coupled Plasma, TCP) chemical vapor deposition equipment and Inductively Coupled Plasma (ICP) chemical vapor deposition equipment. The invention relates to a device that involves plasma generation in the process of forming a dielectric layer. A negative bias screen or an electron flow gun capable of neutralizing the electrical properties of the wafer is installed on the wafer to form the dielectric layer. Above, in the initial stage of the formation of the dielectric layer, to prevent positively charged ions from hitting the wafer surface, a dielectric liner without plasma ion damage can be formed, and then a dielectric layer is formed. The negatively biased sieve with a size slightly larger than the size of the wafer disclosed by the present invention will attract positively charged ions, and only the particles that are electrically neutral will reach the surface of the wafer, so even if plasma unevenness occurs Phenomenon, the antenna effect does not occur. The electron flow gun disclosed in the present invention will electrically neutralize a chip that is positively charged due to the plasma, so the chip will not produce an antenna effect. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with the accompanying drawings, as follows: Brief description of the drawings: FIG. 1 is a drawing Schematic cross-sectional view of the structure of a semiconductor device with partial multi-metal wiring completed; Figure 2 shows a form of gold 5 according to a preferred embodiment of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ) (Please read the note on the back before filling out this page) '--- IIII 1 --I --- IIII ^ Consumer Consumption Cooperation by Intellectual Property Bureau of the Ministry of Economic Affairs 434695 A7 5i46twf.doc / 008 Π7 Ministry of Economic Affairs Wisdom Printed by the Property Bureau, Industrial and Consumer Cooperatives 5. Description of the invention (屮) A schematic cross-sectional view of the structure of the interlayer dielectric layer; FIG. 3 is a diagram showing a high-density plasma chemical vapor deposition device according to a preferred embodiment of the present invention. A schematic diagram of the structure; and FIG. 4 is a schematic diagram of a screen structure according to a preferred embodiment of the present invention. Explanation of the marks of the drawings: 100, 200: substrates 100a, 100b: conductive areas 102: gate electrodes 102a: smell dielectric layers 104, 108a, 108b, 202a, 202b: metal wires 106: contact windows 110, 206: dielectric Layer 204: dielectric liner without plasma ion damage 300: wafer 302: screen 304: electron flow gun 306: reaction chamber cover 308: electrostatic wafer holder 310: turbine pump 312: high conductivity reaction chamber 314: hemispherical The second embodiment of the induction coil is shown in FIG. 2 as a form of gold 6 according to a preferred embodiment of the present invention (please read the back of the article; i will fill in this page) — — — — — — I — ^ «— I ! — — — — — This paper size applies to China National Standard (CNS) A4 (210x 297 meals) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 346 95 A7 514 6twf. Doc / 008 (Ξ :) A schematic structural cross-sectional view of an intergeneric dielectric layer. Referring to FIG. 2, a surface of the substrate 2000 on which the metal wires 202a and 202b have been formed is formed with a dielectric liner 204 without a plasma ion damage, and a dielectric layer 206. Among them, the dielectric liner 204 and the dielectric layer 206 without plasma ion damage are completed by using a high-density plasma chemical vapor deposition technique, for example. FIG. 3 is a schematic structural diagram of a high-density plasma chemical vapor deposition device according to a preferred embodiment of the present invention. Please refer to FIGS. 2 and 3 at the same time. The formation of the dielectric liner 204 without plasma ion damage, for example, in the initial stage of high-density plasma chemical vapor deposition, a size slightly larger than the wafer 3 is placed on the wafer 300 00 size screen 302, and a negative bias is applied to the screen 302. The size of the grid of the screen 302 is, for example, approximately 3x3 to 10x10 mm 2, as shown in FIG. 4. Since this screen 302 is applied with a negative bias, during the formation of the dielectric liner 204 without plasma ion damage, positively charged ions will be attracted to this screen 302, leaving only electrical properties. The neutral particles r (Radical) reach the surface of the wafer 300. In this way, during the initial stage of high-density plasma chemical vapor deposition of metal wires 202a and 202b, even if plasma unevenness occurs, metal wires 202a and 202b will not receive collisions with charged ions, so The metal wires 202a and 202b will not be charged, and of course there will be no potential difference, so the antenna effect will not be generated. Then, when the dielectric liner without plasma ion damage is formed to a 7 (Please read the precautions on the back before filling this page)
.裝--------訂----------Y 本紙張尺度適用中國國家標準（CNS)A.l規格（21〇χ 297公釐） 經濟部智慧財產局員工消費合作社印製 4346 Si Δ7 5146twf.doc/008 βγ 五、發明說明（心） 特定厚度之後，再將施於篩網3〇2之負偏壓去除，以恢 復一般高密度電漿化學氣相沉積製程，而形成介電層 206。 由於金屬導線202a與2〇2b已裨無電漿離子損傷之 介電襯層204所覆蓋，因此即使在形两介電層206的過 程中，帶有正電荷的離子會到達晶片300.羞面，此些帶 有正電荷的離子仍不會碰撞到被無電漿離子損傷之介電 襯層204所覆蓋的金屬導線202a與202b，因此一直到金 屬間介電層完成，金屬導線2_02a與202b都不會帶有電 荷，因而不會造成天線效應的產生。 請再同時參照第2與3圖，此無電漿離子損傷之介 電襯層204的形成，除了在進行高密度電漿化學氣相沉 積的初期，於晶片300的上方放置一尺寸約略大於晶片 300大小之施有負偏壓的篩網302外，亦可使用以廣泛 使用於離子佈植機（Ion Implanter)中，用以中和晶片電性 的電子流槍。 在無電漿離子損傷之介電襯層204形成的同時，開 啓電子流槍304，以中和晶片300上可能累積的正離子， 如此，金屬導線202a與202b將不會帶有電荷’天線效 應因而不會產生^ 當無電漿離子損傷之介電襯層2〇4形成至一特定厚 度之後，將電子流槍304關閉，以恢復一般高密度電漿 化學氣相沉積製程，接著再形成介電層206。 由於金屬導線202a與202b已被無電漿離子損傷之 8 (請先閱讀背面之注意事項再填寫本頁) i--------ITi-------竣 本紙張尺度適用中國國家標準（CNS)Al規格do X 297公釐〉 經濟部智慧財產局員工消費合作社印製 434695 5146twf.doc/00S 五、發明說明（"]) 介電襯層2〇4所覆蓋，因此即使在形成介電層206的過 程中，帶有正電荷的離子會到達晶片300表面，此些帶 有正電荷的離子仍不會碰撞到被無電漿離子損傷之介電 襯層204所覆蓋的金屬導線202a與202b，因此一直到金 屬間介電層完成，金屬導線202a與202b都不會帶有電 荷，因而不會造成天線效應的產生。 本實施例所揭露的第3圖，其他各構件之名稱分別 爲反應室覆蓋（Dome)306、靜電晶片座（Electro-Static Chuck，ESC)308、渦輪式幫浦（Turbo Pump)310、高電導 ' 反應室（High Conductance Chamber)；312與半球形感應線 圈（Hemispherical Induction Coil)314，由於此些構件並非 本發明之特徵，因此在此不贅述。. 本實施例所揭露的防止晶片遭受電漿損傷的裝置， 係針對形成金屬間介電層的製程，除此之外，本發明亦 可應用於形成淺溝渠隔絕結構的製程。 本實施例所揭露的防止晶片遭受電漿損傷的裝置， 係針對高密度電漿化學氣相沉積設備，除此之外，其他 在薄膜形成過程中牽涉到電漿產生的設備，譬如變壓耦 式電漿化學氣相沉積設備，或電感耦式電漿化學氣相沉 積設備，亦適用於本發明。 本發明係在介電層形成過程牽涉到電漿產生的設備 中，裝置一施有負偏壓的篩網，或一可中和晶片電性的 電子流槍，於欲形成介電層的晶片上方，以在介電層形 成初期，防止帶有正電荷的離子撞擊到晶片表面，而可 9 (請先閱讀背面之注意事項再填寫本頁) ---- 訂----------" 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4346 95 Λ7 5146twf.doc/0〇8 r ~ " 五、發明說明（兮） 形成一無電漿離子損傷之介電襯層，然後再形成介電層。 本發明所揭露之尺寸約略大於晶片尺寸之施有負偏 壓的篩網，會吸引正電荷之離子，只剩下電性爲中性的 粒子會到達晶片表面，因此即使發生電漿不均勻的現象’ 天線效應不會產生。 本發明所揭露之電子流槍’會使因電漿而帶有正電 的晶片達到電性中和，因此晶片不會產生天線效應。 雖然本發明已以一較佳實施例揭露如上’然其並非 用以限定本發明，任何熟習此技藝者’在不脫離本發明 之精神和範圍內，當可作各種之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所際定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 裝·---.Packing -------- Order ---------- Y This paper size is applicable to China National Standard (CNS) Al specification (21〇χ297mm) Employees ’Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Print 4346 Si Δ7 5146twf.doc / 008 βγ V. Description of the invention (heart) After the specified thickness, remove the negative bias applied to the screen 302 to restore the general high density plasma chemical vapor deposition process. And a dielectric layer 206 is formed. Since the metal wires 202a and 202b have been covered by the dielectric liner 204 without plasma ion damage, even in the process of forming the two dielectric layers 206, positively charged ions will reach the wafer 300. These positively charged ions will still not collide with the metal wires 202a and 202b covered by the dielectric lining 204 without plasma ion damage, so the metal wires 2_02a and 202b are not completed until the intermetallic dielectric layer is completed. It will be charged, so it will not cause antenna effect. Please refer to FIGS. 2 and 3 at the same time. The formation of the dielectric liner 204 without plasma ion damage, except for the initial stage of high-density plasma chemical vapor deposition, places a size above the wafer 300 slightly larger than the wafer 300 In addition to the large and small screens 302 with negative bias, they can also be used in ion implanters, which are widely used in ion implanters to neutralize the electrical properties of wafers. While the formation of the dielectric liner 204 without plasma ion damage, the electron flow gun 304 is turned on to neutralize the positive ions that may accumulate on the wafer 300. In this way, the metal wires 202a and 202b will not have a charge 'antenna effect and thus No ^ When the dielectric liner layer 204 without plasma ion damage is formed to a specific thickness, the electron flow gun 304 is closed to restore the general high-density plasma chemical vapor deposition process, and then a dielectric layer is formed. 206. Because the metal wires 202a and 202b have been damaged by non-plasma ion 8 (Please read the precautions on the back before filling this page) i -------- ITi ------- Complete paper standards applicable to China National Standard (CNS) Al specification do X 297 mm> Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 434695 5146twf.doc / 00S V. Description of the invention (")) The dielectric lining is covered by 204, so During the formation of the dielectric layer 206, positively charged ions will reach the surface of the wafer 300, and these positively charged ions will still not collide with the metal covered by the dielectric liner 204 which is not damaged by the plasma ions. The wires 202a and 202b are thus completed until the inter-metal dielectric layer is completed, and the metal wires 202a and 202b will not carry a charge, and thus will not cause an antenna effect. In the third figure disclosed in this embodiment, the names of the other components are the reaction chamber cover (Dome) 306, the electrostatic wafer holder (ESC) 308, the turbo pump 310, and the high conductivity. 'Reaction chamber (High Conductance Chamber); 312 and Hemispherical Induction Coil (314). Since these components are not a feature of the present invention, they are not repeated here. The device for preventing the wafer from being damaged by the plasma disclosed in this embodiment is directed to a process of forming an intermetal dielectric layer. In addition, the present invention can also be applied to a process of forming a shallow trench isolation structure. The device for preventing the wafer from being damaged by the plasma disclosed in this embodiment is directed to high-density plasma chemical vapor deposition equipment. In addition, other equipment that involves plasma generation during the film formation process, such as transformer coupling Plasma plasma chemical vapor deposition equipment, or inductively coupled plasma chemical vapor deposition equipment, is also suitable for the present invention. The invention relates to a device that involves plasma generation in the process of forming a dielectric layer. A negative bias screen or an electron flow gun capable of neutralizing the electrical properties of the wafer is installed on the wafer to form the dielectric layer. Above, in order to prevent positively charged ions from hitting the surface of the wafer in the initial stage of the formation of the dielectric layer, but can be 9 (Please read the precautions on the back before filling this page) ---- Order ------- --- " This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 4346 95 Λ7 5146twf.doc / 0〇8 r ~ " V. Description of the invention (Xi) Formation of a plasmaless ion The damaged dielectric liner is then re-formed. The negatively biased sieve with a size slightly larger than the size of the wafer disclosed by the present invention will attract positively charged ions, and only the particles that are electrically neutral will reach the surface of the wafer, so even if plasma unevenness occurs Phenomenon 'antenna effect does not occur. The electron flow gun 'disclosed in the present invention will electrically neutralize the positively charged wafer due to the plasma, so the wafer will not produce an antenna effect. Although the present invention has been disclosed above with a preferred embodiment, 'but it is not intended to limit the present invention. Any person skilled in the art' can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling this page)
1T---------Y 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐）1T --------- Y Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210x297 mm)