JP2001144652A - Spread code communication unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a coding communication unit that can realize stable data transmission reception even under a low C/N environment and extend the communication distance without the need for a carrier recovery circuit and a frequency correction circuit or the like in data communication adopting the spread spectrum communication technology. SOLUTION: The communication unit consists of a QPSK modulation demodulation section 5 that receives a coded signal from a spread coding communication unit that uses a prescribed spread code so as to spread transmission data into spread data and transmits the spread data as the coding signal of the data of a phase rotation sequence depending on the waveform phase rotation direction, a signal difference arithmetic unit 7 that obtains the spread data depending on the phase rotation direction of the received coded signal and a matched filter 8 that applies inverse spread processing to the spread data on the basis of the spread code to recover the transmission data and has a plurality of correlation arithmetic means that respectively correspond to each of spread codes of different start points of the spread data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication apparatus, and more particularly to an RF (Radio Frequency) transmission / reception apparatus for performing packet communication used in an indoor LAN (Local Area Network).

[0002]

2. Description of the Related Art Conventionally, in a synchronous detection system, not only communication using a spread spectrum communication system but also information of a carrier to be transmitted such as a frequency and a phase is transmitted to a carrier receiving side. Need to be detected from For example, in a communication system using a generally used QPSK (Quadrature Phase Shift Keying) modulation / demodulation system shown in FIG. 9A, in order to demodulate received data with high reliability and accuracy, On the receiving side, a carrier used as a reference for modulation is extracted using a preamble (Preamble) provided at the head of the burst signal in a short time prior to data communication, and information on the frequency or phase of the carrier is extracted. Need to play.

However, when the frequency and phase of the carrier wave are not accurately reproduced on the receiving side, the phase of the carrier wave is shown between the transmitting side and the receiving side over time as shown in FIG. The coordinate axes of the signal space (I / Q phase plane) due to the baseband modulation signal I and the baseband modulation signal Q are rotated and shifted, and the receiving side does not match the reference for detecting the phase with the transmitting side. Erroneous determination of the transmitted data to be performed. Therefore, in the demodulation circuit using the synchronous detection as described above, a frequency correction circuit such as a carrier recovery circuit or an AFC circuit is provided to detect the information of the carrier wave on the transmission side on the reception side and always correct the phase with the transmission side. In addition, a shift such as rotation of a coordinate axis is prevented.

[0004]

However, in order for the carrier reproduction circuit or the frequency correction circuit to operate normally on the receiving side, it is necessary that a carrier having a certain signal level is received from the transmitting side. In the transmission and reception, if a spread spectrum technique is used, a carrier having a low C / N (ratio of noise to the received power of a carrier) level where a signal is originally buried in noise can be received, thereby increasing the communication distance. Although it can be expected, there is a problem that the communication level is limited due to the limitation of the reception level required for frequency correction and the like on the transmission side on the reception side.

Further, the carrier recovery circuit and the frequency correction circuit receive the carrier for a certain period, and perform signal processing such as integration operation or LPF (Low Pass Filter). Continuous carrier reception is required. As a result, the preamble period is lengthened, and the data communication efficiency is reduced.
However, in data communication such as a LAN, data is transmitted and received in packet units, so that communication from the transmitting side is intermittent, which is not suitable for frequency correction processing or the like. The present invention has been made under such a background, and does not require a carrier recovery circuit and a frequency correction circuit in data communication using spread spectrum communication technology, and is stable even in a low C / N environment. Provided is a coded communication device capable of realizing efficient transmission and reception of data and extending a communicable distance.

[0006]

According to the spread code communication apparatus of the present invention, transmission data is spread by a predetermined spread code,
And receiving means for receiving an encoded signal encoded by the rotation direction of the phase of the carrier wave comprising the I signal and the Q signal;
Decoding means for demodulating the I signal and the Q signal from the coded signal, and decoding the coded signal according to the rotation direction of the coded signal obtained based on the I signal and the Q signal, as spread data Decoding means for outputting, and a plurality of correlation operation means for despreading by taking a different phase of the spread data as a starting point of the coding and obtaining a correlation with each of the spreading codes, and outputting a correlation signal as a correlation result, A data reproducing unit that calculates the correlation signal output in time series and reproduces the transmission data based on the calculation result. With this configuration, when transmitting and receiving transmission data between the spread code communication devices, the carrier frequency on the transmitting side and the receiving side need only be substantially the same, and the spreading is performed according to the rotation direction of the phase of the coded signal. Since data is obtained, despread and the signal level is increased by the integration effect to detect transmission data, data can be sufficiently reproduced even at a low C / N level. No correction circuit is required to make the transmission side coincide with the reception side. Therefore, in the spread code communication device of the present invention, the correction circuit does not operate unless there is a sufficient C / N level.
Solve the problem of the conventional example that the distance of transmission and reception becomes short,
It is possible to increase the communication distance. Further, since the spread code communication apparatus of the present invention has a plurality of correlation calculation means, it can execute a correlation calculation with a plurality of spread codes at the same time, and can perform despreading of input spread data at high speed. It can be used for packet communication that requires real-time despreading processing quickly. further,
The spread code communication device of the present invention does not require a correction circuit, so that the circuit can be made small, and the device can be reduced in size and cost.

[0007] The decoding means comprises: the I signal and the Q signal;
In the signal space represented by the signal, with reference to the position of the phase of the coded signal obtained immediately before, the rotational direction of the position of the phase of the coded signal is determined as the change ΔI and the change ΔQ, If the data of the obtained change amount ΔI and the obtained data of the change amount ΔQ are output in a time series as the spread data, the signal space of the transmission wave by the baseband modulation signal I and the baseband modulation signal Q ( Even if the phase reference (on the I / Q phase plane) is shifted due to rotation, the spread data is coded according to the direction of phase rotation. Therefore, the rotation speed of this shift is sufficiently smaller than the rotation speed by phase modulation. With this value, the rotation direction of the phase of the carrier wave can be detected (determined). Even if the reference of the phase in the signal space changes with time, the rotation direction of the phase of the carrier wave can be detected with high accuracy. It is possible to reproduce et transmission data.

The correlation calculating means has the spreading codes as combinations of a plurality of rotation directions from different phases in the signal space, and correlates these spreading codes with the spread data. In a configuration in which correlation peaks obtained in a sequence are combined and output as the correlation signal, in a low C / N state, noise is larger than a signal level coded according to a rotation direction. Even if the phase rotation movement becomes dominant and the phase is not rotated on the I / Q phase plane in accordance with the encoding, the correlation of the decoded spread data by the spreading code by the decoding means is obtained. By doing so, only the signal that matches the spread signal is amplified by integration, so that transmission data can be reproduced even in a low C / N state.

The data reproducing means includes: a level of a negative correlation signal indicating data “0” in the correlation signal;
The level of the positive correlation signal indicating the data of “1” is compared, and when the level of the negative correlation signal is large, the transmission data is estimated and output as “0”, and the level of the positive correlation signal is If the transmission data is assumed to be “1” and output when it is large, the phase change in the time series of the received signal (the voltage difference signal DSI and the voltage output from the signal difference calculator 7). Since the correlation between the difference signal DSQ) and the spreading code is obtained, it is possible to detect (estimate) a correlation signal based on the rotation direction of the phase used for encoding by the integration effect. Accordingly, the spread code communication apparatus of the present invention determines transmission data transmitted by the transmission side accurately as a correlation peak output by decoding by a matched filter, and determines the correlation signal as “0” or “1”. ,
It can be reproduced as transmission data.

[0010] The correlation calculating means includes a data of a change amount ΔI and a change amount ΔQ inputted from the decoding means in time series.
Has a first register column and a second register column for sequentially holding and transferring each of the data, and in a register at a corresponding predetermined position, the first register column and the second register column In the configuration in which the transfer destination is exchanged between the points A to D, the crossing shift register including the first register row and the second register row sets the points A to D as the starting points of the phase rotation.
Since a data string of a phase rotation code corresponding to each of the data “1” and the data “0” can be formed, a complicated arrangement of a switching circuit is not required, and a data string generation circuit can be constituted only by hardware. Therefore, the circuit configuration is prevented from becoming large. Further, in the spread code communication device of the present invention, since the replacement process can be performed only by the shift process, the correlation value data is sequentially and rapidly (ie, real-time) from the voltage difference signal indicating the rotation direction input in time series. Can be performed.

[0011] When the correlation calculating means is constituted by a matched filter for despreading the spread data based on the spread code, the spread data input in time series from the decoding means is output for each chip. Because the correlation can be obtained in real time, the reproduction of the data constituting the packet and the determination of the start of the packet can be performed at high speed,
It can be used for packet communication that requires a high communication speed.

In the spread code communication apparatus, the correlation peak output from the decoding means is integrated for each chip timing constituting the spread code, and the transmission data is reproduced at any chip timing of one cycle of the spread code. By providing a timing correction means for correcting whether or not to perform, even if the reference of the I / Q phase plane indicating the phase of the carrier wave shifts with the passage of time, the timing of the chip of one cycle of the spreading code at which the correlation peak becomes maximum is always maintained. Since the correction is performed, the timing for determining whether the transmission data is “0” or “1” is adjusted to an optimal position, and the transmission data can be determined with high accuracy.

In the spread code communication device, by providing a circuit for correcting an error such as a convolutional code in the transmission data, the reception performance of the transmission data can be improved and the communication distance between the communication devices can be extended. It becomes possible.

In the spread code communication apparatus according to the present invention, the transmission data is spread by a predetermined spread code, and the I signal and the Q signal are transmitted.
Receiving means for receiving a coded signal coded according to the rotation direction of the phase of a carrier wave comprising a signal; demodulating means for demodulating the I signal and the Q signal from the coded signal;
A decoding means for decoding the coded signal and outputting it as spread data according to the rotation direction of the coded signal obtained based on the signal and the Q signal, and a different phase of the spread data as a starting point of coding, A plurality of sliding correlation means for despreading by taking a correlation with the spreading code and outputting a correlation signal as a correlation result, and calculating the correlation signal output in time series, and calculating the transmission data based on the calculation result. And a data reproducing means for reproducing the data. With this configuration, when transmitting and receiving transmission data between the spread code communication devices, the carrier frequency on the transmitting side and the receiving side need only be substantially the same, and the spreading is performed according to the rotation direction of the phase of the coded signal. Since data is obtained, despread and the signal level is increased by the integration effect to detect transmission data, data can be sufficiently reproduced even at a low C / N level. No correction circuit is required to make the transmission side coincide with the reception side. Therefore, the spread code communication apparatus of the present invention can solve the problem of the conventional example that the correction circuit does not operate unless the C / N level is sufficient and the transmission / reception distance is short, and can increase the communication distance. It is possible. Further, since the spreading code communication device of the present invention does not require a correction circuit, the circuit can be made small, and the device can be reduced in size and cost.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a spread code communication device according to an embodiment of the present invention. Here, a QPSK (four-phase modulation) system is used for transmission and reception. In this QPSK method, 2
The sequence-synchronized binary signals are made to correspond to two modulated waves having phases different from each other by π / 2. In the figure, a microcontroller 1 is composed of a CPU and a memory, and controls each part of the spread code communication device T according to a program stored in the memory. Details of the control of the microcontroller 1 will be sequentially described according to the description of each unit.

The microcontroller 1 converts transmission data input from another circuit (not shown) to be transmitted to another spread code communication device into a preamble or CR necessary for packet communication.
The data is converted into a series of serial data DT to which a C (Cyclic Redundancy Check) code or the like is added, and output to the convolutional encoder 2. The convolutional encoder 2 has, for example, a constraint length of 5,
This is a convolutional encoder having a coding rate of 1/2, which sequentially encodes serial data DT by a convolution operation and outputs serial data DC to the data spreading unit 3 as an encoded result.

The data spreading section 3 spreads the serial data DC output from the convolutional encoder 2 on a bit-by-bit basis, encodes the data, and outputs the resulting data to the phase rotation modulator 4 as spread data DS. That is, the data spreading unit 3
One bit sequentially input of the serial data DC is assumed to be 13 chips, and for example, a spread code “111110111” is used.
0100 ", the spectrum is sequentially spread in time series. At this time, the data spreading unit 3 sets the bit value to “1”.
, The spread data DS “11” is used as the spread data.
11101110100 ", and when the bit value is" 0 ", the spread data DS
"00000010001011" is converted to the phase rotation modulator 4
To the serial data DC in the order of the bit arrangement.

Next, referring to FIG.
Represents the spread data DS input from the data spreading unit 3,
Encoding is performed based on the chip value for each chip constituting the spread data DS. Here, the encoding performed in the phase rotation modulator 4 is based on a modulation / demodulation method capable of normally reproducing transmission data even if a frequency of a carrier generated locally between the spread code communication devices is shifted. . That is, in the conceptual diagram showing the encoding by the chip value of the phase rotation modulation in FIG. 2, the chip value of the spread data DS is changed to the baseband signal I
On an I / Q phase plane (signal space) represented by (I signal) and baseband signal Q (Q signal), a composite wave (four-phase modulated wave) of baseband signal I and baseband signal Q That is, the counterclockwise rotation of the phase of the carrier is expressed as “1”, and the clockwise rotation of the phase of the composite wave is expressed as “0”, as shown in FIG.

As shown in FIG. 2, the modulation point of the phase is a point A having a phase of "π / 4" and a phase of "3π
/ 4 ", point C having a phase of" 5π / 4 ", and point D having a phase of" 7π / 4 ". For example, A
Assuming that the point is a starting point (a start point of phase rotation), when the value of the chip is “0”, the phase of the composite wave rotates clockwise, so that the phase of the composite wave moves from point A to point D. At this time, the phase of the composite wave moves from the point A to the point D because the baseband signal Q decreases, and is expressed as “−Q”.

On the other hand, when the value of the chip is "1", the phase of the composite wave is rotated in the counterclockwise direction.
Move from point to point B. At this time, the phase of the composite wave moves from the point A to the point B because the baseband signal I decreases, and is expressed as "-I".

As a result, if the spread data DS of the "1" bit in the serial data DC is "11111011110100" as described above, the encoding is started from the left end, and the point A is the starting point of the phase rotation in the encoding. , The movement from point A is ｛A → B → C → D → A → B
→ A → B → C → D → C → D → C → B｝, [-I,
−Q, I, Q, −I, I, −I, −Q, I, −I, I,
−I, Q] is generated, and this code sequence is used as a phase rotation sequence (encoded signal). Also, if the spread data DS of the bit “0” in the serial data DC is “0000010001011” as described above,
When the point A is the starting point of the phase rotation in the encoding, the movement from the point A is ｛A → D → C → B → A → D → A → D → C →
B → C → B → C → D}, and [-Q, -I, Q, I,
-Q, Q, -Q, -I, Q, -Q, Q, -Q, I] are generated.

When the point B is a starting point (start point of phase rotation), when the value of the chip is “0”, the phase of the composite wave is rotated clockwise, so that the phase of the composite wave is shifted from the point B by A Move to a point. At this time, the phase of the composite wave moves from the point B to the point A because the baseband signal I increases, and is expressed as “I”. On the other hand, when the value of the chip is “1”, the phase of the composite wave rotates counterclockwise, so that the phase of the composite wave moves from point B to point C. At this time, the phase of the composite wave moves from the point B to the point C because the baseband signal Q decreases, and is expressed as “−Q”.

If the point C is the starting point (the starting point of the phase rotation), when the value of the chip is “0”, the phase of the composite wave rotates clockwise, so that the phase of the composite wave changes from the point C to the point B. Move to a point. At this time, the reason why the phase of the composite wave moves from the point C to the point B is that the baseband signal Q increases, which is expressed as “Q”. On the other hand, when the value of the chip is “1”, the phase of the composite wave rotates counterclockwise, so that the phase of the composite wave moves from point C to point D. At this time, the phase of the composite wave moves from the point C to the point D because the baseband signal I increases and is expressed as "I".

If the point D is the starting point (the starting point of the phase rotation), when the value of the chip is "0", the phase of the composite wave rotates clockwise. Move to a point. At this time, the phase of the synthesized wave moves from the point D to the point C because the baseband signal I decreases, and is expressed as "-I". On the other hand, when the value of the chip is “1”, the phase of the composite wave rotates counterclockwise, so that the phase of the composite wave moves from point D to point A. At this time, the phase of the composite wave moves from the point D to the point A because the baseband signal Q increases and is expressed as “Q”.

As described above, the meaning of indicating data by increasing or decreasing the baseband signal I and the baseband signal Q differs depending on which point is the starting point of rotation. For example, when increasing the baseband signal I, "0" means moving from point B to point A, while "1" means moving from point C to point D. . For this reason, the result of encoding the data of the spread code differs depending on how to take the starting point of the phase rotation.

For example, "111110" is used as the spreading code.
When "1110100" is used, the spreading code "11111011101" indicates "1" as transmission data.
00 "and the transmission code indicating" 0 "is the spreading code" 0000010001011 ". At this time, as a spreading code “11111011110100”, that is, as a spread-coded phase rotation sequence of data “1” (although the starting point of point A has been described above and repeated), the starting point of point A: [−I, −Q , I, Q, -I, I, -I,-
Q, I, -I, I, -I, Q] Point B origin: [-Q, I, Q, -I, -Q, Q, -Q,
I, Q, -Q, Q, -Q, -I] C point origin: [I, Q, -I, -Q, I, -I, I, Q,
-I, I, -I, I, -Q] Point D origin: [Q, -I, -Q, I, Q, -Q, Q,-
I, -Q, Q, -Q, Q, I]

Similarly, the spreading code “000001000
1011 ”, that is, a phase-rotated sequence of data“ 0 ”that is spread-encoded (although the A-point origin has been described above and will be repeated), the A-point origin: [−Q, −I, Q, I, − Q, Q, -Q,-
I, Q, -Q, Q, -Q, I] Point B origin: [I, -Q, -I, Q, I, -I, I,-
Q, -I, I, -I, I, Q] C point origin: [Q, I, -Q, -I, Q, -Q, Q, I,
-Q, Q, -Q, Q, -I] Point D origin: [-I, Q, I, -Q, -I, I, -I,
Q, I, -I, I, -I, -Q] As described above, the phase rotation modulator 4 includes the data spreading unit 3
Of the spread data DS input from the chip in accordance with the above rule for each chip.

Then, as a result of the encoding using the phase rotation sequence, the phase rotation modulator 4 outputs points A, B, C,
A series of phase data transiting the four phase points at point D is QP
Output to the SK modulator / demodulator 5. At this time, for example, "point A"
In the case of, the data output to the I channel and the Q channel are a signal “1” and a signal “1”, respectively. Also,
In the case of “point D”, data output to the I channel and the Q channel are a signal “1” and a signal “−1”, respectively. The signal “1” and the signal “−1” used here are each indicated by a predetermined voltage value, and indicate the amplitude of the I-channel signal and the Q-channel signal. The QPSK modulation / demodulation unit 5 generates a signal in which the phase of a carrier is modulated based on the data of each of the I-channel and Q-channel signals of the input phase rotation sequence, and modulates the phase of this carrier from the antenna 6. The signal is radiated into space as radio waves.

Next, the details of the part of the QPSK modulation / demodulation unit 5 that performs transmission processing will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration of the QPSK modulation / demodulation unit 5 in FIG. In this figure, the buffer 20
The buffer 21 shapes the waveform of the phase rotation sequence data input from the I channel and the Q channel, and outputs the data to the low-pass filter 22 and the low-pass filter 23, respectively. The low-pass filter 22 is a buffer 2
Unnecessary harmonics in the data signal of the I-channel phase rotation sequence input from 0 are removed and output to the amplifier 24. Similarly, the low-pass filter 23 removes unnecessary harmonics in the Q-channel phase rotation sequence data signal input from the buffer 21, and
Output to

The amplifier 24 adjusts the level of the signal of the data of the phase rotation sequence of the I channel input from the low-pass filter 22 to a predetermined value, and outputs it to the QPSK modulator 26. The amplifier 25 adjusts the level of the signal of the data of the phase rotation sequence of the Q channel input from the low-pass filter 23 to a predetermined value, and outputs the signal to the QPSK modulator 26. The PLL circuit 31 converts a local carrier having a frequency substantially the same as that of another spread code communication device to be transmitted to the VCO by the control signal of the microcontroller 1.
(Voltage-controlled oscillator). And
The switch 33 switches whether the carrier output from the VCO 32 is supplied to the QPSK modulator 26 or the QPSK demodulator 34 in accordance with a control signal of the microcontroller 1.

The QPSK modulator 26 changes the amplitude of each of the modulated signal I component and the modulated signal Q component for each chip of the spread data DS based on the phase rotation sequence data that is input. Also, the QPSK modulation section 26 has a VCO
The carrier wave inputted from 32 is converted into the I component and Q
The phase of the carrier is changed based on the components, and an electric signal Do (encoded signal, carrier) of a four-phase modulated wave is generated and output to the amplifier 27.

The amplifier 27 changes the electric signal Do input from the QPSK modulator 26 to a predetermined voltage and outputs the electric signal Do to the low-pass filter 28. The low-pass filter 28
Unnecessary harmonics of the electric signal Do input from the amplifier 27 are removed and output to the switch 29. The switch 29
The control signal from the microcontroller 1 controls whether the electric signal Do input from the low-pass filter 28 is output to the antenna 6 (transmission) or the electric signal Di is input from the antenna 6 to the band-pass filter 35 (reception). I do. The antenna 6 radiates the electric signal Do input from the switch 29 into space as a radio wave.

Next, the receiving unit in the spread code communication apparatus according to one embodiment will be described with reference to FIGS. The antenna 6 receives the radio wave, converts it into an electric signal Di (carrier) of a four-phase modulated wave, and outputs it to the switch 29.
The switch 29 outputs an electric signal Di input to the band-pass filter 35 according to a control signal from the microcontroller 1. The band-pass filter 35 passes only a predetermined frequency band of the input electric signal Di and outputs the electric signal Di to the linear amplifier 36. Linear amplifier 36
Amplifies the level of the input electric signal Di in a predetermined voltage range and outputs the amplified signal to the band-pass filter 37.

The band-pass filter 37 passes only a predetermined frequency band of the input electric signal Di,
Output to the amplifier 38. The amplifier 38 amplifies the input electric signal Di to a predetermined voltage level and outputs the amplified electric signal Di to a low-pass filter 39. The low-pass filter 39 is
Excessive harmonics in the input electric signal Di are removed and output to the QPSK demodulation unit 34.

The QPSK modulation / demodulation unit 2 converts the input electric signal Di into a baseband signal (demodulated signal) I which is an in-phase component and a baseband signal which is an quadrature component with respect to a local carrier generated by the VCO 32. The band signal (demodulated signal) Q is output to the amplifier 40 and the amplifier 41, respectively.
The amplifier 40 amplifies the input baseband signal I to a predetermined voltage level and outputs it to the low-pass filter 42. Similarly, the amplifier 41 amplifies the input baseband signal Q to a predetermined voltage level and outputs the same to the low-pass filter 43.

The low-pass filter 42 removes unnecessary harmonic components generated at the time of demodulation contained in the input baseband signal I, and outputs the result to the amplifier 44. Similarly,
The low-pass filter 43 removes unnecessary harmonic components generated at the time of demodulation contained in the input baseband signal Q, and outputs the result to the amplifier 45. Amplifier 44 amplifies the input baseband signal I to a predetermined voltage level, and outputs the amplified voltage to A / D converter 46. Similarly, the amplifier 45 amplifies the input baseband signal Q to a predetermined voltage level and outputs the same to the A / D converter 47.

The A / D converter 46 controls the input baseband signal I under the control of the microcontroller 1.
At a predetermined sampling rate, for example, at a rate (or speed) twice or four times the chip rate (chip transmission cycle), and digitally indicates the analog voltage value of the sampled baseband signal I. To a voltage value DVI, and a signal difference calculator 7
(See FIG. 1). Here, the obtained voltage signal DVI represents the amplitude of the baseband signal I at the time when it is extracted by sampling. Similarly, A /
Under the control of the microcontroller 1, the D converter 47 samples the input baseband signal Q at a predetermined sampling rate, for example, at a rate (or speed) twice or four times the chip rate, and performs sampling. The analog voltage value of the baseband signal Q thus converted is converted into a digital voltage value DVQ, which is output to the signal difference calculator 7 (see FIG. 1). Here, the obtained voltage signal DVQ represents the amplitude of the baseband signal Q at the time of sampling.

Whether the ratio of the oversampling is doubled or quadrupled depends on the balance between the performance and the circuit size. The following description will be made with reference to the quadrupled oversampling as an example. At this time, the sampling in the A / D converter 46 and the A / D converter 47 is performed, for example, as shown in FIG.
And at a sampling rate four times the chip rate of the baseband signal Q, each of the baseband signals I and Q is oversampled. FIG.
(A) is a conceptual diagram showing sampling processing of baseband signal I or baseband signal Q. And A
The / D converter 46 outputs a voltage signal DVI indicating the amplitude of the baseband signal I, and the A / D converter 47 outputs a voltage signal DVQ indicating the amplitude of the baseband signal Q.

Next, in FIG. 1, the signal difference calculator 7
For example, as a first calculation method for obtaining the voltage difference signal DSI, the input voltage signal DVI is subtracted from the previously sampled voltage signal DVI, and the voltage difference signal DSI (variation ΔI) is obtained as the voltage difference between the two. Matched filter 8
Output to At this time, the voltage signal DVI sampled at the sampling point in FIG.
And the voltage difference signal DSI, DSI1 = DVI5-DVI1 DSI2 = DVI6-DVI2 DSI3 = DVI7-DVI3...

Here, DSI1, DSI2, DSI3,...
Is a voltage difference signal D sequentially output from the signal difference calculation circuit 7.
It shows the voltage value of SI. Also, DVI1 to DVI3,
DVI5 to DVI7 correspond to the A / D converter 46 shown in FIG.
A voltage value obtained by A / D (analog / digital) conversion is shown by sampling at sampling point P1, sampling point P2, sampling point P3, sampling point P5, sampling point P7, and sampling point P7 shown in FIG. I have.

Similarly, the signal difference calculator 7 subtracts the input voltage signal DVQ from the previously sampled voltage signal DVQ as a first calculation method for obtaining the voltage difference signal DSQ, for example. Voltage difference signal D as voltage difference
SQ (change amount ΔQ) is output to the matched filter 8.
At this time, the relationship between the voltage signal DVQ sampled at the sampling point in FIG. 4A and the voltage difference signal DSQ is as follows: It has become.

Here, DSQ1, DSQI2, DSQ3,
.. Indicate the voltage values of the voltage difference signal DSQ sequentially output from the signal difference calculation circuit 7. DVQ1 to DVQ
3, DVQ5 to DVQ7 are provided by the A / D converter 47 when the sampling point PP1, the sampling point PP2, the sampling point PP3, the sampling point PP5, and the sampling point PP shown in FIG.
7, a voltage value obtained by A / D (analog / digital) conversion by sampling at a sampling point PP7.

As a second method of calculating the voltage difference signal DSI, the voltage difference signal DVI obtained by quadrupling oversampling is supplied to the signal difference calculator 7 instead of the configuration for calculating the voltage difference signal DSI described above. It is also possible to subtract from the previously sampled voltage signal DVI while thinning out at a predetermined interval, and output the voltage difference signal DSI (variation ΔI) to the matched filter 8 as the voltage difference between them. At this time, the relationship between the voltage signal DVI sampled at the sampling point in FIG. 4A and the voltage difference signal DSI is as follows: DSI1 = DVI4-DVI1 DSI2 = DVI6-DVI3 DSI3 = DVI8-DVI5... It has become.

That is, in the second operation method, unlike the first operation method, the voltage signals DVI sampled at all the sampling points are not used continuously. DVI4 and DVI1 used to determine DSI1 are not used in subsequent calculations. In this case, sampling points used for calculation are thinned out as compared with the first calculation method. According to the second calculation method, the signal difference calculator 7 can obtain the voltage difference signal DSI at a calculation speed 1/2 that of the first method (double oversampling). Here, DSI1, DSI2, DSI3,... Indicate voltage values of the voltage difference signal DSI sequentially output from the signal difference calculation circuit 7. Also, DVI1, DVI3 to DVI
6, DVI8 is sampled by the A / D converter 46 at the sampling point P1, sampling point P3, sampling point P4, sampling point P5, sampling point P6, and sampling point P8 shown in FIG. analog/
(Digital) conversion.

Similarly, as a second operation method of the voltage difference signal DSQ, as in the above-described second operation method of the voltage difference signal DSI, the signal difference calculator 7 is obtained by four times oversampling. While thinning out the voltage signal DVQ at a predetermined interval, the previously sampled voltage signal DVQ
, And a voltage difference signal DSQ (change amount ΔQ) can be output to the matched filter 8 as a voltage difference between the two. At this time, the voltage signal DVQ sampled at the sampling point in FIG.
, And the voltage difference signal DSQ, DSQ1 = DVQ4-DVQ1 DSQ2 = DVQ6-DVQ3 DSQ3 = DVQ8-DVQ5...

That is, in the second operation method, unlike the first operation method, the voltage signals DVQ sampled at all the sampling points are not used continuously, but as shown in the above-mentioned equation. DVQ4 and DVQ1 used to determine DSQ1 are not used in subsequent calculations. In this case, sampling points used for calculation are thinned out as compared with the first calculation method. According to the second calculation method, the signal difference calculator 7 can obtain the voltage difference signal DSQ at a calculation speed 1/2 that of the first method. Here, DSQ1, DSQ2, DSQ
.. Indicate the voltage values of the voltage difference signal DSI sequentially output from the signal difference calculation circuit 7. DVQ1, DQ
VQ3 to DVQ6 and DVQ8 are A / D converters 47.
Are the sampling points PP1, PP3, and PP shown in FIG.
4, sampling points PP5, sampling points PP6, and sampling points PP8 indicate voltage values obtained by A / D (analog / digital) conversion.

The voltage difference signal DSI input from the signal difference calculation circuit 7 indicates the amount of change in the amplitude information of the baseband signal I. That is, depending on the polarity of the subtraction result, the voltage value of the baseband signal I sampled this time is increased with respect to the baseband signal I sampled last time, or the baseband signal It can be determined whether the voltage value of I has decreased. Thus, the signal difference calculator 7 outputs the voltage difference signal DSI as data on which the rotation direction is estimated. Similarly, the voltage difference signal DSQ is the baseband signal Q
Of the amplitude information shown in FIG. That is, depending on the polarity of the subtraction result, the voltage value of the baseband signal Q sampled this time is increased with respect to the baseband signal Q sampled last time, or the baseband signal It can be determined whether the voltage value of Q has decreased. Thereby, the signal difference calculator 7 outputs the voltage difference signal DSQ as data on which the rotation direction is estimated.

The matched filter 8 decodes transmission data transmitted from another spread code communication apparatus based on the input voltage difference signal DSI and voltage difference signal DSQ, that is, a signal encoded based on the rotation direction. Decrypts the
Despread the composited spread data to obtain data "1"
The correlation data MP indicating the correlation peak of the data or the correlation data MM indicating the correlation peak of the data “0” is output.

Here, the matched filter 8 is composed of a matched filter 300 and a matched filter 500 as shown in FIG. At this time, since the sampling is performed at the same rate (or speed) as the baseband signal I and the baseband signal Q, the voltage difference signal DVI and the voltage difference signal DVQ input from the signal difference calculator 7 are used.
Has the same rate (or speed) as the baseband signal I and the baseband signal Q.

The matched filter 300 outputs the correlation data MP and the correlation data M, each of which indicates the correlation peak of the data “1” and the data “0” between the points A and C at the start point of the phase rotation.
M is output by sequentially performing despreading processing with predetermined spread data based on the voltage difference signal DSI and the voltage difference signal DSQ input in time series. Similarly, the matched filter 500 converts each of the correlation data MP and the correlation data MM in which the starting point of the phase rotation indicates the correlation peak of the data “1” and the data “0” between the points B and D in time series. Based on the input voltage difference signal DSI and voltage difference signal DSQ, output is performed by sequentially performing despreading processing with predetermined spread data.

The matched filter 300 performs the calculation of the correlation value, that is, the despreading process, with the configuration shown in FIG. FIG. 6 is a block diagram showing a configuration of the matched filter 300 of FIG. As shown in FIG. 6, the matched filter 300 calculates a correlation data MP which is a correlation peak of data “1”, and a match filter which calculates correlation data MM which is a correlation peak of data “0”. Filter section 370, input voltage difference signal DS
The cross shift register 380 includes two shift registers 380A and 380B for rearranging and shifting the I and voltage difference signals DSQ. Shift register 380A is formed from registers 400 to 412, and shift register 380B is formed from registers 450 to 462.

The matched filter 500 performs the calculation of the correlation value, that is, the despreading process, by the configuration shown in FIG. FIG. 7 is a block diagram showing a configuration of the matched filter 500 of FIG. As shown in FIG. 7, the matched filter 500 calculates the correlation data MP which is the correlation peak of the data "1", and the match filter 520 which calculates the correlation data MM which is the correlation peak of the data "0". Filter section 570, input voltage difference signal DS
Two-system shift register 580A and shift register 580B for rearranging and shifting I and voltage difference signal DSQ
And a cross shift register 580.

At this time, in the matched filter 300, the matched filter unit 320 generates the phase rotation sequence data corresponding to the data “1” generated according to the spreading code and having the point A or C as the starting point of the phase rotation. Then, it is detected whether or not the spread data formed by rearranging the voltage difference signal DSI and the voltage difference signal DSQ input in time series match. Similarly, in matched filter 300, matched filter section 370 generates a phase rotation sequence data corresponding to data “0” generated based on the spreading code and having point A or C as a phase rotation start point, and a time series To detect whether or not the voltage difference signal DSI and the voltage difference signal DSQ input to the input terminal are the same as the spread data formed by rearranging the signals.

Here, the phase rotation sequence in encoding is:
It is assumed to be indicated by paragraph number 0026 and paragraph number 0027. That is, the matched filter 300 sequentially converts the voltage difference signal DSI and the voltage difference signal DSQ input from the signal difference calculator 7 into data “1” and data “1”, Rearrange data "0" into a data format corresponding to each phase rotation sequence to be encoded

That is, in response to the encoding of the data "1", the data string D1 [DSI, DSQ, DSI, DS
Q, DSI, DSI, DSI, DSQ, DSI, DS
I, DSI, DSI, DSQ]. On the other hand, corresponding to the encoding of the data “0”, the data string D3 [DSQ, D
SI, DSQ, DSI, DSQ, DSQ, DSQ, DS
I, DSQ, DSQ, DSQ, DSQ, DSI]. The data sequence D1 described above indicates a phase rotation sequence indicating data “1” starting from the points A and C. Similarly, the data sequence D3 indicates a phase rotation sequence indicating data “0” starting from the points A and C.

Referring to FIG. 6, a cross shift register 380 is shown.
Shift register 380A and shift register 3 in FIG.
80B inputs the input data strings in time series,
Shift rightward sequentially. Here, the shift register 380A and shift register 380B are input to the data string from the left end of the data in the string. Line segments # 1 and # 2 in FIG. 6 indicate the flow of the data shift operation in the shift register 380A and the shift register 380B, respectively. As can be seen from the line segment # 1 and the line segment # 2, the shift register 380A and the shift register 380B are configured such that the connection of the constituent registers crosses at a predetermined register position so that the data string can be rearranged. ing. That is, the configuration of the shift register 380A and the shift register 380B is configured by the register connection shown in FIG. FIG. 8 is a block diagram showing a configuration of the cross shift register 380 of FIG.

In FIG. 8, shift register 380A
Is composed of 13 registers 400 to 412, and is inputted from the signal difference calculator 7.
The data of the data sequence sampled in the cycle of the chip is input, and the shift operation is sequentially performed. At this time, the spread code has 13 chips and is input at a sampling rate that does not cause oversampling, and the shift register 380A has 13 (the number of spread code chips) registers. Similarly, in FIG. 8, shift register 380B includes registers 450 to
The register 462 includes 13 registers.
A shift operation is performed by inputting data of a data sequence sampled in a chip cycle. At this time, since the spreading code is 13 chips and is input at a sampling rate at which oversampling is not performed,
The shift register 380B includes 13 registers (the number of chips of the spread code).

In the shift registers 380A and 380B, the output terminal of the register 400 is connected to the input terminal of the register 451, and the output terminal of the register 450 is connected to the input terminal of the register 401. Are configured to intersect. Similarly, the shift register 380A and the shift register 380B have the output terminal of the register 404 connected to the register 4
55, the output terminal of the register 454 is connected to the input terminal of the register 405,
5 is connected to the input terminal of the register 456, and the output terminal of the register 455 is connected to the register 406.
, The output terminal of the register 408 is connected to the input terminal of the register of the register 459, the output terminal of the register 458 is connected to the input terminal of the register of the register 409, and the output terminal of the register 459 is connected to the register An output terminal of the register 409 is connected to an input terminal of the register of the register 460, an output terminal of the register 460 is connected to an input terminal of the register of the register 411, and an output terminal of the register 410 is connected to the input terminal of the register 410. The input terminal of the register 461 is connected to the input terminal of the register.
12 is connected to the input terminal of the
Are connected to the input terminals of the registers of the register 462 so that the data shift processing flows cross each other.

Thus, the matched filter 300
Voltage difference signal DSI and voltage difference signal D input in time series
SQ is a data string stored in the shift register 380A, that is, data input in order from the left end (reverse relationship to the data shift direction in the shift register 380A shown in FIGS. 6 and 8). [DSI1, DSQ2, DSI3, DSQ4, DSI
5, DSI6, DSI7, DSQ8, DSI9, DSI
10, DSI11, DSI12, DSQ13]. For example, the leftmost bit of the data string is the register 4
12 corresponds to the bit stored in the T.12.

Similarly, the matched filter 300 includes a voltage difference signal DSI and a voltage difference signal DSQ input in time series.
As a data string stored in the shift register 380B, that is, data input in order from the left end (the relationship opposite to the data shift direction in the shift register 380B shown in FIGS. 6 and 8), for example, the shift register 380A At the same timing as the data sequence [DSQ1, DSI2, DSQ3, DSI4, DSQ
5, DSQ6, DSQ7, DSI8, DSQ9, DSQ
10, DSQ11, DSQ12, DSI13]. For example, the leftmost bit of the data string is the register 4
It corresponds to the bit stored in 62. At this time, the voltage difference signal DSQ is input from the signal difference calculator 7 to the register 400 in time series, and the voltage difference signal DSI is input to the register 450 in time series.

In FIG. 6, multipliers 301 to 313 respectively include a register 412, a register 411, a register 410,... In a shift register 380A.
..., register 402, register 401, register 400
To the value output (stored) by each register,
Multiplication is performed under the control of the controller 1 using “−1” or “1” as a code. Then, the multipliers 301 to 3
13 outputs the result of the multiplication to the correlation adder 315. Similarly, the multipliers 351 to 363 are respectively connected to the registers 462, 461, 460,..., 452, 451, and 450 in the shift register 380B, and output (store) the registers. ) The value is multiplied by the control of the controller 1 with “−1” or “1” as a sign. Then, the multipliers 351 to 363 output the multiplied results to the correlation adder 365.

As described above, the matched filter section 320 in the matched filter 300 multiplies each voltage difference signal by a code indicating each rotation direction of the phase rotation sequence corresponding to the data sequence D1, and Add data.
That is, the code {−1, −1, 1, 1, −− of the phase rotation sequence used for encoding the data “1” starting from the point A.
1,1, −1, −1,1, −1,1, −1,1} are converted by the multipliers 301 to 313 into a data string D1 [DS
I, DSQ, DSI, DSQ, DSI, DSI, DS
I, DSQ, DSI, DSI, DSI, DSI, DS
Q] is multiplied to the corresponding chip.

At this time, the data string D1 is stored in the register 412 and the register 41 in the shift register 380A.
1, register 410, register 409, register 40
8, register 407, register 406, register 40
5, register 404, register 403, register 40
2. The shifted voltage difference signal DSI and the shifted voltage difference signal DSQ are respectively supplied to the register 401 and the register 400 by [DS
I1, DSQ2, DSI3, DSQ4, DSI5, DS
I6, DSI7, DSQ8, DSI9, DSI10, D
SI11, DSI12, DSQ13]. Then, the multipliers 301 to 313
Data sequence (spread data) resulting from multiplication of the above code
[-DSI1, -DSQ2, DSI3, DSQ4, -D
SI5, DSI6, -DSI7, -DSQ8, DSI
9, -DSI10, DSI11, -DSI12, DSQ
13], that is, the data of the voltage difference signal corresponding to the polarity of the phase rotation sequence in the rotation direction is output to the correlation adder 315. Accordingly, the correlation adder 315 outputs the data string (spread data) [-DSI1, -DSQ2, DSI3, DSQ
4, -DSI5, DSI6, -DSI7, -DSQ8,
DSI9, -DSI10, DSI11, -DSI12,
DSQ13], and the result of the addition is output as correlation data MP of the peak of the positive value of the matching (correlation).

Similarly, regarding the decoding of the encoding of the data “1” starting from the point C, the data string D
1 that is the same as the polarity of the code of the phase rotation sequence starting from point A multiplied by each element of ｛−1, −1, 1, 1, 1,
−1,1, −1, −1,1, −1,1, −1,1},
For the data string D1 stored in the registers 412, 411, 410, 409, 408, 407, 406, 405, 404, 403, 402, 401, and 400, The data strings [-DSI1, -DSQ2, DSI3, DSQ4, -D multiplied by the multipliers 301 to 313, respectively.
SI5, DSI6, -DSI7, -DSQ8, DSI
9, -DSI10, DSI11, -DSI12, DSQ
13] is output to the correlation adder 315. This allows
The correlation adder 315 generates a data string [−D
SI1, -DSQ2, DSI3, DSQ4, -DSI
5, DSI6, -DSI7, -DSQ8, DSI9,-
DSI10, DSI11, -DSI12, DSQ13]
Is output as correlation data MP of the peak of the negative value of the matching (correlation).

The matched filter section 370 in the matched filter 300 multiplies each voltage difference signal by a code indicating the rotation direction of each of the phase rotation sequences corresponding to the data sequence D3, and converts the data in the data sequence. to add. That is, the codes {−1, −1, 1, 1, −1, −1, −1, −1, 1, 1, −1, of the phase rotation sequence used for encoding the data “0” starting from the point A.
1, −1, −1,1, −1,1, −1,1} are subjected to a data sequence D3 [DSQ,
DSI, DSQ, DSI, DSQ, DSQ, DSQ, D
Each of the chips corresponding to SI, DSQ, DSQ, DSQ, DSQ, DSI} is multiplied.

At this time, the data string D3 is stored in the register 46.
2, register 461, register 460, register 45
9, register 458, register 457, register 45
6, register 455, register 454, register 45
3, register 452, register 451, register 450
The shifted voltage difference signal DSI and the shifted voltage difference signal DSQ respectively correspond to [DSQ1, DSI2, DSQ3, DSI
4, DSQ5, DSQ6, DSQ7, DSI8, DSQ
9, DSQ10, DSQ11, DSQ12, DSI1
3] is stored. Then, the multiplier 35
The multipliers 1 to 363 generate a data string (spread data) [−DSQ1, −DSI2, DS>
Q3, DSI4, -DSQ5, DSQ6, -DSQ7,
−DSI8, DSQ9, −DSQ10, DSQ11, −
DSQ12, DSI13], that is, data of the voltage difference signal corresponding to the polarity in the rotation direction of the phase rotation sequence to the correlation adder 365. Thereby, the correlation adder 365
Is a data string (spread data) [-DSQ1, -DSI
2, DSQ3, DSI4, -DSQ5, DSQ6, -D
SQ7, -DSI8, DSQ9, -DSQ10, DSQ
11, -DSQ12, DSI13], and outputs the addition result as correlation data MP of the peak of the positive value of the matching (correlation).

As for the decoding of the coding starting from the point C, the same code {−1} as the code of the phase rotation sequence starting from the point A obtained by multiplying each element of the data sequence D3 in the above description. , -1,1,1, -1,1, -1, -1, -1,
1, −1,1, −1,1} are stored in the registers 462, 461, 460, 459, 458, 457, 456, 4
55, register 454, register 453, register 45
2, the data string D3 stored in the register 451 and the register 450 is multiplied by the multipliers 351 to 363, and the multiplied data string [−DSQ1, −DS
I2, DSQ3, DSI4, -DSQ5, DSQ6,-
DSQ7, -DSI8, DSQ9, -DSQ10, DS
Q11, -DSQ12, DSI13] is the correlation adder 36
5 is output. Accordingly, the correlation adder 365 converts the data sequence of the voltage difference signal into [-DSQ1, -DSI2,
DSQ3, DSI4, -DSQ5, DSQ6, -DSQ
7, -DSI8, DSQ9, -DSQ10, DSQ1
1, -DSQ12, DSI13] are added. As a result, the addition result is output as correlation data MM of a negative peak of matching (correlation).

On the other hand, in matched filter 500 of FIG. 7, matched filter section 520 generates phase rotation sequence data corresponding to data “1” originating at point B or D generated according to the spreading code, It is detected whether or not the voltage difference signal DSI and the voltage difference signal DSQ input in time series match the spread data formed by rearranging.
Similarly, in matched filter 500, matched filter section 570 receives the phase rotation sequence data corresponding to data “0” originating from point D or point B, generated in accordance with the spreading code, and time-series input. Voltage difference signal DSI
Then, it is detected whether or not the spread data formed by rearranging the voltage difference signal DSQ match.

Here, the phase rotation sequence in encoding is:
It is assumed to be indicated by paragraph number 0026 and paragraph number 0027. That is, the matched filter 500 sequentially converts the voltage difference signal DSI and the voltage difference signal DSQ input from the signal difference calculator 7 into data “1” and “1” Rearrange data "0" into a data format corresponding to each phase rotation sequence to be encoded

That is, in response to the encoding of the data "1", the data string D2 [DSQ, DSI, DSQ, DS
I, DSQ, DSQ, DSQ, DSI, DSQ, DS
Q, DSQ, DSQ, DSI]. On the other hand, corresponding to the encoding of the data “0”, the data string D4 [DSI, D
SQ, DSI, DSQ, DSI, DSI, DSI, DS
Q, DSI, DSI, DSI, DSI, DSQ]. The data sequence D2 described above indicates a phase rotation sequence indicating data “1” starting from the points B and D. Similarly, the data sequence D4 indicates a phase rotation sequence indicating data “0” starting from the points D and B.

In FIG. 7, cross shift register 580
Shift register 580A and shift register 5
80B inputs the input data strings in time series,
Shift rightward sequentially. Here, the shift register 580A and shift register 580B are input to the data string from the left end of the data in the string. Lines # 3 and # 4 in FIG. 6 indicate the flow of the data shift operation in shift register 580A and shift register 580B, respectively. As can be seen from the line segments # 3 and # 4, the shift register 580A and the shift register 580B are configured such that the connection of the constituent registers crosses at a predetermined register position so that the data string can be rearranged. ing.

That is, the configuration of shift register 580A and shift register 580B is similar to that of shift register 380.
A and the shift register 380B are configured by the register connection shown in FIG. FIG. 8 is a block diagram showing a configuration of the cross shift register 580 of FIG. The structure of the shift register 580A and the shift register 580B is the same as that of the shift register 380A and the shift register 380.
The description is omitted because it is the same as B. At this time, the voltage difference signal DSI is input to the register 400 in time series, and the voltage difference signal DSQ is input to the register 450 in time series.

In FIG. 8, shift register 580A
Is composed of thirteen registers of registers 400 to 412, inputs data of a data string sampled at the cycle of the chip input from the signal difference calculator 7, and sequentially performs a shift operation. . At this time, the spread code has 13 chips and is input at a sampling rate that does not cause oversampling, and the shift register 580A has 13 (the number of chips of the spread code) registers. Similarly, in FIG. 8, shift register 580B includes registers 450 to 4
It is constituted by 13 registers of 62, and inputs data of a data string sampled at a cycle of an input chip and performs a shift operation. At this time, the spread code has 13 chips and is input at a sampling rate that does not cause oversampling, and the shift register 580B has a register number of 13 (the number of chips of the spread code).

With the above configuration, the matched filter 50
0 indicates that the voltage difference signal DSI and the voltage difference signal DSQ input in time series are data strings stored in the shift register 580A, that is, data input in order from the left end (see FIG. 7 and FIG. 8). The relationship opposite to the data shift direction in the register 580A), for example, a data string [DSI, DSQ, DSI, DSQ, DSI, DS
I, DSI, DSQ, DSI, DSI, DSI, DS
I, DSQ]. For example, the leftmost bit of the data string corresponds to the bit stored in the register 412.

Similarly, the matched filter 500 includes a voltage difference signal DSI and a voltage difference signal DSQ input in time series.
As a data string stored in the shift register 580B, that is, data sequentially input from the left end (the relationship opposite to the data shift direction in the shift register 580B shown in FIGS. 7 and 8). At the same timing, the data string [D
SQ1, DSI2, DSQ3, DSI4, DSQ5, D
SQ6, DSQ7, DSI8, DSQ9, DSQ10,
DSQ11, DSQ12, DSI13].
For example, the leftmost bit of the data string corresponds to the bit stored in the register 462.

In FIG. 7, multipliers 501 to 513 respectively include registers 412, 411, 410,... In shift register 580A.
..., register 402, register 401, register 400
To the value output (stored) by each register,
Multiplication is performed under the control of the controller 1 using “−1” or “1” as a code. Then, the multipliers 501 to 5
13 outputs the result of the multiplication to the correlation adder 515. Similarly, the multipliers 551 to 563 are connected to the registers 462, 461, 460,..., 452, 451, and 450 of the shift register 580B, and output (store) the registers. ) Multiply the value by the control of the controller 1 with “−1” or “1” as a sign. Then, the multipliers 551 to 563 output the multiplied results to the correlation adder 565.

At this time, in matched filter section 520, the codes 系列 −1, 1, 1, −1, −1, −1 of the phase rotation sequence used for encoding “1” data starting from point B
1, −1,1,1, −1,1, −1, −1} are subjected to data sequence D2 [DSQ,
DSI, DSQ, DSI, DSQ, DSQ, DSQ, D
SI, DSQ, DSQ, DSQ, DSQ, DSI].

At this time, the data string D2 is stored in the register 41
2, register 411, register 410, register 40
9, register 408, register 407, register 40
6, register 405, register 404, register 40
3, register 402, register 401, register 400
Respectively, the shifted voltage difference signal DSI and the shifted voltage difference signal DSQ are respectively [DSQ1, DSI2, DSQ3, D
SI4, DSQ5, DSQ6, DSQ7, DSI8, D
SQ9, DSQ10, DSQ11, DSQ12, DSI
13] is stored. And a multiplier 5
01 to multiplier 513 form a data sequence (spread data) [-DSQ1, DSI2, DS
Q3, -DSI4, -DSQ5, DSQ6, -DSQ
7, DSI8, DSQ9, -DSQ10, DSQ11,
−DSQ12, −DSI13], that is, data of the voltage difference signal corresponding to the polarity in the rotation direction of the phase rotation sequence, to the correlation adder 515. Thereby, the correlation adder 51
5 is a data string (spread data) [-DSQ1, DSI
2, DSQ3, -DSI4, -DSQ5, DSQ6,-
DSQ7, DSI8, DSQ9, -DSQ10, DSQ
11, -DSQ12, -DSI13], and
The result of the addition is output as correlation data MP of the peak of the positive value of the matching (correlation).

Similarly, in matched filter section 520, with respect to the decoding of the encoding of the data “1” starting from point D, point B obtained by multiplying each element of data string D2 in the above manner ｛-1,1,1, −1, −1,1, −1,1,
1, -1, 1, -1, -1} are stored in the registers 412, 411, 410, 409, 408, 407, 406, 405, 404, 403, and 4
02, the register 401, and the data string D2 stored in the register 400, the multiplier 501 to the multiplier 513.
[-DSQ1, DSI
2, DSQ3, -DSI4, -DSQ5, DSQ6,-
DSQ7, DSI8, DSQ9, -DSQ10, DSQ
11, -DSQ12, -DSI13] is a correlation adder 56.
5 is output. Thereby, the correlation adder 565, the data sequence of the voltage difference signal [−DSQ1, DSI2, DSQ
3, -DSI4, -DSQ5, DSQ6, -DSQ7,
DSI8, DSQ9, -DSQ10, DSQ11, -D
SQ12, -DSI13] is output as correlation data MP of a negative peak of matching (correlation).

On the other hand, in matched filter section 570, the codes of the phase rotation sequence {-1, 1, 1, -1, -1, -1,
1, −1, 1, 1, −1, 1, −1, −1} are converted into a data sequence D4 [DSI,
DSQ, DSI, DSQ, DSI, DSI, DSI, D
SQ, DSI, DSI, DSI, DSI. DSQ] to the corresponding chip.

At this time, the data string D4 is stored in the register 46.
2, register 461, register 460, register 45
9, register 458, register 457, register 45
6, register 455, register 454, register 45
3, register 452, register 451, register 450
The shifted voltage difference signal DSI and the shifted voltage difference signal DSQ are respectively [DSI1, DSQ2, DSI3, DSQ
4, DSI5, DSI6, DSI7, DSQ8, DSI
9, DSI10, DSI11, DSI12. DSQ1
3] is stored. And the multiplier 55
1 to multiplier 563 perform a data sequence (spread data) [-DSI1, DSQ2, DSI
3, -DSQ4, -DSI5, DSI6, -DSI7,
DSQ8, DSI9, -DSI10, DSI11, -D
SI12, -DSQ13], that is, data of a voltage difference signal corresponding to the polarity of the phase rotation sequence in the rotation direction, to the correlation adder 565. Thus, the correlation adder 565
Is a data string (spread data) [-DSI1, DSQ2,
DSI3, -DSQ4, -DSI5, DSI6, -DS
I7, DSQ8, DSI9, -DSI10, DSI1
1, -DSI12, -DSQ13], and the result of the addition is output as correlation data MM of a peak of a positive value of matching (correlation).

Similarly, as for the decoding of the encoding based on the rotation at the point B, the same code as the code of the phase rotation sequence starting at the point D obtained by multiplying each element of the data sequence D4 in the above description. -1,1,1, -1, -1, -1, -1,
1,1, -1,1, -1, -1} are stored in registers 462,
Multiplier 351 is applied to data string D3 stored in register 461, register 460, register 459, register 458, register 457, register 456, register 455, register 454, register 453, register 452, register 451, and register 450. ~ Multiplier 3
63, and the multiplied data sequence [−DSI1,
DSQ2, DSI3, -DSQ4, -DSI5, DSI
6, -DSI7, DSQ8, DSI9, -DSI10,
DSI11, -DSI12, -DSQ13] are output to the correlation adder 565. Thus, the correlation adder 565
Is a data string [-DSI1, DSQ of the voltage difference signal.
2, DSI3, -DSQ4, -DSI5, DSI6,-
DSI7, DSQ8, DSI9, -DSI10, DSI
11, -DSI12, -DSQ13] is output as the correlation data MM of the negative peak of matching (correlation).

In the decoding as described above, the matched filter 8 operates in the phase rotation sequence using the data “1” and the data “0” in the transmission data, as in the case where the point A is the starting point. When the starting point is set to point B, point C, and point D, the timing (corresponding to the number multiplied by oversampling if oversampling) is transferred in time series for matching (correlation) with the phase rotation sequence The correlation data MP and the correlation data MM are sequentially output to the peak synthesis circuit 9 and the peak configuration circuit 10, respectively.

At this time, as described above, the correlation data MP and the correlation data MM have the same sign and polarity of the phase rotation sequence (the starting point of point A and the starting point of point B in the case of data "1"), or The opposite polarity (C for data "1")
(Point origin and D point origin), the intensity of the correlation signal of the maximum peak is obtained. Conversely, if the polarities of the codes are different and do not match, the addition results are averaged, and the peak of the correlation value decreases. That is, each time a new voltage difference signal is input, the matched filter 8 sequentially corresponds to the data “1” and the data “0” to the voltage difference signal input from the signal difference calculator 7 in time series. The correlation values obtained by multiplying and adding the signs of the phase rotation sequence starting from the points A to D are used as the correlation data MP and the correlation data MM, respectively, as the peak synthesis circuit 9 and the peak synthesis circuit 10. Output to

At this time, the correlation data MP and the correlation data MM are, as described above, if the sign and the polarity of the phase rotation sequence match (in the case of data "1", the starting point of point A, the starting point of point B, and the data " 0 "reference and A reference),
The maximum peak correlation signal strength of the positive value is obtained, while
If the respective rotation directions are completely opposite polarities (starting point C and starting point D for data "1", starting point C and point B for data "0"), the maximum peak of a negative value Are obtained. Conversely, the shift register 38
In the case where 0A and the polarity of the sign of each chip of the data string of the shift register 380B are different from each other, that is, when they are not spread data indicating data “0” and data “1”, respectively, the correlation adder 315 and Correlation adder 365
Are averaged, and the addition result is not limited to a positive value or a negative value.
The peak of the correlation value output from 65 decreases. Similarly, shift register 580A and shift register 580
If the sign polarity of each chip of the data string of B is disjoint, that is, if it is not spread data indicating data “0” and data “1”, respectively, the correlation adder 5
15 and the addition result in the correlation adder 565 are averaged, and the peak of the correlation value output from the correlation adder 515 and the correlation adder 565 is not limited to a positive value or a negative value.

That is, every time a new voltage difference signal is input, the matched filter 8 causes the signal difference calculator 7 to sequentially and sequentially set a set of voltage difference signals indicating a phase change at the same time. , Shift register 380A, shift register 380B, shift register 580A shift register 58
0B. As described above, for example, the set of voltage difference signals DSI is input according to the line segment # 1, the set of voltage difference signals DSQ is input according to the line segment # 2, and the set of voltage difference signals DSI is set to the line # 3. And a set of voltage difference signals DSQ is input and input according to the line segment # 4.

As a result, the data strings of the voltage difference signals stored in the shift registers 380A and 380B and the shift registers 580A and 580B have A corresponding to data “1” and data “0”, respectively. Point and point B (D for shift register 52B)
The correlation value obtained by multiplying and adding the sign of the phase rotation sequence starting from the point (point) is output to the peak synthesis circuit 9 and the peak synthesis circuit 10 as correlation data MP and correlation data MM, respectively. At this time, the shift registers 380A and 380B and the shift registers 580A and 580B shift the data one bit to the right each time a new voltage difference signal is input. Thereby, the data of the register 412 and the data of the register 462 are shifted rightward,
Discarded.

The intersection of the input / output signal connection of each register in the shift register 380A and the shift register 380B described above may be controlled, for example, by the program control of the microcontroller 1, as necessary, for example, the phase-rotation series data strings D1 to D1. When the combination of the data in the data string D4, that is, when the spreading code is changed, it is possible to change so as to intersect at any register part. The intersection of the input / output signal connection of each register in the shift register 580A and the shift register 580B may be controlled, for example, by the program control of the microcontroller 1, as necessary, for example, by the data sequence of the data sequence D1 to data sequence D4 of the phase rotation sequence. , That is, when the spreading code is changed, it is possible to change so as to intersect at any register part.
Similarly, multipliers 301 to 313 and multipliers 351 to 351
The code of the phase rotation sequence to be multiplied by the phase rotation sequence in the multiplier 363, the multipliers 501 to 513, and the multipliers 551 to 563 is also controlled by the program control of the microcontroller 1 if necessary. The polarity setting can be changed, for example, when the combination of the data strings D1 to D4 of the rotation sequence, that is, when the spreading code is changed.

The peak synthesis circuit 9 includes a matched filter 8
, The absolute values of the correlation data MP starting from the point A (or point C) and the point B (or point D) are taken, and all of them are added to obtain the addition data DP.
Output to 1. Similarly, the peak synthesizing circuit 10 outputs the point A (or C
Point), correlation data MM starting from point D (or point B)
, And add them all to output the added data DM to the difference calculator 11.

At this time, every time the voltage difference signal is input, the peak synthesizing circuit 9 calculates the absolute value of the correlation data MP starting from the point A (or point C) output from the matched filter 8 and the absolute value of B Correlation data M starting from point (or point D)
It adds the absolute value of P and outputs addition data DP as the addition result. Similarly, every time the voltage difference signal is input, the peak synthesizing circuit 10 outputs the absolute value of the correlation data MM starting from the point A (or point C) output from the matched filter 8 and the point D (or Correlation data MM starting from point B)
And outputs the addition data DM as the addition result.

Further, every time the voltage difference signal is input, the peak synthesizing circuit 9 outputs the signal A output from the matched filter 8.
The absolute value of the addition result obtained by adding the correlation data MP starting from the point (or the point C) and the correlation data MP output immediately before, and the correlation data MP starting from the point B (or the point D).
Alternatively, a configuration may be adopted in which the absolute value of the addition result obtained by adding the correlation data MP output immediately before is added to output the addition data DP of the addition result. Similarly, every time the voltage difference signal is input, the peak synthesis circuit 10 outputs the correlation data MM starting from the point A (or point C) output from the matched filter 8 and the correlation data M output immediately before.
The absolute value of the result of adding M, and point D (or point B)
And the absolute value of the addition result obtained by adding the correlation data MM starting from and the correlation data MM output immediately before,
A configuration in which the addition data DM of the addition result is output may be employed.

The peak synthesizing circuit 9 calculates the absolute value of the correlation data MP corresponding to the point A (or point C) input from the matched filter 8 and the correlation data MP corresponding to the point B (or point D). Calculate the absolute value of the point A (or C
The absolute value of the correlation data MP corresponding to
It is also possible to replace the configuration in which the larger one of the absolute values of the correlation data MP corresponding to the point (or the point D) is output as the addition data DP. Similarly, the peak synthesis circuit 1
For 0, the absolute value of the correlation data MM corresponding to the point A (or point C) input from the matched filter 8 and the absolute value of the correlation data MM corresponding to the point D (or point B) are calculated. The larger of the absolute value of the correlation data MM corresponding to the point (or the point C) and the absolute value of the correlation data MM corresponding to the point D (or the point B) is the larger of the addition data D
It is also possible to replace the configuration of outputting as M.

The difference calculator 11 sequentially outputs the peak synthesizing circuit 9
Data DP inputted from the input terminal and the peak synthesizing circuit 10
And outputs the difference signal PM to the peak detection circuit 12 as the difference. The adder 13 adds the sequentially input addition data DP and the addition data DM, and outputs the addition result TM to the peak timing circuit 14 in a time series every time the addition data DP and the addition data DM are input. ing.

The above-described matched filter 8 has a circuit configuration in which sampling is performed at a rate (or speed) similar to the chip rate of the baseband signal I and the baseband signal Q without oversampling. At this time, the voltage signal DVI sampled at the sampling point in FIG.
The relationship with the voltage difference signal DSI is DSI1 = DVI2-DVI1 DSI2 = DVI3-DVI2...

Here, DSI1, DSI2, DSI3,...
Is a voltage difference signal D sequentially output from the signal difference calculation circuit 7.
It shows the voltage value of SI. Also, here DVI1 ~
The A / D converter 46 samples the voltage at the sampling points P1b, P2b, P3b,... Shown in FIG. Is shown.

Similarly, the signal difference calculator 7 subtracts the input voltage signal DVQ from the previously sampled voltage signal DVQ as a first calculation method for obtaining the voltage difference signal DSQ, for example. Voltage difference signal D as voltage difference
SQ (change amount ΔQ) is output to the matched filter 8.
At this time, the relationship between the voltage signal DVQ sampled at the sampling point in FIG. 4A and the voltage difference signal DSQ is as follows: DSQ1 = DVQ2-DVQ1 DSQ2 = DVQ3-DVQ2.

Here, DSQ1, DSQI2, DSQ3,
.. Indicate the voltage values of the voltage difference signal DSQ sequentially output from the signal difference calculation circuit 7. DVQ1 to DVQ3
Means that the A / D converter 47 determines that the sampling point PP1b and the sampling point PP2 shown in FIG.
b, sampling points PP3b,... indicate voltage values obtained by A / D (analog / digital) conversion.

However, in order to perform highly accurate decoding, it is necessary to perform A / D conversion at a sampling rate (at least twice the oversampling) which is at least twice the chip rate of the baseband signal I and the baseband signal Q. Is desirable. When double oversampling is performed, the relationship between the voltage signal DVI sampled at the sampling point in FIG. 4C and the voltage difference signal DSI is as follows: DSI1 = DVI3−DVI1 DSI2 = DVI4−DVI2 DSI3 = DVI5− DVI3---

Here, DSI1, DSI2, DSI3, DSI
.., SI4, DSI5,... Indicate the voltage values of the voltage difference signal DSI sequentially output from the signal difference calculation circuit 7. Also,
Here, DVI1 to DVI5 correspond to the A / D converter 46.
Are the sampling points P1c, P2c, and P3 shown in FIG.
c, sampling points P4c, sampling points P5c,... indicate voltage values obtained by A / D (analog / digital) conversion.

Similarly, the signal difference calculator 7 subtracts the input voltage signal DVQ from the previously sampled voltage signal DVQ as a first calculation method for obtaining the voltage difference signal DSQ, for example. Voltage difference signal D as voltage difference
SQ (change amount ΔQ) is output to the matched filter 8.
At this time, the relationship between the voltage signal DVQ sampled at the sampling point in FIG. ing.

Here, DSQ1, DSQI2, DSQ3,
DSQI4, DSQ5,... Indicate the voltage values of the voltage difference signal DSQ sequentially output from the signal difference calculation circuit 7. The A / D converter 47 converts the DVQ1 to DVQ5 into the sampling points PP1c, PP2c, and PP3 shown in FIG.
c, sampling points PP4c, sampling points PP5c,... indicate voltage values obtained by A / D (analog / digital) conversion.

A / D converter 46 and A / D in FIG.
In converter 47, voltage signal DVI and voltage signal DV
It is possible to double the sampling rate of Q to oversampling. Hereinafter, a configuration for performing double oversampling in the spread code communication device of the present invention will be described. Referring to FIG. 9, the A / D converter 46
In the case where the A / D converter 47 performs double oversampling, the cross shift register in one embodiment will be described. FIG. 9 shows a case where the A / D converter 47 from the signal difference calculation circuit 7 performs double oversampling, and in one embodiment, the cross shift register 390 (or the cross shift register 390) used instead of the cross shift register 380 (or the cross shift register 580). Or a cross-shift register (590).

The cross shift register 390 is easily described.
(Or cross shift register 590) is replaced by cross shift register 380 (or cross shift register 58) described above.
0), but other circuit configurations include:
It is necessary to double the sampling rate of the A / D converter 46 and the A / D converter 47 for sampling the voltage signal DVI and the voltage signal DVQ, and the processing speed of the matched filter 8 and the like. That is, the matched filter 8
Is driven at twice the baseband chip rate (chip transfer rate).

The cross shift register 390 (cross shift register 590) has two shift registers 390A and 390B (or shift register 590A and 590B), like the cross shift register 380 (or cross shift register 580). It consists of a shift register. Here, in the cross shift register 390, the signal difference calculator 7 (see FIG. 1)
, A voltage difference signal DS obtained based on a double oversampled voltage signal DVI input in time series
I data string {DSI1A, DSI1B, DSI2A,
DSI2B, DSI3A, DSI3B,... Are input to the shift register 390A, and the data sequence {DSQ1A, DSQ1B, DSQ2 of the voltage difference signal DSQ obtained based on the double oversampled voltage signal DVQ.
A, DSQ2B, DSQ3A, DSQ3B,...｝ Are input to the shift register 390B. For example, as a result of the oversampling of the baseband signal I and the baseband signal Q, the voltage difference signal DSQ1
A and the voltage difference signal DSQ1B, the voltage difference signal DSQ2A, the voltage difference signal DSQ2B,.

At this time, as shown in FIG. 6, the matched filter 300 computes the correlation data MP, which is the correlation peak of the data “1”, and the matched filter unit 315 calculates the correlation peak of the data “0”. Matched filter section 365 for calculating data MM, inputted voltage difference signal DS
Two-system shift register 390A and shift register 390B for rearranging and shifting I and voltage difference signal DSQ
And a cross shift register 390. Similarly, as shown in FIG. 7, the matched filter 500 calculates the correlation data MP which is the correlation peak of the data “1”, and the correlation data MM which is the correlation peak of the data “0”. Computed matched filter section 565, input voltage difference signal DSI
And a cross shift register 590 comprising two shift registers 590A and 590B for rearranging and shifting the voltage difference signal DSQ.

At this time, in matched filter 300, matched filter section 320 generates a phase rotation corresponding to data “1” generated according to the spreading code and starting at point A or C (starting point of phase rotation). Series data,
Voltage difference signal DSI and voltage difference signal D input in time series
It is detected whether or not the SQs are the same as the spread data formed by rearranging the SQs. Similarly, in matched filter 300, matched filter section 370 generates data “0” starting from point A or point C generated according to the spreading code.
Is detected whether the data of the phase rotation sequence corresponding to the above and the spread data formed by rearranging the voltage difference signal DSI and the voltage difference signal DSQ input in time series match.

Here, the phase rotation sequence in encoding is:
It is assumed to be indicated by paragraph number 0026 and paragraph number 0027. That is, the matched filter 300 sequentially converts the voltage difference signal DSI and the voltage difference signal DSQ input from the signal difference calculator 7 into data “1” and data “1”, Rearrange data "0" into a data format corresponding to each phase rotation sequence to be encoded

That is, the data string D1 [DSI, DSQ, DSI, DS
Q, DSI, DSI, DSI, DSQ, DSI, DS
I, DSI, DSI, DSQ]. On the other hand, corresponding to the encoding of the data “0”, the data string D3 [DSQ, D
SI, DSQ, DSI, DSQ, DSQ, DSQ, DS
I, DSQ, DSQ, DSQ, DSQ, DSI]. The data sequence D1 described above indicates a phase rotation sequence indicating data “1” starting from the points A and C. Similarly, the data sequence D3 indicates a phase rotation sequence indicating data “0” starting from the points A and C.

In FIG. 6, cross shift register 390
Shift register 390A and shift register 3
90B inputs the input data sequence in time series,
Shift rightward sequentially. Here, the data string is input to the shift register 390A and the shift register 390B from the left end of the data in the string. # 1 in FIG.
Lines # 2 and # 2 show the flow of the data shift operation in shift register 390A and shift register 390B, respectively. As can be seen from the line segment # 1 and the line segment # 2, the shift register 390A and the shift register 390B are configured such that the connection of the constituent registers crosses at a predetermined register position so that the data string can be rearranged. ing. That is, the configuration of the shift register 390A and the shift register 390B is configured by the register connection shown in FIG. FIG. 9 is a block diagram showing a configuration of the cross shift register 390 of FIG.

In FIG. 9, shift register 390A
Is composed of 25 registers 400A to 412B, and inputs data of a double oversampling data string input from the signal difference calculator 7, and sequentially performs a shift operation. At this time, the spread code has 13 chips, and is input with double oversampling.
(Number of chips of spread code) It is composed of the number of registers. The shift register 390A is composed of 25 registers because the 25th register, that is, the register 462B, obtains the data corresponding to the 13th chip of the spread code for performing the correlation value detection processing. This is because there is no need to provide the 26th register.

Similarly, in FIG. 9, shift register 3
90B is 25 of registers 450A to 462B.
And a shift operation is performed by inputting the data of the input data string with double oversampling. At this time, the spread code has 13 chips and is input with double oversampling, and the shift register 390B has a register number of 25 (the number of chips of the spread code). The shift register 390B is composed of 25 registers because the 25th register, that is, the register 462B, obtains the data corresponding to the 13th chip of the spread code for performing the correlation value detection processing. This is because there is no need to provide the 26th register.

The shift register 390A and the shift register 390B have an output terminal of the register 400A connected to an input terminal of the register 451B, and a register 450A.
Is connected to the input terminal of the register 401B,
The data shift processing flows are configured to intersect. Similarly, the shift register 390A and the shift register 390B have an output terminal of the register 404A connected to an input terminal of the register 455B, and
4A is connected to the input terminal of the register 405B, the output terminal of the register 405A is connected to the input terminal of the register of the register 456B, the output terminal of the register 455A is connected to the input terminal of the register of the register 406B, and the register 408A Output terminal is register 459B
Is connected to the input terminal of the register 458A, the output terminal of the register 458A is connected to the input terminal of the register of the register 409B, and the output terminal of the register 459A is connected to the register 410.
B is connected to the input terminal of the register 409A.
Is connected to the input terminal of the register of the register 460B, and the output terminal of the register 460A is connected to the register 41
1B is connected to the input terminal of the register 410B.
A output terminal is connected to the input terminal of the register of the register 461B, and the output terminal of the register 461A is connected to the register 4
12B is connected to the input terminal of the register 41B.
The output terminal of 1A is connected to the input terminal of the register of the register 462B, so that the data shift processing flows cross each other.

As a result, the matched filter 300
Voltage difference signal DSI and voltage difference signal D input in time series
SQ is a data string stored in the shift register 390A, that is, data input in order from the left end (reverse relationship to the data shift direction in the shift register 390A shown in FIGS. 6 and 9). [DSI1A, DSI1B, DSQ2A, DSQ2B,
DSI3A, DSI3B, DSQ4A, DSQ4B, D
SI5A, DSI5B, DSI6A, DSI6B, DS
I7A, DSI7B, DSQ8A, DSQ8B, DSI
9A, DSI9B, DSI10A, DSI10B, DS
I11A, DSI11B, DSI12A, DSI12
B, DSQ13A, DSQ13B]. For example, the voltage difference signal DSI1 which is the leftmost bit of the data string
A corresponds to the bit stored in register 412B.

Similarly, the matched filter 300 includes a voltage difference signal DSI and a voltage difference signal DSQ input in time series.
As a data string stored in the shift register 390B, that is, data sequentially input from the left end (reverse relationship to the data shift direction in the shift register 390B shown in FIGS. 6 and 9), for example, the shift register 390A At the same timing as the data sequence [DSQ1A, DSQ1B, DSI2A, DSI2B,
DSQ3A, DSQ3B, DSI4A, DSI4B, D
SQ5A, DSQ5B, DSQ6A, DSQ6B, DS
Q7A, DSQ7B, DSI8A, DSI8B, DSQ
9A, DSQ9B, DSQ10A, DSQ10B, DS
Q11A, DSQ11B, DSQ12A, DSQ12
B, DSI 13A, DSI 13B]. For example, the voltage difference signal DSQ1 which is the leftmost bit of the data string
A corresponds to the bit stored in register 462B. At this time, the voltage difference signal DSQ is input to the register 400B in time series, and the voltage difference signal DSI is input to the register 450B in time series.

Also, in FIG. 6, multipliers 301 to 313 are respectively a register 412B, a register 411B, and a register 410 in shift register 390A.
B,..., Are connected to the registers 402B, 401B, and 400B, and multiply the values output (stored) by the registers under the control of the controller 1 with “−1” or “1” as a code. And the multiplier 30
1 to the multiplier 313 each add the result of the multiplication to the correlation adder 3
15 is output. Similarly, multipliers 351 to 363
Are the registers 4 in the shift register 390B, respectively.
62B, register 461B, register 460B,...
Register 452B, Register 451B, Register 450
B, and multiplies the value output (stored) from each register by the control of the controller 1 using “−1” or “1” as a code. Then, the multipliers 351 to 363 output the multiplied results to the correlation adder 365.

As described above, the matched filter section 320 in the matched filter 300 multiplies each voltage difference signal by the code indicating the rotation direction of the phase rotation sequence corresponding to the data sequence D1, and generates the data sequence. Add data.
That is, the code {−1, −1, 1, 1, −− of the phase rotation sequence used for encoding the data “1” starting from the point A.
1,1, −1, −1,1, −1,1, −1,1} are converted by the multipliers 301 to 313 into a data string D1 [DS
I, DSQ, DSI, DSQ, DSI, DSI, DS
I, DSQ, DSI, DSI, DSI, DSI, DS
Q] is multiplied to the corresponding chip.

At this time, the data sequence D1 is stored in the register 412B and the register 41 in the shift register 380A.
1B, register 410B, register 409B, register 408B, register 407B, register 406B, register 405B, register 404B, register 403B,
Register 402B, Register 401B, Register 400
B, the shifted voltage difference signal DSI and the shifted voltage difference signal DSQ are respectively denoted by [DSI1A, DSQ2A, DSI3A,
DSQ4A, DSI5A, DSI6A, DSI7A, D
SQ8A, DSI9A, DSI10A, DSI11A,
DSI12A, DSQ13A].

Then, the multipliers 301 to 313
Data sequence (spread data) resulting from multiplication of the above code
[-DSI1A, -DSQ2A, DSI3A, DSQ4
A, -DSI5A, DSI6A, -DSI7A, -DS
Q8A, DSI9A, -DSI10A, DSI11A,
−DSI12A, DSQ13A], that is, data of the voltage difference signal corresponding to the polarity of the phase rotation sequence in the rotation direction, to the correlation adder 315. Thereby, the correlation adder 3
15 is a data string (spread data) [-DSI1A, -D
SQ2A, DSI3A, DSQ4A, -DSI5A, D
SI6A, -DSI7A, -DSQ8A, DSI9A,
-DSI10A, DSI11A, -DSI12A, DS
Q13A] is added, and the result of the addition is output as correlation data MP of a positive value peak of matching (correlation).

Similarly, regarding the decoding of the encoding of the data “1” starting from the point C, the data string D
1 that is the same as the polarity of the code of the phase rotation sequence starting from point A multiplied by each element of ｛−1, −1, 1, 1, 1,
−1,1, −1, −1,1, −1,1, −1,1},
Register 412B, Register 411B, Register 410
B, register 409B, register 408B, register 4
07B, the register 406B, the register 405B, the register 404B, the register 403B, the register 402B, the register 401B, and the data string D1 stored in the register 400B are respectively multiplied by the multipliers 301 to 313 [− DSI1A, -DSQ2
A, DSI3A, DSQ4A, -DSI5A, DSI6
A, -DSI7A, -DSQ8A, DSI9A, -DS
I10A, DSI11A, -DSI12A, DSQ13
A] is output to the correlation adder 315.

As a result, the correlation adder 315 outputs the data string [-DSI1A, -DSQ2A, D
SI3A, DSQ4A, -DSI5A, DSI6A,-
DSI7A, -DSQ8A, DSI9A, -DSI10
A, DSI11A, -DSI12A, DSQ13A] is output as correlation data MP of the peak of the negative value of the matching (correlation).

Further, matched filter section 370 in matched filter 300 multiplies each voltage difference signal by a code indicating the rotation direction of the phase rotation sequence corresponding to data sequence D3, and converts the data of the data sequence. to add. That is, the codes {−1, −1, 1, 1, −1, −1, −1, −1, 1, 1, −1, of the phase rotation sequence used for encoding the data “0” starting from the point A.
1, −1, −1,1, −1,1, −1,1} are subjected to a data sequence D3 [DSQ,
DSI, DSQ, DSI, DSQ, DSQ, DSQ, D
Each of the chips corresponding to SI, DSQ, DSQ, DSQ, DSQ, DSI} is multiplied.

At this time, the data string D3 is stored in the register 46.
2B, register 461B, register 460B, register 459B, register 458B, register 457B, register 456B, register 455B, register 454B,
Register 453B, Register 452B, Register 451
B and the register 450B respectively provide the shifted voltage difference signal DSI and the shifted voltage difference signal DSQ in [DSQ1A, DSI
2A, DSQ3A, DSI4A, DSQ5A, DSQ6
A, DSQ7A, DSI8A, DSQ9A, DSQ10
A, DSQ11A, DSQ12A, DSI13A].

The multipliers 351 to 363 are
Data sequence (spread data) resulting from multiplication of the above code
[-DSQ1A, -DSI2A, DSQ3A, DSI4
A, -DSQ5A, DSQ6A, -DSQ7A, -DS
I8A, DSQ9A, -DSQ10A, DSQ11A,
−DSQ12A, DSI13A], that is, data of the voltage difference signal corresponding to the polarity in the rotation direction of the phase rotation sequence to the correlation adder 365. Thereby, the correlation adder 3
65 is a data string (spread data) [-DSQ1A, -D
SI2A, DSQ3A, DSI4A, -DSQ5A, D
SQ6A, -DSQ7A, -DSI8A, DSQ9A,
-DSQ10A, DSQ11A, -DSQ12A, DS
I13A], and sums the result of the addition to obtain the correlation data M of the positive value peak of matching (correlation).
Output as P.

As for the decoding of the coding starting from the point C, the same code {−1} as the code of the phase rotation sequence starting from the point A obtained by multiplying each element of the data sequence D3 in the above. , -1,1,1, -1,1, -1, -1, -1,
1, −1, 1, −1, 1} are registered as registers 462B, 461B, 460B, 459B,
Register 458B, Register 457B, Register 456
B, register 455B, register 454B, register 4
53B, the register 452B, the register 451B, and the data string D3 stored in the register 450B are multiplied by the multipliers 351 to 363, and the multiplied data strings [-DSQ1A, -DSI2A, DSQ3A, D
SI4A, -DSQ5A, DSQ6A, -DSQ7A,
-DSI8A, DSQ9A, -DSQ10A, DSQ1
1A, -DSQ12A, DSI13A] is the correlation adder 3
65 is output.

Accordingly, the correlation adder 365 converts the data string of the voltage difference signal into [-DSQ1A, -DSI2A,
DSQ3A, DSI4A, -DSQ5A, DSQ6A,
-DSQ7A, -DSI8A, DSQ9A, -DSQ1
0A, DSQ11A, -DSQ12A, DSI13A]
to add. As a result, the addition result is matched (correlated).
Is output as the correlation data MM of the peak of the negative value of.

On the other hand, in matched filter 500 in FIG. 7, matched filter section 520 generates phase rotation sequence data corresponding to data “1” originating at point B or D, generated according to the spreading code, and It is detected whether or not the voltage difference signal DSI and the voltage difference signal DSQ input in time series match the spread data formed by rearranging.
Similarly, in matched filter 500, matched filter section 570 receives the phase rotation sequence data corresponding to data “0” originating from point D or point B, generated in accordance with the spreading code, and time-series input. Voltage difference signal DSI
Then, it is detected whether or not the spread data formed by rearranging the voltage difference signal DSQ match.

Here, the phase rotation sequence in encoding is:
It is assumed to be indicated by paragraph number 0026 and paragraph number 0027. That is, like the matched filter 300, the matched filter 500 sequentially converts the voltage difference signal DSI and the voltage difference signal DSQ input from the signal difference calculator 7 into, for example, The used data "1" and data "0" are rearranged into data formats corresponding to respective phase rotation sequences for encoding.

That is, in response to the encoding of the data “1”, the data string D2 [DSQ, DSI, DSQ, DS
I, DSQ, DSQ, DSQ, DSI, DSQ, DS
Q, DSQ, DSQ, DSI]. On the other hand, corresponding to the encoding of the data “0”, the data string D4 [DSI, D
SQ, DSI, DSQ, DSI, DSI, DSI, DS
Q, DSI, DSI, DSI, DSI, DSQ]. The data sequence D2 described above indicates a phase rotation sequence indicating data “1” starting from the points B and D. Similarly, the data sequence D4 indicates a phase rotation sequence indicating data “0” starting from the points D and B.

In FIG. 7, cross shift register 590
Shift register 590A and shift register 5
90B inputs the input data sequence in time series,
Shift rightward sequentially. Here, the data sequence is input to the shift register 590A and the shift register 590B from the left end of the data in the sequence. Lines # 3 and # 4 in FIG. 6 indicate the flow of the data shift operation in shift register 590A and shift register 590B, respectively. As can be seen from the line segments # 3 and # 4, the shift register 590A and the shift register 590B are configured such that the connection of the constituent registers crosses at a predetermined register position so that the data string can be rearranged. ing.

That is, the structure of shift register 590A and shift register 590B is the same as that of shift register 390.
Like the A and the shift register 390B, it is configured by the register connection shown in FIG. FIG. 9 is a block diagram showing a configuration of the cross shift register 590 of FIG. The structure of the shift register 590A and the shift register 590B is the same as that of the shift register 390A and the shift register 390.
The description is omitted because it is the same as B. At this time, the voltage difference signal DSI is input to the register 400B in time series, and the voltage difference signal DSQ is input to the register 450B in time series.

In FIG. 9, shift register 590A
Is composed of 25 registers 400B to 412B, and inputs double oversampling data train data input from the signal difference calculator 7 and sequentially performs a shift operation. At this time, the spread code is 13 chips, and is input by double oversampling, and the shift register 590A
It is composed of (number of chips of spreading code × multiple of oversampling−1) number of registers. Shift register 5
90A is composed of 25 registers.
This is because the data corresponding to the thirteenth chip of the spread code for performing the correlation value detection processing is obtained in the twenty-fifth register, that is, the register 412B, so that there is no need to provide the twenty-sixth register.

Similarly, in FIG.
90B is 25 of registers 450B to 462B.
And a shift operation is performed by inputting the data of the input data string with double oversampling. At this time, the spread code is 13 chips and is input with double oversampling, and the shift register 590B is configured with 25 (number of spread code chips x multiple of oversampling-1) registers. . The shift register 590B is composed of 25 registers because the 25th register, that is, the register 462B, obtains the data corresponding to the 13th chip of the spread code for performing the correlation value detection processing. This is because there is no need to provide the 26th register.

With the above configuration, the matched filter 50
0 indicates that the voltage difference signal DSI and the voltage difference signal DSQ input in time series are data strings stored in the shift register 590A, that is, data input in order from the left end (shifts shown in FIGS. 7 and 9). The relationship opposite to the data shift direction in the register 580A), for example, the data string [DSI1A, DSQ2A, DSI3A, DSQ4
A, DSI5A, DSI6A, DSI7A, DSQ8
A, DSI9A, DSI10A, DSI11A, DSI
12A, DSQ13A]. For example, the voltage difference signal DSI1A, which is the leftmost bit of the data string, corresponds to the bit stored in the register 412B.

Similarly, the matched filter 500 includes a voltage difference signal DSI and a voltage difference signal DSQ input in time series.
As a data string stored in the shift register 590B, that is, data sequentially input from the left end (a relationship opposite to the data shift direction in the shift register 590B shown in FIGS. 7 and 9), for example, the shift register 590A At the same timing as the data sequence [DSQ1A, DSI2A, DSQ3A, DSI4A,
DSQ5A, DSQ6A, DSQ7A, DSI8A, D
SQ9A, DSQ10A, DSQ11A, DSQ12
A, DSI 13A]. For example, the voltage difference signal DSQ1A, which is the leftmost bit of the data string, corresponds to the bit stored in the register 462B.

In FIG. 7, multipliers 501 to 513 are respectively a register 412B, a register 411B and a register 410 in a shift register 590A.
B,..., Are connected to the registers 402B, 401B, and 400B, and multiply the values output (stored) by the registers under the control of the controller 1 with “−1” or “1” as a code. And a multiplier 50
1 to a multiplier 513 each add the result of the multiplication to the correlation adder 5
15 is output. Similarly, multipliers 551 to 563
Are the registers 4 in the shift register 590B, respectively.
62B, register 461B, register 460B,...
Register 452B, Register 451B, Register 450
B, and multiplies the value output (stored) from each register by the control of the controller 1 using “−1” or “1” as a code. Then, the multipliers 551 to 563 output the multiplied results to the correlation adder 565.

At this time, in matched filter section 520, the codes ｛−1, 1, 1, −1, −1, −1 of the phase rotation sequence used for encoding “1” data starting from point B
1, −1,1,1, −1,1, −1, −1} are subjected to data sequence D2 [DSQ,
DSI, DSQ, DSI, DSQ, DSQ, DSQ, D
SI, DSQ, DSQ, DSQ, DSQ, DSI].

At this time, the data string D2 is stored in the register 41.
2B, register 101B, register 410B, register 409B, register 408B, register 407B, register 406B, register 405B, register 404B,
Register 403B, Register 402B, Register 401
B, the shifted voltage difference signal DSI and the shifted voltage difference signal DSQ are respectively stored in the register 400B [DSQ1A,
DSI2A, DSQ3A, DSI4A, DSQ5A, D
SQ6A, DSQ7A, DSI8A, DSQ9A, DS
Q10A, DSQ11A, DSQ12A, DSI13
A].

Then, the multipliers 501 to 513 are
Data sequence (spread data) resulting from multiplication of the above code
[-DSQ1A, DSI2A, DSQ3A, -DSI4
A, -DSQ5A, DSQ6A, -DSQ7A, DSI
8A, DSQ9A, -DSQ10A, DSQ11A,-
DSQ12A, -DSI13A], that is, data of the voltage difference signal corresponding to the polarity of the phase rotation sequence in the rotation direction, to correlation adder 515. Thereby, the correlation adder 5
15 is a data string (spread data) [-DSQ1A, DS
I2A, DSQ3A, -DSI4A, -DSQ5A, D
SQ6A, -DSQ7A, DSI8A, DSQ9A,-
DSQ10A, DSQ11A, -DSQ12A, -DS
I13A] is added, and the result of the addition is output as correlation data MP of a positive peak of matching (correlation).

Similarly, in matched filter section 520, with respect to the decoding of the encoding of the data of "1" starting from point D, point B obtained by multiplying each element of data string D2 in the above manner ｛-1,1,1, −1, −1,1, −1,1,1 similar to the phase rotation sequence code
1, −1,1, −1, −1} are stored in the registers 412B, 411B, 410B, and 409.
B, register 408B, register 407B, register 4
06B, the register 405B, the register 404B, the register 403B, the register 402B, the register 401B, and the data string D2 stored in the register 400B are multiplied by the multipliers 501 to 513 by the data strings [-DSQ1A, DSI2A, respectively. , DSQ3A,-
DSI4A, -DSQ5A, DSQ6A, -DSQ7
A, DSI8A, DSQ9A, -DSQ10A, DSQ
11A, -DSQ12A, -DSI13A] are output to the correlation adder 565.

As a result, the correlation adder 565, the data sequence of the voltage difference signal [-DSQ1A, DSI2A, DSQ
3A, -DSI4A, -DSQ5A, DSQ6A, -D
SQ7A, DSI8A, DSQ9A, -DSQ10A,
DSQ11A, -DSQ12A, -DSI13A] is output as correlation data MP of a negative peak of matching (correlation).

On the other hand, in matched filter section 570, the codes {−1, 1, 1, −1, −1, −1, −1, 1, −1, −1 of the phase rotation sequence used for encoding “0” data starting from point D.
1, −1, 1, 1, −1, 1, −1, −1} are converted into a data sequence D4 [DSI,
DSQ, DSI, DSQ, DSI, DSI, DSI, D
SQ, DSI, DSI, DSI, DSI. DSQ] to the corresponding chip.

At this time, the data string D4 is stored in the register 46.
2B, register 461B, register 460B, register 459B, register 458B, register 457B, register 456B, register 455B, register 454B,
Register 453B, Register 452B, Register 451
B and the register 450B store the shifted voltage difference signal DSI and the shifted voltage difference signal DSQ in [DSI1A, DSQ
2A, DSI3A, DSQ4A, DSI5A, DSI6
A, DSI7A, DSQ8A, DSI9A, DSI10
A, DSI11A, DSI12A, DSQ13A].

Then, the multipliers 551 to 563 are
Data sequence (spread data) resulting from multiplication of the above code
[-DSI1A, DSQ2A, DSI3A, -DSQ4
A, -DSI5A, DSI6A, -DSI7A, DSQ
8A, DSI9A, -DSI10A, DSI11A,-
DSI12A, -DSQ13A], that is, data of the voltage difference signal corresponding to the polarity of the phase rotation sequence in the rotation direction, to the correlation adder 565. Thereby, the correlation adder 5
65 is a data string (spread data) [-DSI1A, DS
Q2A, DSI3A, -DSQ4A, -DSI5A, D
SI6A, -DSI7A, DSQ8A, DSI9A,-
DSI10A, DSI11A, -DSI12A, -DS
Q13A], and the result of the addition is output as correlation data MM of a positive peak of matching (correlation).

Similarly, with respect to the decoding of the encoding starting from the point B, the same code as the code of the phase rotation sequence starting from the point D obtained by multiplying each element of the data sequence D4 in the above manner. 1,1,1, -1, -1, -1,1, -1,1,1,
1, -1, 1, -1, -1} are stored in the registers 462B, 461B, 460B, and 459.
B, register 458B, register 457B, register 4
56B, register 455B, register 454B, register 453B, register 452B, register 451B, and register 450B are multiplied by data multipliers 551 to 563 by multipliers 551 to 563, and the multiplied data stream [-DSI1A , DSQ2A, DSI3
A, -DSQ4A, -DSI5A, DSI6A, -DS
I7A, DSQ8A, DSI9A, -DSI10A, D
SI11A, -DSI12A, -DSQ13A] are output to the correlation adder 565.

As a result, the correlation adder 565 outputs the data sequence [-DSI1A, DSQ2A, DS
I3A, -DSQ4A, -DSI5A, DSI6A,-
DSI7A, DSQ8A, DSI9A, -DSI10
A, DSI11A, -DSI12A, -DSQ13A]
Is output as the correlation data MM of the peak of the negative value of the matching (correlation).

In the decoding as described above, the matched filter 8 operates in the phase rotation sequence using the data “1” and the data “0” in the transmission data as in the case where the point A is the starting point. When the starting point is point B, point C, and point D, the timing (corresponding to the number multiplied by oversampling if oversampling) is transferred in time series for matching (correlation) with the phase rotation sequence. The correlation data MP and the correlation data MM are sequentially output to the peak synthesis circuit 9 and the peak configuration circuit 10, respectively.

At this time, as described above, the correlation data MP and the correlation data MM each have the same sign and polarity as the phase rotation sequence (point A and point B in the case of data “1”), or have no relation at all. In the case of the opposite polarity (the C point reference and the D point reference in the case of the data “1”), the intensity of the correlation signal of the maximum peak is obtained. Conversely, if the polarities of the codes are different and do not match, the addition results are averaged, and the peak of the correlation value decreases. That is, the matched filter 8
The points A to D corresponding to data "1" and data "0" are sequentially added to the voltage difference signal input from the signal difference calculator 7 in time series each time a new voltage difference signal is input. The correlation value obtained by multiplying and adding the sign of the phase rotation sequence based on the reference is used as the correlation data MP and the correlation data MM, respectively, as the peak synthesis circuit 9 and the peak synthesis circuit 1.
Output to 0.

The shift register 390A and the shift register 390B (or the shift register 590A and the shift register 59) in the matched filter 8 described above.
0B), the intersection of the input and output signal connections is controlled by the program of the microcontroller 1 as necessary.
For example, when the data combination of the data sequence D1 to data sequence D4 of the phase rotation sequence, that is, when the spreading code is changed, it is possible to change so as to intersect at any register part. Similarly, the multiplier 301 to the multiplier 313 and the multiplier 351 to the multiplier 363 (or the multiplier 501 to the multiplier 513 and the multiplier 551 to the multiplier 561)
The code of the phase rotation sequence to be multiplied by the phase rotation sequence in 3) is also controlled by the program of the microcontroller 1, if necessary, for example, the data sequence D1 of the phase rotation sequence.
The polarity setting can be changed when the combination of the data in the data string D4, that is, when the spreading code is changed, or the like.

The data processing of the potential difference signal DSI and the potential difference signal DSQ when double oversampling is performed using the cross shift register 390 (or the cross shift register 590) has been described.
The circuit configuration that realizes (n is a natural number) times data processing is as follows:
The configuration can be made by multiplying the register configuration when oversampling is not performed by n times. By increasing the multiple of the frequency of the oversampling, the accuracy of decoding the spread data in the despreading increases. When n-times oversampling is performed, the peak synthesis circuit 9, the peak synthesis circuit 10, the difference calculation circuit 11, and the peak detection circuit 1
2 requires n times the data processing speed.

Hereinafter, similarly to the case where oversampling is not performed, the peak synthesizing circuit 9 uses the points A (or C) and B (or D) sequentially input from the matched filter 8 as starting points. The absolute values of the correlation data MP are taken, all of them are added, and the sum data DP is output to the difference calculator 11. Similarly, the peak synthesizing circuit 10 outputs the point A (or C
Point), correlation data MM starting from point D (or point B)
, And add them all to output the added data DM to the difference calculator 11.

At this time, every time the voltage difference signal is input, the peak synthesizing circuit 9 outputs the absolute value of the correlation data MP starting from the point A (or point C) output from the matched filter 8 and the absolute value of B Correlation data M starting from point (or point D)
It adds the absolute value of P and outputs addition data DP as the addition result. Similarly, each time the voltage difference signal is input, the peak synthesis circuit 10 sets the absolute value of the correlation data MM based on the point A (or point C) output from the matched filter 8 and the point D (or Correlation data MM based on point B)
And outputs the addition data DM as the addition result.

Each time the voltage difference signal is input, the peak synthesizing circuit 9 outputs the signal A output from the matched filter 8.
The absolute value of the addition result obtained by adding the correlation data MP starting from the point (or the point C) and the correlation data MP output immediately before, and the correlation data MP based on the point B (or the point D).
Alternatively, a configuration may be adopted in which the absolute value of the addition result obtained by adding the correlation data MP output immediately before is added to output the addition data DP of the addition result. Similarly, every time the voltage difference signal is input from the signal difference calculator 7, the peak synthesis circuit 10 outputs the correlation data MM starting from the point A (or point C) output from the matched filter 8 and the immediately preceding correlation data MM. An absolute value of an addition result obtained by adding the output correlation data MM,
The correlation data MM starting from the point D (or point B) and the absolute value of the addition result obtained by adding the correlation data MM output immediately before are added to output the addition data DM of the addition result. Can also.

The peak synthesizing circuit 9 calculates the absolute value of the correlation data MP corresponding to the point A (or point C) input from the matched filter 8 and the correlation data MP corresponding to the point B (or point D). Calculate the absolute value of the point A (or C
The absolute value of the correlation data MP corresponding to
It is also possible to replace the configuration in which the larger one of the absolute values of the correlation data MP corresponding to the point (or the point D) is output as the addition data DP. Similarly, the peak synthesis circuit 1
For 0, the absolute value of the correlation data MM corresponding to the point A (or point C) input from the matched filter 8 and the absolute value of the correlation data MM corresponding to the point D (or point B) are calculated. The larger of the absolute value of the correlation data MM corresponding to the point (or the point C) and the absolute value of the correlation data MM corresponding to the point D (or the point B) is the larger of the addition data D
It is also possible to replace the configuration of outputting as M.

The difference calculator 11 sequentially outputs the peak
Data DP inputted from the input terminal and the peak synthesizing circuit 10
And outputs the difference signal PM to the peak detection circuit 12 as the difference. The adder 13 adds the sequentially input addition data DP and the addition data DM, and outputs the addition result TM to the peak timing circuit 14 in a time series every time the addition data DP and the addition data DM are input. ing. The above-described peak synthesis circuit 9, peak synthesis circuit 10, and difference calculation circuit 11
For data processing with double oversampling,
As a matter of course, it operates at twice the speed as compared with the case where oversampling is not performed.

Until now, the cross shift registers 380, 3
90 and cross shift register 580590, 2
Potential difference signal D when double oversampling is performed
Although the data processing of the SI and the potential difference signal DSQ has been described, a circuit configuration that realizes p (p is a natural number) times data processing can be configured by multiplying the register configuration when oversampling is not performed by p. . By increasing the multiple of the frequency of the oversampling, the accuracy of decoding the spread data in the despreading increases. When the p-times oversampling is performed, the peak synthesis circuit 9, the peak synthesis circuit 10, the difference calculation circuit 11, and the peak detection circuit 12 require a p-times data processing speed.

The peak timing circuit 14 is provided with the difference calculator 1
1 to the peak detection circuit 12, which determines whether the input difference signal PM data is either "0" or "1".
A peak detection signal G for controlling the timing of data determination processing is output. Here, the peak timing circuit 14
Has the configuration shown in FIG. FIG. 10 is a block diagram showing a configuration of the peak timing circuit 14 in FIG. In FIG. 10, a register row RG includes n registers R1 to Rn (SRAM: storage element such as a static random access memory).

N is a number obtained by multiplying the number of chips of the spreading code by a number corresponding to oversampling. For example, when the number of chips of the spread code is 13, and as described above, at the time of input to the peak timing circuit 14, the oversampling is performed at twice the predetermined chip rate of the baseband signal I and the baseband signal Q. If so, n = 13 × 2 = 26. Here, based on the configuration of FIG. 8 described above, when oversampling is not performed, the register row RG is configured by 13 registers. Further, in the case where double oversampling is performed based on the configuration in FIG. 9 described above, the register row RG includes 26 registers.

The selector 250 is provided with a counter 2
According to the control signal Sn output from the register 51, any one of the registers R1 to Rn in the register row RG is selected. That is, the circulation counter 251 counts from 0 to n-1. For example, the control signal S of the circulation counter 51
If the value of n is "2", the selector 250 selects the register R3. Further, the circulation counter 251 outputs a count value indicating how many times the counting from 0 to n-1 has been performed as a control signal Sm. The addition circuit 252 includes the selector 25
When the control signal Sn is "0", the stored data is read out from the register R1, and the data and the addition result TM input from the adder 13 are added to the register R1. The signal is output via the averaging circuit 253 and stored in the register R1. The timing at which the addition result TM is input from the adder 13 coincides with the counting timing of the circulation counter 251. When the next addition result TM is input, the circulation counter 251 performs a one-time counting process, and The value of Sn becomes "1", and the selector 250 selects the register R2. And the addition circuit 2
52 adds the input counting result TM and the data read from the register R2, outputs the result to the register R1 via the averaging circuit 253, and stores the result in the register R1.

As described above, at the timing when the counting result TM is input in time series, the counting circuit 25
2 reads out data stored in the register selected by the selector 250 by the control signal Sn, adds the data to the input addition result TM, and returns the data of the addition result to the original register. I do. And
The adder 13 performs the cumulative addition process for each register described above every m (m is an integer of 1 or more) times based on the following equation. Cumulative value Tj = (previous cumulative value Tj + (TM0 + TM1 + ...
+ TMm-1)) / 2 The accumulated value Tj is data stored in each register, and has a relationship of 0 ≦ j ≦ n. That is, the accumulated value T1
Are stored in the register R1, the cumulative value T2 is stored in the register R2,..., The cumulative value Tn is stored in the register Rn.
Is stored in When the spread code communication apparatus starts the receiving process, the registers R1 to Rn are in a reset state, and "0" is stored.

In the above formula, TM0, TM1,..., TMm-
1 is a numerical value indicating the addition result TM input from the adder 13 to the addition circuit 252. Here, m is a numerical value indicating how many times the circulation counter 251 has counted from 0 to n-1. That is, the addition circuit 252 operates in the register R1
The number of times the process of adding the data read from each register and the addition result TM input in time series to each of the registers Rn and returning the data of the addition result to the same register is performed. It is a numerical value shown. The peak timing circuit 14 is provided from the difference calculator 11 to the peak detection circuit 12.
In addition, the determination timing of the difference signal PM input in time series is corrected. However, if the peak of each chip is determined in one cycle of the spread data, an accurate correction timing signal G cannot be obtained. Then, the peak is detected using the integration effect.

For example, if m is set to "3" and the control signal Sm output from the circulation counter 251 becomes "2", the process of adding the addition result TM to each register of the register row RG is the third time. Therefore, for example, if the control signal Sm is "2" and the control signal Sn is "0", the selector 250 selects the register R1, the addition circuit 252 reads out the data of the register R1, and adds the input data to this register. The result is added to the result TM, and the added data is output to the register R1 via the averaging circuit 253. At this time, since the control signal Sm is “2”, the averaging circuit 253
The added data input from the adding circuit 252 is averaged as １ ／, and is output to the register R1 as a cumulative value T1. When the control signal Sm is other than "2", the averaging circuit 253 outputs the input added data to the register R1 in the same state, that is, without halving. Then, the register R1 stores the input cumulative value T1. Then, the detection circuit 254 stores the accumulated value T1 and the value “0” of the control signal Sn of the counter.

Next, when the addition result TM is input from the adder 13, the circulation counter 251 performs one counting and outputs the control signal Sn as "1". Then, the selector 250 selects the register R2 because the control signal Sn is "1". As a result, the addition circuit 252 stores the register R
2 is read out, added to this data and the added result TM, and the added data is averaged by the averaging circuit 25.
3 to the register R2. At this time, since the control signal Sm is “2”, the averaging circuit 253 reduces the added data input from the addition circuit 252 by １ ／.
And outputs it to the register R2 as the accumulated value T2. Then, the register R2 stores the input cumulative value T2. Then, the detection circuit 254 calculates the accumulated value T2
Is compared with the stored cumulative value T1 to determine which is greater. At this time, the detection circuit 254
Determines that the cumulative value T2 is greater than the cumulative value T1, deletes the cumulative value T1, and resets the cumulative value T2 and the counter control signal S
The value “1” of n is stored.

Similarly, a cumulative value of the addition result TM input in time series from the adder 13 is sequentially calculated for a register selected by the selector 250 according to the value of the control signal Sn, and an averaging circuit is obtained. A cumulative value is calculated as １ ／ by 253 and stored in the corresponding register. When the detection circuit 254 determines that the newly input accumulated value is larger than the accumulated value stored as the maximum value so far, the detection circuit 254 deletes the accumulated value stored as the maximum value so far, and newly deletes the accumulated value. The value of the control signal Sn of the counter indicating the input cumulative value and the register in which the cumulative value is stored is stored. When the circulation counter 251 outputs the control signal Sn having the value of “n−1”, the detection circuit 254 supplies the accumulated values T1, T2,.
The maximum value of Tn is stored.

Thus, the peak timing circuit 14
Can detect which of the chips in the spread code for one cycle is the timing for detecting data. Then, when the next addition result TM is input, the timing correction signal G is output to the peak detection circuit 12. The timing correction signal G indicates which of the registers R1 to Rn has the maximum peak, that is, the register R
Numerical values of the control signal Sn indicating which one of the registers 1 to Rn has the largest accumulated value are included. At this time, the circulation counter 251 performs one count, the control signal Sn becomes “0”, and the control signal Sm similarly becomes “0”.
Becomes Then, the peak timing circuit 14 continuously performs the process of detecting the peak timing for outputting the timing correction signal G described above.

After the timing correction signal G is input from the peak timing circuit 14, the peak detection circuit 12 outputs the control signal Sn output from the circulation counter 251 of the peak timing circuit 14 and the control signal Sn included in the timing correction signal G. When the numerical values are equal to each other, a comparison is made between the difference signal PM input from the difference calculator 11 and a judgment level set internally in advance. Thereby, the peak detection circuit 12
In the matched filter 8,
Even if it is not known where the correlation peak (data detection position) of the voltage difference signal input in time series is output,
Even if the frequencies on the transmitting side and the receiving side are slightly shifted, the timing correction is performed once every m times of the detection of the transmission data, so that the maximum correlation peak of the correlation data or the correlation data DM is output. It is possible to determine whether the difference signal PM is data “0” or data “1” at a highly accurate determination timing estimated as follows.

At this time, when the peak detection circuit 12 determines that the difference signal PM is larger than the determination level, the correlation data DP for “1” output from the peak synthesis circuit 9 is obtained.
Is larger than the correlation data DM for “0” output from the peak synthesizing circuit 10, and outputs the determination data of “1” (bit data of transmission data) to the Viterbi decoder 15. On the other hand, when the peak detection circuit 12 determines that the difference signal PM is smaller than the determination level, the correlation data DM for “0” output from the peak synthesis circuit 10 is:
Since the correlation data DP for “1” output from the peak synthesis circuit 9 is larger than the correlation data DP for “1”, the determination data of “0” (bit data of the serial data DC) is transmitted to the Viterbi decoder 15.
Output to Note that in the peak detection circuit 12,
The method of determining “0” or “1” and outputting it to the Viterbi decoder 15 is simple called “hard decision”, but in order to further enhance the error correction capability, the output of the peak detection circuit 12 is represented by a multi-bit value. A soft decision method may be used.

The Viterbi decoder 15 uses a Viterbi decoding method for selecting a trellis path that minimizes the Hamming distance or the Euclidean distance with respect to a bit string of serial data DC input in a time series, and generates an error corresponding to the maximum likelihood estimation. After performing a correction process, each bit of the decoded serial data DC is output and output to the microcontroller 1 as decoded transmission data. The spread code communication device of the present invention performs error correction of transmission data using the above-described convolutional code, so that data communication performance is improved and a communication distance can be increased.

[0168] The intensity integrating circuit 16 outputs the baseband signal I
The sum of the absolute value of the change amount ΔI (voltage difference signal DSI) and the change amount ΔQ (voltage difference signal DSQ) of each of the baseband signal Q is calculated by an AGC (Automatic Gain Con).
troll) cumulative addition over a predetermined period required for control,
The cumulative value obtained by the cumulative addition is compared with preset comparison data that defines an upper limit value and a lower limit value of the cumulative value. When the accumulated value is larger than the upper limit value of the comparison data, the intensity integration circuit 16 reduces the gain of the AGC amplifier 48 placed before the QPSK demodulation unit 34 of the QPSK modulation / demodulation unit 5 to reduce the conversion rate. Adjust so that it falls within the range of the comparison data. When the accumulated value is smaller than the lower limit value of the comparison data, the intensity integration circuit 16 similarly increases the gain of the AGC amplifier 48 and adjusts the conversion rate to fall within the range of the comparison data.

Next, an example of an operation of transmitting transmission data in the spread code communication apparatus according to one embodiment will be described with reference to FIGS. The microcontroller 1 receives, for example, an 8-bit data signal DR “1, 0, 0, 0, 1, 1, 1, 0” from another circuit (not shown) as transmission data.
Is entered. Thereby, the microcontroller 1 follows the program stored in the internal storage unit,
The transmission process of the data signal DR “1, 0, 0, 0, 1, 1, 1, 0” is started. And the microcontroller 1
Is a data signal DR “1, 0, 0, 0, 1, 1, 1, 1, which is parallel transmission data to be transmitted to another spread code communication apparatus.
“0” is converted to serial data DT “10001110” and output to the convolutional encoder 2.

As a result, the convolutional encoder 2 receives the input serial data D
Each bit constituting T “10001110” is convolved with a plurality of preceding bits to generate an output signal [G
0, G1], the output signal [0, 1], the output signal [1, 0], the output signal [0, 0], the output signal [1,
0], output signal [0,0], output signal [0,1], output signal [1,1], output signal [0,1] in time series with output signal G0 first, then output signal G1 is output later, and the serial data DC "011000100011" is output.
101 ”is output to the data spreading unit 3 from the left end. Then, the data spreading unit 3 sequentially starts from the convolutional encoder 2.
The output serial data DC "0110001000
"011101" is spread spectrum by bit,
The encoded data is output to the phase rotation modulator 4 as spread data DS. That is, the data spreading unit 3 converts the sequentially input bits of the serial data DC “10001110” into
Spread by a predetermined spreading code for each bit, for example,
The 13-chip spreading code "1111101111010"
By "0", the spectrum is sequentially spread in time series. For example, since the value of the leftmost bit is “0”, the data spreading unit 3 sets the spread data DS “000” as the spread data.
0010001011 "is output, and the value of the second bit from the left end is" 1 ". As spread data, spread data DS" 11111011110100 "is sent to the phase rotation modulator 4 in the bit arrangement order of the serial data DC (right end). To), output in chronological order.

Then, the phase rotation modulator 4 outputs the spread data DS “11111011” input from the data spreading unit 3.
"10100" is sequentially encoded for each chip from the left end in accordance with the value of the chip. For example, assuming that the point A (see FIG. 2) is the starting point, the spread data DS “1111101”
Since the value of the leftmost chip of “110100” is “1”, the phase rotates counterclockwise, and the phase moves from point A to point B. At this time, the phase shift from the point A to the point B is "-I" in order to reduce the baseband signal I. Next, since the value of the second chip from the right is also “1”, the phase rotates counterclockwise, so that the phase moves from point B to point C. At this time, the reason why the phase shifts from the point B to the point C is to reduce the baseband signal Q,
Q ”.

Similarly, as a result of encoding for 13 chips, if the spread data DS of bits “1” in the serial data DC is “11111011110100”, if the point A is the starting point in the encoding, the point A Movement is ｛A
→ B → C → D → A → B → A → B → C → D → C → D → C →
B}, and [−I, −Q, I, Q, −I, I, −I,
-Q, I, -I, I, -I, Q] are generated. In the serial data DC, since the second bit from the left end is “0”, the spread data DS
Is "0000010001011", and since the point B is a starting point in encoding, the movement from the point B is ｛B → A → D → C → B → A → B → A → D → C → D → C
→ D → A}, and [-Q, -I, Q, I, -Q, Q,
-Q, -I, Q, -Q, Q, -Q, I] are generated.

As a result, the phase rotation modulator 4 outputs the data of the amplitude components of the baseband signal I and the baseband signal Q corresponding to a series of phase points to the QPSK modulation / demodulation unit 5. Here, the phase rotation modulation unit 5 outputs the phase rotation sequence [−
I, -Q, I, Q, -I, I, -I, -Q, I, -I,
I, -I, Q], and outputs the amplitude data to the I channel and the Q channel in order from the left end data.
That is, the phase rotation modulator 4 sets [1,
-1, -1,1,1, -1,1, -1, -1, -1,1,-
[1, 1, -1, -1,...] And outputs a data string of [1, 1, -1, -1, 1, 1, 1,
1, 1, -1, -1, -1, -1, -1, 1,...] Are output. The QPSK modem 5
A modulation signal is generated by phase modulation based on the input data sequence of the amplitude signals of the I- and Q-channels of the phase rotation sequence, and the antenna 6 radiates the modulation signal as radio waves into space.

Next, an example of the operation of receiving transmission data in the spread code communication apparatus according to one embodiment will be described with reference to FIGS. The antenna 6 receives a radio wave, converts it into an electric signal Di, and outputs the electric signal Di to the QPSK modulation / demodulation unit 5. As a result, the QPSK modulation / demodulation unit 5 removes low-frequency noise and harmonics included in the electric signal Di, performs two-phase demodulation independently, and demodulates and outputs two reference carriers having phases different by π / 2. As two baseband signals I
And a baseband signal Q. And QPS
The K modulator / demodulator 5 converts an analog voltage value of the baseband signal Q sampled at a predetermined sampling rate into a digitally indicated voltage value DVQ, and outputs this voltage value DVQ to the signal difference calculator 7. The analog voltage value of the sampled baseband signal I is converted into a digital voltage value DVI, and this voltage value DVI
Is output to the signal difference calculator 7.

Next, the signal difference calculator 7 converts the input voltage signal DVI into the previously sampled voltage signal DV.
It subtracts from I and outputs a voltage difference signal DSI to the matched filter 8 as a voltage difference between the two. Similarly, the signal difference calculator 7 subtracts the input voltage signal DVQ from the previously sampled voltage signal DVQ, and outputs a voltage difference signal DSQ to the matched filter 8 as a voltage difference between the two.

The matched filter 8 uses the voltage difference signal DSI and the voltage difference signal DSQ input in time series from the signal difference calculator 7 at the points A,
The data is rearranged into a data format corresponding to each of the phase rotation sequences starting from the points B, C, and D, that is, the data sequence D1 [DSI, DS
Q, DSI, DSQ, DSI, DSI, DSI, DS
Q, DSI, DSI, DSI, DSI, DSQ], and a data string D2 corresponding to the encoding of the data “0”.
[DSQ, DSI, DSQ, DSI, DSQ, DSQ,
DSQ, DSI, DSQ, DSQ, DSQ, DSQ, D
SI].

Here, when the rotation start point is point A, the phase rotation sequence used by the transmitting spread code communication apparatus to encode the data “1” in the transmission data is [−I, −Q,
I, Q, -I, I, -I, -Q, I, -I, I, -I,
Q], and the phase rotation sequence used to encode the data “0” is [−Q, −I, Q, I, −Q, Q, −Q, −I,
Q, -Q, Q, -Q, I], and using the rules shown in paragraphs 0021 and 0022, the matched filter 8
Detects the correlation value of the transmitted encoded data sequence from the values of the voltage difference signal DSI and the voltage difference signal DSQ input in time series. At this time, the matched filter 8
Is obtained by multiplying the numerical value of the voltage difference signal by a code indicating the rotation direction of each of the phase rotation sequences corresponding to the data sequence D1 and the data sequence D2, and for each data sequence, the voltage difference signal corresponding to the chip of the data sequence Add the value of.

That is, for example, with the starting point of the phase rotation being point A, the code {-1, -1,1,1, -1, -1,1,-of the phase rotation sequence used for encoding the data of "1". 1, -1,
1, -1, 1, -1, 1] to a data string D1 [DSI,
DSQ, DSI, DSQ, DSI, DSI, DSI, D
SQ, DSI, DSI, DSI, DSI, DSQ] and multiply the corresponding chip by a data string [-DSI, -D
SQ, DSI, DSQ, -DSI, DSI, -DSI,
−DSQ, DSI, −DSI, DSI, −DSI, DS
Q] is added. As a result, the addition result is output as correlation data MP for matching (correlation).

Similarly, with the point A as the starting point of the phase rotation, the code {-1, -1,1,1, -1, -1,1,1 of the phase rotation sequence used for encoding "0" data. -1, -1,1,1,
−1, 1, −1, 1] into a data string [DSI, DSQ,
DSI, DSQ, DSI, DSI, DSI, DSQ, D
SI, DSI, DSI, DSI, DSQ] and multiply the corresponding chip by a data string [-DSI, -DSQ, D
SI, DSQ, -DSI, DSI, -DSI, -DS
Q, DSI, -DSI, DSI, -DSI, DSQ]. As a result, the addition result is output as correlation data MM for matching (correlation).

In the above-described decoding, as in the case where the point A is set as the starting point of the phase rotation, the starting point of the phase rotation in the phase rotating sequence using the data “1” and the data “0” in the transmission data for encoding is set. Detecting matching (correlation) with the phase rotation sequence at points B, C, and D,
The correlation data MP and the correlation data MM are output to the peak synthesis circuit 9 and the peak configuration circuit 10, respectively. This allows
Even if the signal level of the input data is buried in the noise level, the correlation between the amount of rotation change in the time series of the received signal and the rotation direction corresponding to the spreading code as a result of despreading in spread spectrum communication. In this case, the integration effect can be obtained, and the peak of the received transmission data can be detected. That is, since the spread data having a weak signal level has a high correlation with the spread code, a signal level sufficiently higher than the noise level can be obtained.

The peak synthesizing circuit 9 takes the absolute values of the correlation data MP based on the points A, B, C, and D, which are input from the matched filter 8, and adds them all. And outputs the addition data DP to the difference calculator 11. Similarly, the peak synthesizing circuit 10 takes the absolute values of the correlation data MM input from the matched filter 8 with reference to the points A, B, C, and D, adds all of them, and adds them all. The data DM is output to the difference calculator 11. This makes it possible to increase the data level of the correlation peak with respect to the noise level.

The peak synthesizing circuit 9 converts the correlation data MP having the largest value among the input correlation data MP, using the point A (or point C) and the point B (or point D) as a rotation reference. It may be output as the maximum data DP. Similarly, the peak synthesizing circuit 10 converts the correlation data MM having the maximum value among the input correlation data MM, using the point A (or the point C) and the point D (the point B) as a rotation reference, to the maximum data DM. May be output. As a result, the correlation data having the highest correlation at the level of the data of the correlation peak can be used in the next difference calculator 11. As described above, the spread code communication apparatus of the present invention provides an I / O signal indicating the phase of the carrier wave between the transmitting side and the receiving side over time.
Even if the reference coordinate axis of the Q phase plane is shifted (VC
Since the frequency of the carrier wave changes over time due to O · 32) and the determination timing for determining the correlation peak difference signal PM is always corrected, it is possible to accurately decode the value of the transmission data. I have.

Next, the difference calculator 11 sequentially adds the added data (maximum data) DP inputted from the peak synthesizing circuit 9.
And the difference between the sum data (maximum data) DM input from the peak synthesis circuit 10 and the difference signal PM as the difference.
Is output to the peak detection circuit 12. At the same time, adder 13
Are sequentially inputted addition data DP and addition data DM
Is added, and the addition result TM is output to the peak timing circuit 14 in time series each time the addition data DP and the addition data DM are input.

At this time, the peak timing circuit 14
The timing at which the addition result TM input from the difference calculator 11 is cumulatively added for each chip unit (including oversampling) of the spread data over m periods of the spread data and the peak detection circuit 12 makes a determination, that is, transmission. The timing of determining whether the difference signal PM is “0” or “1” in data bit units is corrected every m periods. In the matched filter 8, the correlation peaks between the spread code and the input voltage difference signal DSI and voltage difference signal DSQ are determined at points A and B with respect to data "0" and data "1" in the transmission data. Output is performed for a phase rotation sequence using the points, points C and D as a reference for phase rotation. At this point, the timing of the correlation peak in one cycle of the spread data is unknown.

For this reason, as described above, the peak detection circuit 12 sets the difference signal PM and the difference signal PM at the timing of the chip at which the correlation peak appears in one cycle of the spread code.
A comparison is made with a previously set determination level to determine whether the difference signal PM from the difference calculator 11 is data “0” or data “1” in the transmission data. However, as for the relationship between the frequencies of the carrier waves on the transmitting side and the receiving side, the receiving side has points A, B,
Since it is not known which of the points C and D is the starting point of the phase rotation, it is necessary to detect the timing of determining whether the difference signal PM data is “0” or “1” in the initial stage. Yes, and only the chip rate (system clock frequency) serving as a reference for the processing speed on the receiving side and the chip rate (frequency) on the transmitting side roughly match, and the above is detected as time elapses. Since the determination timing is shifted, the correction is performed every m periods in which the shift is equal to or larger than the allowable value. As a result, the receiving side uses the internally generated local chip rate (frequency of the system clock of the microcomputer or the logic) which substantially coincides with the transmitting side. Even if it deviates, it can be corrected in real time.

For example, at this time, if the transmitting side sequentially transmits the serial data DC “10001110”, the peak detection circuit 12 sequentially converts the difference signal PM input from the difference calculator 11 at the above-described determination timing.
It is determined whether the data is either “0” or data “1”, and as a determination result, data “1”,
It is determined that the data is “0”,..., Data “0”, and is output to the Viterbi decoder 15 as serial data DC “0110001000011101” (or not a hard decision of “0” or “1” but a multi-bit soft decision). Perform judgment output).

The Viterbi decoder 15 sequentially decodes and inputs the serial data DC “011000”.
Each bit of the transmission data of "1000011101" is input, a predetermined number of bits are accumulated, and a signal obtained as the next signal is obtained by using a Viterbi decoding method of selecting a trellis path that minimizes the Hamming distance or the Euclidean distance. The correct state is estimated from the combination with the stored signal, and serial data DT as transmission data is output to the microcontroller 1. For example, "010101010
After the preamble signal of "1", the serial data DC
When each bit of “0110001000011101” is sequentially input from the left end, the Viterbi decoder 15
As the decoding result, the serial data DT “1000111”
"0" is output to the microcontroller 1 from the left end.
Then, the microcontroller 1 outputs the input serial data DT “10001110” to an external circuit at a predetermined timing.

When the voltage value DVI and the voltage value DVQ are n
When sampling is performed by double oversampling, it is necessary to change the configuration of the matched filter shown in FIG. That is, in the case of double oversampling, as shown in FIG. 7, 13 (spread code) × 2
(One set of data) x 2 (multiple of oversampling)-3
Determines the number of registers constituting the shift register. The last “−3” is because the multiplier is provided only in one of the four registers and is used for the correlation value detection processing, that is, the data corresponding to the thirteenth chip of the spreading code is “ 2 (a set of data) × 2 (a multiple of oversampling) ”, the remaining three registers are unnecessary.

In the spread code communication apparatus according to the above-described embodiment, on the receiving side, a local carrier having substantially the same phase and frequency as the carrier on the transmitting side is converted into an internal VCO3.
2, a base hand signal I and a baseband signal Q are extracted from the received electric signal Di by a QPSK demodulation unit 34 having a built-in frequency conversion circuit, quadrature demodulator, and the like. At this time, when the frequencies and phases of the independently generated carrier waves are slightly shifted between the transmitting side and the receiving side, the baseband signal I and the baseband signal Q are on the I / Q phase plane (signal space). Is observed as an operation in which the reference for phase determination in is rotated. However, the signal encoded on the transmitting side using the phase rotation direction as described above has the phase rotating counterclockwise or clockwise, so that the phase rotation does not stop. Even if the phase reference is rotated and shifted on the Q phase plane, if the rotation speed at the shift is sufficiently lower than the rotation speed by the phase rotation coding, the direction of the phase rotation in the coding can be determined. is there.

Further, in the spread code communication apparatus according to the above-described embodiment, it is possible to accurately decode transmission data even in a low C / N state buried in noise. That is, in the spread code communication apparatus according to the embodiment, in the low C / N state, the noise is larger than the phase-rotation-modulated signal level, so that the phase rotation movement due to noise fluctuation becomes dominant, Even when the phase is not rotated corresponding to the encoding on the I / Q phase plane,
Since the noise and the coded spread data are additive, the center of the noise distribution can be detected so as to shift regularly in accordance with the coded carrier according to the direction of phase rotation. By correlating the decoded spread data with the spread code in the filter 8, transmission data can be reproduced even in a low C / N state.

Therefore, the spread code communication apparatus according to the present embodiment, as in the case of despreading in spread spectrum communication, uses the amount of phase change in the time series of the received signal (the voltage difference signal output from the signal difference calculator 7). The correlation between the DSI and the voltage difference signal DSQ) and the spreading code makes it possible to detect the rotation direction of the phase due to the integration effect, and the transmission data transmitted by the transmission side is reproduced accurately by decoding by the matched filter 8. It becomes possible.

Further, the spread code communication apparatus according to one embodiment comprises:
An operation in which the phase of the encoded signal rotates counterclockwise on the I / Q phase plane is defined as data “1”, and an operation in which the phase rotates clockwise is defined as data “0”. In order to perform encoding, the phase should not be fixed on the I / Q phase plane, and the phase should not fly diagonally, and should be smoothly rotated left and right through a low-pass filter. In the phase decoding, the rotation direction of the phase can be detected, and the transmission data accurately transmitted by the transmission side can be reproduced by the despreading process by the matched filter 8.

Further, the spread code communication apparatus of one embodiment comprises a cross shift register 380, a cross shift register 3
90, the cross shift register 580 and the cross shift register 590, the points A to D are used as the starting point of the phase rotation.
Since the data sequence D1 to data sequence D4 of the phase rotation code corresponding to each of the data "1" and the data "0" can be formed, a complicated structure of the exchange processing circuit is not required, and the data sequence of the data sequence is realized only by hardware. Since the generation circuit can be configured, the circuit configuration can be prevented from becoming large-scale, and the replacement process can be performed only by the shift process. (Ie, real-time), it is possible to perform arithmetic processing of correlation value data.

In addition, since the spread code communication apparatus of one embodiment encodes using the rotation of the phase of the carrier,
Because the allowable level of the frequency deviation of the carrier wave between transmission and reception can be set large, for example, communication can be performed sufficiently with the accuracy of an unadjusted crystal oscillation circuit, and a stable reception circuit that is resistant to characteristic fluctuations due to operating temperature , The rotation direction of the phase can be detected even in the low C / N state, and the transmission data accurately transmitted by the transmission side can be reproduced by the despreading process by the matched filter 8.

As described above, one embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. The present invention is also included in the present invention. Further, in the above-described embodiment, the correlation operation or the like is performed as a digital signal using the carrier signal of the input analog signal via the A / D converter 46 and the A / D converter 47. However, in place of the matched filter of one embodiment, even if an analog type matched filter circuit or the like is applied based on a sample-and-hold circuit or the like that samples an analog signal and holds the analog signal as it is, The same effect as the effect obtained is obtained.

In the digital circuit according to the second embodiment, the matched filter 8 in one embodiment may be replaced with a correlator 8A using a sliding correlator shown in FIG. FIG.
FIG. 7 is a block diagram showing a configuration of a correlator 8A that performs despreading of spread data by a sliding correlator instead of the matched filter 8 in one embodiment. At this time, the matched filter 8 shown in FIG.
Is replaced by

The I / Q exchanger 53 includes a signal difference calculation circuit 7
The voltage difference signal DSI and the voltage difference signal DSQ input from (see FIG. 1) are alternately input to the sliding correlator 700, the sliding correlator 701, the sliding correlator 702, and the sliding correlator 703 by switching. At this time, sliding correlator 700 to sliding correlator 703 in correlator 8A.
Are points A, B, and C generated according to the spreading code, respectively.
Whether the data of each phase rotation sequence starting from the points D and D (the start point of phase rotation) matches the spread data composed of the voltage difference signal DSI and the voltage difference signal DSQ input in time series Detect whether or not. Here, the phase rotation sequence in the encoding is a paragraph number 0026 and a paragraph number 002.
7.

That is, the correlator 8A sequentially outputs the voltage difference signal DSI and the voltage difference signal DSI input from the signal difference calculator 7.
The SQ is converted by the I / Q exchanger 53 into, for example, a data format corresponding to each phase rotation sequence for encoding data “1” and data “0”, which is used by the transmitting spread code communication apparatus for encoding. Sort. At this time, if the state is not oversampling, the signal difference calculation circuit 7
For example, a data string [DSI1, DS
I2, DSI3, DSI4, DSI5, DSI6, DS
I7, DSI8, DSI9, DSI10, DSI11,
, DSI12, DSI13,...], And a data string [DSQ1, DSQ2, DSQ3, DQ] of the voltage difference signal DSQ.
SQ4, DSQ5, DSQ6, DSQ7, DSQ8, D
SQ9, DSQ10, DSQ11, DSQ12, DSQ
13,...] Are input.

Each time a voltage difference signal is input, the I / Q switch 53 switches the switching so that the voltage difference signals of the data sequence D1 and the data sequence D4 in the phase rotation sequence based on the spreading code are arranged. To the sliding correlator 700 and the sliding correlator 703,
Data string [DSI1, DSQ2, DSI3, DSQ4
DSI5, DSI6, DSI7, DSQ8, DSI9,
DSI10, DSI11, DSI12, DSQ13]. Similarly, every time a voltage difference signal is input, the I / Q exchanger 53 is arranged such that the voltage difference signals of the data sequence D2 and the data sequence D3 in the phase rotation sequence based on the spreading code (for example, 13 chips) are arranged. , And switching is performed, and a data string [DSQ1, DSI2,
DSQ3, DSI4, DSQ5, DSQ6, DSQ7,
DSI8, DSQ9, DSQ10, DSQ11, DSQ
12, DSI 13].

Since the code shift register 704 has 13 chips of the spreading code, the code sequence {-1, -1, + 1, + 1, -1,1, + 1, -1 ,,-} of the code corresponding to each chip.
1, +1, -1, +1, -1, +1} are stored, the output terminal is a cyclic shift register connected to the input terminal, and the code string is shifted by one bit (cyclic).
By doing so, the codes are output to the sliding correlator 700 and the sliding correlator 701 in the order of the code string (from the left end to the right end). The code shift register 704 shifts by thirteen times, so that the code sequence circulates. Therefore, the code shift register 704 returns to the initial state, that is, the code sequence.

Similarly, since the code shift register 705 has 13 spreading codes, the code sequence {-1, + 1, + 1, -1, -1, -1, + 1, + 1,...
−1, +1, +1, −1, +1, −1, −1} are stored, and the output terminal is a cyclic shift register connected to the input terminal. ), The codes are inserted into the sliding correlator 702 and the sliding correlator 7 in the order of the code string.
03 is output. The code shift register 704 shifts by thirteen times, so that the code sequence circulates. Therefore, the code shift register 704 returns to the initial state, that is, the code sequence.

Since sliding correlator 700 to sliding correlator 703 have the same configuration, the operation of sliding correlator 700 will be described using sliding correlator 700 as a representative. The sliding correlator 700 is
Inside, an integrating circuit 800 (not shown) is provided. Each time a potential difference signal is input from the I / Q exchanger 53, a code to be output is input while multiplying the code shift register 704 once and multiplied. The multiplied data is added to the circuit and accumulated.

That is, the sliding correlator 700
For example, assuming that the code shift register 704 is in the initial state and the voltage difference signal DSI1 is input, when the code “−1” is input from the code shift register 704, “−DSI1” is added to the integrating circuit 800. accumulate. When the code shift register 704 shifts by one chip and outputs the second code “−1”, the sliding correlator 700 outputs the second input voltage difference signal DS.
Q2 is multiplied by this “−1”, and the multiplication result “−DSQ”
"2" is added to the accumulation circuit 801 and accumulated.

As described above, the sliding correlator 7
00 is a data string [DSI1, DSQ2,
DSI3, DSQ4, DSI5, DSI6, DSI7,
DSQ8, DSI9, DSI10, DSI11, DSI
12, DSQ13] to the code string {-1, -1, + 1, + 1, -1, -1, + 1,-from the code shift register 704.
1, −1, + 1, −1, + 1, −1, + 1} are sequentially multiplied, and the multiplication result [−DSI1, −DSQ2, DSI
3, DSQ4, -DSI5, DSI6, -DSI7,-
DSQ8, DSI9, -DSI10, DSI11, -D
SI12, DSQ13] to the integrating circuit and accumulate them.

When the sign shift register 704 shifts by one bit and outputs the last sign “+1”, the sliding correlator 700 outputs the last voltage difference signal DSQ.
13 is multiplied by this “+1”, and the multiplication result “DSQ1
3 "is added to the accumulation circuit 800 and accumulated. This allows
Since the integrating circuit 800 has added the data of the thirteen voltage difference signals, the integrating circuit 800 outputs the integrated data to the peak synthesizing circuit 9 as correlation data MP. Then, the sliding correlator 700 deletes the data stored in the integrating circuit 800 and sets the data to “0”.

The above-described processing is repeated, and the sliding correlator 700 performs despreading by multiplying the voltage difference signal input in time series from the I / Q converter 53A by the code of the code string. Also, the sliding correlator 701
Similarly to the sliding correlator 700, every time a voltage difference signal is input in time series from the I / Q converter 53, the voltage difference signal is set according to the code sequence set in the code shift register 704.
The correlation data MM is output. Further, the sliding correlator 702 also performs a code shift register 705 every time the voltage difference signal is input from the I / Q converter 53 in time series.
The correlation correlator MP is output in accordance with the code string set in the..., And the sliding correlator 703 is similarly set in the code shift register 705 every time a voltage difference signal is input in time series from the I / Q converter 53. According to the code string
The correlation data MM is output.

At this time, as described above, the correlation data MP and the correlation data MM have the same sign and polarity (phase A reference and point B reference in the case of data “1”), or not, at all, as described above. In the case of the opposite polarity (the C point reference and the D point reference in the case of the data “1”), the intensity of the correlation signal of the maximum peak is obtained. Conversely, if the polarities of the codes are different and do not match, the addition results are averaged, and the peak of the correlation value decreases. Therefore, when the peak of the correlation value during the predetermined period does not reach the predetermined level, it is determined that the timing of the correlation is not synchronized, and the period of the correlation calculation is set to 1
The chip is shifted and the above-described correlation operation is started. That is,
Until the peak of the correlation value reaches a predetermined level, the correlation operation of the input data sequence (voltage difference signal input in time series) is performed while sequentially shifting the synchronization of the correlation operation by one chip cycle.

The sliding correlators 700 to 700 of the I / Q exchanger 53 in the matched filter 8A described above.
The switching operation of the data string of the voltage difference signal to the sliding correlator 703 is performed by program control of the microcontroller 1 as needed, for example, by combining the data of the data strings D1 to D4 of the phase rotation sequence, that is, spreading. When the code is changed, it can be changed arbitrarily. Similarly, the code of the phase rotation sequence to be multiplied by the voltage difference signal in the code shift register 704 and the code shift register 705 is also controlled, for example, by the program control of the microcontroller 1 as needed, for example, the data sequence D1 of the phase rotation sequence The polarity setting can be changed, for example, when the data combination of the data sequence D4, that is, when the spreading code is changed.

In the spread code communication apparatus according to the second embodiment, as in the case of the first embodiment, the local carrier having substantially the same phase and frequency as the carrier on the transmitting side is transmitted to the VCO 32 inside the receiving side. The base hand signal I and the baseband signal Q are extracted from the received electric signal Di by the QPSK demodulation unit 34 having a built-in frequency conversion circuit and quadrature demodulator. At this time,
When the frequencies and phases of the independently generated carrier waves are slightly shifted between the transmitting side and the receiving side, the baseband signal I and the baseband signal Q are determined on the I / Q phase plane (signal space). Is observed as if the reference is rotating. However, the signal encoded on the transmitting side using the phase rotation direction as described above has the phase rotating counterclockwise or clockwise, so that the phase rotation does not stop. Even if the phase reference is rotated and shifted on the Q phase plane, the rotation speed at the shift is smaller than the rotation speed obtained by the phase rotation coding.
If the rotation speed is sufficiently low, the direction of the phase rotation in encoding can be determined.

In the above-described spread code communication apparatus according to the second embodiment, a low C /
Even in the N state, it is possible to decode transmission data with high accuracy. That is, in the spread code communication apparatus according to the second embodiment, in the low C / N state, since the noise is larger than the phase-rotation-modulated signal level, the phase rotation movement due to the noise fluctuation is dominant. Even if the phase is not rotated corresponding to the encoding on the I / Q phase plane, the noise and the encoded spread data are additive, and the center of the noise distribution is encoded by the direction of rotation of the phase. Since it is possible to detect that the spread data is shifted in a regular manner in accordance with the converted carrier, the spread code is correlated with the spread code in the correlator 8A, so that even in a low C / N state, Reproduction of transmission data is possible.

Therefore, the spread code communication apparatus according to the second embodiment operates in the same manner as the despreading in the spread spectrum communication, in which the phase change in the time series of the received signal (the voltage output from the signal difference calculator 7). The correlation between the difference signal DSI and the voltage difference signal DSQ) and the spreading code makes it possible to detect the direction of rotation of the phase due to the integration effect, and reproduces the transmission data transmitted by the transmitting side correctly by decoding by the correlator 8A. It is possible to do.

The spread code communication apparatus according to the second embodiment defines an operation in which the phase of a coded signal rotates counterclockwise on an I / Q phase plane as data “1”, and conversely. Since an operation in which the phase rotates clockwise is defined as data “0” and coding is performed, the phase is not fixed on the I / Q phase plane, and the phase does not fly diagonally. Through the filter, the operation can be performed so as to smoothly rotate left and right. In the phase decoding, the rotation direction of the phase can be detected, and the transmission data transmitted by the transmission side can be accurately despread by the correlator 8A. By processing
It becomes possible to reproduce.

Further, since the spread code communication apparatus of the second embodiment performs encoding by using the rotation of the phase of the carrier, the allowable level of the frequency shift of the carrier between transmission and reception can be set large. Communication becomes possible with the accuracy of an unadjusted crystal oscillation circuit, and a stable receiving circuit that is resistant to fluctuations in characteristics due to operating temperature enables the phase rotation direction to be detected even in a low C / N state. The transmission data transmitted by the transmission side can be reproduced by the despreading process by the correlator 8A.

In addition, in the spread code communication apparatus according to the second embodiment, when a high speed correlation operation is not required, the above-described sliding correlator 700 to sliding correlator 703 can be used to provide a matched filter. Since the circuit configuration of the portion is simplified, there is an effect that the power consumption at the time of correlation can be significantly reduced.

[0215]

According to the present invention, since a carrier frequency correcting circuit is not required between the transmitting and receiving apparatuses, the required C / N level can be reduced by the effect of the spread rate of the spread spectrum. The communication distance can be increased by the strength. Further, according to the present invention, since the encoding is performed using the rotation of the phase of the carrier, the allowable level of the frequency shift of the carrier between transmission and reception can be set large, for example, with the accuracy of an unadjusted crystal oscillation circuit. Sufficient communication becomes possible, and a stable receiving circuit that is resistant to characteristic fluctuations due to operating temperature can be configured.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a spread code communication device according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing encoding based on chip values of phase rotation modulation.

FIG. 3 is a block diagram illustrating a configuration example of a QPSK modulation / demodulation unit 5 in FIG. 1;

FIG. 4 is a conceptual diagram showing a sampling process of a baseband signal I or a baseband signal Q.

FIG. 5 is a block diagram showing a configuration of a matched filter 8 used in one embodiment.

FIG. 6 is a block diagram showing a configuration of a matched filter 300 in FIG.

FIG. 7 is a block diagram showing a configuration of a matched filter 500 of FIG.

8 is a block diagram showing a configuration of the cross shift register 380 in FIG. 6 (or the cross shift register 580 in FIG. 7).

9 is a block diagram illustrating a configuration of the cross shift register 390 of FIG. 6 (or the cross shift register 590 of FIG. 7).

FIG. 10 is a block diagram showing a configuration example of a peak timing circuit 14 in FIG.

FIG. 11 is a block diagram showing a configuration of a matched filter 8B that performs despreading of spread data by a sliding correlator used in the second embodiment.

FIG. 12 is a conceptual diagram illustrating a deviation of a reference of an I / Q phase plane between a transmitting side and a receiving side.

[Explanation of symbols]

Reference Signs List 1 microcontroller 2 convolutional encoder 3 data spreading unit 4 phase rotation modulation unit 5 QPSK modulation / demodulation unit 6 antenna 7 signal difference calculator 8, 8A matched filter 9 peak synthesis circuit 11 difference calculation unit 12 peak detection circuit 13 adder 14 peak Timing circuit 15 Viterbi decoder 16 Intensity integration circuit 20, 21 Buffer 22, 23, 28, 39, 42, 43 Low-pass filter 24, 25, 27, 38, 40, 41, 44, 45 Amplifier 29, 33 Switch 35, 37 Band Pass filter 36 Linear amplifier 26 QPSK modulator 34 QPSK demodulator 46, 47 A / D converter 48 AGC amplifier 380, 390, 580, 590 Cross shift register 53 I / Q exchanger 250 Selector 251 Loop counter 252 Addition circuit 253 Flat Equalization circuit 254 Detection circuit 315, 365, 515, 565 Correlation adder 380A, 380B, 390A, 390B Shift register 580A, 580B, 590A, 590B Shift register 700, 701, 702, 703 Sliding correlator 704, 705 Code shift register R1 , R2, R3, R4, R5, ..., Rn-1, Rn register RG register string

Claims (7)

[Claims] 1. A receiving means for receiving a coded signal in which transmission data is spread by a predetermined spreading code and which is coded according to a rotation direction of a phase of a carrier consisting of an I signal and a Q signal, and Demodulating means for demodulating the I signal and the Q signal, and decoding means for decoding the coded signal according to the rotation direction of the coded signal obtained based on the I signal and the Q signal, and outputting the coded signal as spread data When,
A plurality of correlation operation means for despreading by taking a different phase of the spread data as a starting point of encoding, and taking a correlation with each of the spread codes, and outputting a correlation signal as a correlation result; and A spread code communication apparatus comprising: a data reproducing unit that calculates a correlation signal and reproduces the transmission data based on a result of the calculation. 2. The method according to claim 1, wherein the decoding unit determines a phase position of the encoded signal in a signal space represented by the I signal and the Q signal with reference to a phase position of the encoded signal obtained immediately before. 2. The spread code communication according to claim 1, wherein the rotation direction of the data is obtained as a change amount ΔI and a change amount ΔQ, and the data of the change amount ΔI and the data of the change amount ΔQ are output in time series as the spread data. apparatus. 3. The correlation calculating means has the spread code as a combination of a plurality of rotation directions from different phases in the signal space, and calculates a correlation between the spread code and the spread data, 3. The spread code communication device according to claim 1, wherein the correlation peaks obtained in a time series are combined and output as the correlation signal. 4. The data reproducing means includes: a level of a negative correlation signal indicating data “0” in the correlation signal;
The level of the positive correlation signal indicating the data of “1” is compared, and when the level of the negative correlation signal is large, the transmission data is estimated and output as “0”, and the level of the positive correlation signal is 4. The spread code communication apparatus according to claim 1, wherein when the transmission data is large, the transmission data is estimated as "1" and output. 5. The first correlation calculation means for sequentially holding and transferring each of the data of the change amount ΔI and the data of the change amount ΔQ inputted from the decoding means in time series.
And a second register column, and a first register column for exchanging a transfer destination between the first register column and the second register column in a register at a corresponding predetermined position. The spread coding apparatus according to any one of claims 1 to 4, comprising a second register string. 6. The spread code communication according to claim 1, wherein said correlation operation means comprises a matched filter for despreading said spread data based on said spread code. apparatus. 7. A receiving means for receiving a coded signal in which transmission data is spread by a predetermined spreading code and which is coded according to a rotation direction of a phase of a carrier wave comprising an I signal and a Q signal, and Demodulating means for demodulating the I signal and the Q signal, and decoding means for decoding the coded signal according to the rotation direction of the coded signal obtained based on the I signal and the Q signal, and outputting the coded signal as spread data When,
A plurality of sliding correlation means for despreading by taking a different phase of the spread data as a starting point of the coding and respectively taking a correlation with the spread code, and outputting a correlation signal as a correlation result, A spread code communication apparatus comprising: a data reproducing unit that calculates a correlation signal and reproduces the transmission data based on a result of the calculation.