JP2001156680A - Spread code communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a coding communication system used for data communications employing a spread spectrum communication technology that can realize stable data transmission and reception even under an environment of a low C/N and extend the communication range without the need for a carrier recovery circuit and a frequency correction circuit or the like. SOLUTION: A communication unit of the communication system consists of a QPSK modulation/demodulation section 5 comprising a QPSK demodulation section receiving a coded signal from a spread coding communication unit that transmits spread data, which result from spreading transmission data with a prescribed spread code, as the coded signal of the data of a phase rotation sequence depending on the phase rotation direction of the waveform of the spread data, of a signal difference arithmetic unit 7 that obtains the spread data depending on the rotation direction of the phase of the received coded signal, and of a matched filter 8 that applies inverse spread processing to the spread data based on the spread code to recover the transmission data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication apparatus, and more particularly to an RF (Radio Frequency) transmission / reception apparatus for performing packet communication used in an indoor LAN (Local Area Network).

[0002]

2. Description of the Related Art Conventionally, in a synchronous detection system, not only communication using a spread spectrum communication system but also information of a carrier to be transmitted such as a frequency and a phase is transmitted to a carrier receiving side. Need to be detected from For example, a generally used QPSK (Quadrature Phase Shift Keying), whose concept is shown in FIG.
In a communication system using a modulation and demodulation method, a prefix code provided at the head of a burst signal in a short time prior to data communication on the receiving side in order to reliably and accurately demodulate received data. (Preamble)
, It is necessary to extract a carrier serving as a reference for modulation, and reproduce information on the frequency or phase of the carrier.

[0003] However, when the frequency and phase of the carrier are not accurately reproduced on the receiving side, as shown in FIG.
The coordinate axes of the signal space (I / Q phase plane) due to the baseband signal I and the baseband signal Q indicating the phase of the carrier wave are rotated and shifted, and the receiving side does not match the reference for detecting the phase with the transmitting side. Therefore, erroneous determination of received transmission data is performed. Therefore, in the demodulation circuit using the synchronous detection as described above, a frequency correction circuit such as a carrier recovery circuit or an AFC circuit is provided to detect the information of the carrier wave on the transmission side on the reception side and always correct the phase with the transmission side. In addition, a shift such as rotation of a coordinate axis is prevented.

[0004]

However, in order for the carrier reproduction circuit or the frequency correction circuit to operate normally on the receiving side, it is necessary that a carrier having a certain signal level is received from the transmitting side. In the transmission and reception, if a spread spectrum technique is used, a carrier having a low C / N (ratio of noise to the received power of a carrier) level where a signal is originally buried in noise can be received, thereby increasing the communication distance. Although it can be expected, there is a problem that the communication level is limited due to the limitation of the reception level required for frequency correction and the like on the transmission side on the reception side.

Further, the carrier recovery circuit and the frequency correction circuit receive the carrier for a certain period, and perform signal processing such as integration operation or LPF (Low Pass Filter). Continuous carrier reception is required. As a result, the preamble period is lengthened, and the data communication efficiency is reduced.
However, in data communication such as a LAN, data is transmitted and received in packet units, so that communication from the transmitting side is intermittent, which is not suitable for frequency correction processing or the like. The present invention has been made under such a background, and does not require a carrier recovery circuit and a frequency correction circuit in data communication using spread spectrum communication technology, and is stable even in a low C / N environment. Provided is a coded communication device capable of realizing efficient transmission and reception of data and extending a communicable distance.

[0006]

According to the present invention, there is provided a spread code communication apparatus comprising: a data spreading means for spreading transmission data by a predetermined spreading code and outputting the spread data as spread data; Encoding means for outputting as an encoded signal, a transmitting apparatus having a transmitting means for transmitting the encoded signal, a receiving means for receiving the encoded signal, and a rotation direction of the phase of the encoded signal. A receiving device having decoding means for obtaining the spread data and despreading means for despreading the spread data based on the spread code to reproduce the transmission data. With this configuration, in transmission and reception of transmission data between the spread code communication devices, it is only necessary that the frequency of the composite wave on the transmission side and the reception side substantially match, and depending on the rotation direction of the phase of the encoded signal. Since the spread data is obtained, despread and the signal level is increased by the integration effect to detect the transmission data, the data can be sufficiently reproduced even at a low C / N level. No correction circuit for matching the phase of the signal on the transmitting side and the receiving side is required. Therefore, in the spread code communication apparatus of the present invention, since the correction circuit does not operate unless there is a sufficient C / N level, it is possible to solve the problem of the conventional example that the transmission / reception distance is shortened and increase the communication distance. It is possible. Also,
The spread code communication device of the present invention does not require a correction circuit, so that the circuit can be made small, and the device can be reduced in size and cost.

The decoding means extracts the phase of the coded signal in a time series, detects the rotation direction of the extracted phase based on the phase of the coded signal received immediately before, and determines the rotation direction. With the configuration in which spread data is output as data, even if the reference of the phase in the signal space (on the I / Q phase plane) by the baseband signal I and the baseband signal Q in the transmission wave is rotated and shifted, the phase rotation is performed. Since the spread data is encoded according to the direction, if the rotational speed of this shift is set to a value sufficiently smaller than the rotational speed by the phase modulation, the rotational direction of the phase of the composite wave can be detected (determined), and the signal space can be detected. It is possible to reproduce the transmission data from the rotation direction of the phase of the composite wave with high accuracy even if the reference of the phase changes temporally.

The despreading means decodes the rotation direction data input in time series in accordance with a predetermined rule, and detects the correlation between the decoded rotation direction data and the spreading code. When the transmission data is reproduced by despreading, in the low C / N state, the noise is larger than the signal level encoded in the rotation direction, so that the phase rotation due to the noise fluctuation is performed. Is dominant, and even if the phase is not rotated on the I / Q phase plane in accordance with the encoding, the despreading means correlates the decoded spread data by the spreading code. Since only the signal that matches the spreading code is amplified by integration, transmission data can be reproduced even in a low C / N state.

If the decoding means is constituted by a matched filter for despreading the spread data based on the spreading code, the spread data input in time series from the decoding means is output for each chip. Since correlation can be obtained in real time, it is possible to determine packet synchronization in a short time with a short preamble, and it is possible to reproduce data at high speed by the correlation processing constituting the packet, thereby achieving high-speed communication. It can be used for packet communication requiring a high speed.

[0010] A spread code communication apparatus according to the present invention comprises: first data spreading means for spreading transmission data with a predetermined first spreading code and outputting the spread data as first spread data; A second data spreading means for spreading with a predetermined second spreading code and outputting the spread data as second spread data; coding the second spread data according to a rotation direction of a phase of a waveform and outputting as a coded signal; A transmitting device having an encoding unit, a transmission unit for transmitting the encoded signal, a receiving unit for receiving the encoded signal, and a decoding unit for obtaining the spread data from a rotation direction of the phase of the encoded signal Second despreading means for despreading the second spread data based on the expanded second spreading code to reproduce the first spread data; and converting the first spread data to the expanded spread data. 1 diffusion code The first spreading means and the second spreading means perform two-stage spread spectrum, and perform the comparison by performing the first spread means and the second spread means. In a small-scale data spreading circuit and a despreading circuit, a large spreading factor can be taken, so that the level of a received signal can be increased due to the effect of integration of spread data. Data transmission with high data transfer efficiency by enabling transmission data reception and using a matched filter for despreading of spread data, so that communication does not require redundant headers in intermittent packet communication etc. Is possible.

[0011] In the spread code communication apparatus, the correlation peak output from the decoding means is integrated for each chip timing constituting the spread code, and the transmission data is reproduced at any chip timing of one cycle of the spread code. If timing correction means for correcting whether or not to perform the correction is provided, even if the reference of the I / Q phase plane indicating the phase of the composite wave is shifted with the passage of time, the timing of the chip of one cycle of the spreading code at which the correlation peak is always maximum is always obtained. Is corrected, the timing for determining whether the transmission data is “0” or “1” is adjusted to an optimal position, and the transmission data can be determined with high accuracy.

Further, in the spread code communication apparatus, if a circuit for performing error correction such as a convolutional code on transmission data is provided, reception performance of transmission data can be improved.
It is possible to increase the communication distance between communication devices.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a spread code communication device according to the first embodiment of the present invention. Here, a QPSK (four-phase modulation) system is used for transmission and reception. In this QPSK method,
The two series of synchronized binary signals are made to correspond to two modulated waves having phases different from each other by π / 2. In the figure, a microcontroller 1 is composed of a CPU and a memory, and controls each part of the spread code communication device T according to a program stored in the memory. Details of the control of the microcontroller 1 will be sequentially described according to the description of each unit.

The microcontroller 1 converts transmission data, which is input from another circuit (not shown) and is transmitted to another spread code communication device, into a preamble and a C signal necessary for packet communication.
RC (Cyclic Redundancy Chec)
k) Convert the data to a series of serial data DT to which a code or the like is added, and output the serial data DT to the convolutional encoder 2. The convolutional encoder 2 is a convolutional encoder having a constraint length of 5 (indicating a numerical value instead of a code) and a coding rate of 、, and sequentially encodes input serial data DT by a convolution operation. The serial data DC is output to the data spreading unit 3.

The data spreading section 3 spreads the serial data DC output from the convolutional encoder 2 on a bit-by-bit basis, encodes the data, and outputs the resulting data to the phase rotation modulation section 4 as spread data DS. That is, the data spreading unit 3
One bit sequentially input of the serial data DC is assumed to be 13 chips, and for example, a spread code “111110111” is used.
0100 ", the spectrum is sequentially spread in time series.

At this time, when the value of the bit is "1", the data spreading section 3 sets the spread data D as the data after spreading.
S “11111011100100” is output, and when the value of the bit is “0”, the spread data DS “00000010001011” is sent to the phase rotation modulation unit 4 as the data after spreading to the phase rotation modulation unit 4 in time sequence in the bit arrangement order of the serial data DC. Output. At this time, the spreading code used includes a Barker sequence and an M sequence (Max) having good autocorrelation characteristics.
A spreading code such as an imum length code and a Gold sequence is suitable.

The phase rotation modulation section 4 encodes the spread data DS input from the data spread section 3 for each chip constituting the spread data DS by using the chip value. Here, the encoding performed in the phase rotation modulation unit 4 is based on a modulation / demodulation method that can normally reproduce transmission data even if the frequency of a synthetic wave generated locally between the spread code communication devices is shifted. is there. That is, in the conceptual diagram showing the encoding by the chip value of the phase rotation modulation in FIG.
The value of the chip of the spread data DS is represented by, for example, an I / Q phase plane (signal space) represented by a baseband signal I and a baseband signal Q as shown in FIG. Synthesized wave with baseband signal Q (4
Phase-modulated wave), that is, the counterclockwise rotation of the phase of the composite wave is expressed as “1”, and the clockwise rotation of the phase of the composite wave is expressed as “0” as shown in FIG. (Phase rotation modulation).

As shown in FIG. 2, the modulation point of the phase is a point A having a phase of "π / 4" and a phase modulation point of "3π".
/ 4 ", point C having a phase of" 5π / 4 ", and point D having a phase of" 7π / 4 ". For example, A
Assuming that the point is a starting point (a start point of phase rotation), when the value of the chip is “0”, the phase of the composite wave rotates clockwise, so that the phase of the composite wave moves from point A to point D. At this time, the reason why the phase of the composite wave moves from the point A to the point D is to decrease the baseband signal Q, which is expressed as “−Q”.

On the other hand, when the value of the chip is "1", the phase of the composite wave is rotated in the counterclockwise direction.
Move from point to point B. At this time, the phase of the composite wave moves from the point A to the point B to reduce the baseband signal I, and is expressed as "-I".

Thus, if the spread data DS of the bit "1" in the serial data DC is "11111011110100" as described above, the encoding is started from the left end, and the point A is used as a reference for rotation in the encoding. Move from point A to ｛A → B → C → D → A → B → A
→ B → C → D → C → D → C → B｝, [-I,-
Q, I, Q, -I, I, -I, -Q, I, -I, I,-
I, Q] is generated, and this code sequence is used as a phase rotation sequence (encoded signal). Also, the serial data D
If the spread data DS of the bit “0” in C is “0000010001011” as described above, A
If a point is used as a reference for rotation in encoding, the movement from point A is ΔA → D → C → B → A → D → A → D → C → B → C
→ B → C → D}, and [-Q, -I, Q, I, -Q,
[Q, -Q, -I, Q, -Q, Q, -Q, I] are generated.

If the point B is the starting point (the starting point of the phase rotation), if the value of the chip is "0", the phase of the composite wave is rotated clockwise, so that the phase of the composite wave is Move to a point. At this time, the phase of the composite wave moves from the point B to the point A because the baseband signal I is increased, and is expressed as “I”. On the other hand, when the value of the chip is “1”, the phase of the composite wave rotates counterclockwise, so that the phase of the composite wave moves from point B to point C. At this time, the reason why the phase of the composite wave moves from the point B to the point C is to decrease the baseband signal Q, which is expressed as “−Q”.

If the point C is the starting point (the starting point of the phase rotation), when the value of the chip is "0", the phase of the composite wave rotates clockwise, so that the phase of the composite wave changes from the point C to the point B. Move to a point. At this time, the reason why the phase of the composite wave moves from the point C to the point B is to increase the baseband signal Q, which is expressed as “Q”. On the other hand, when the value of the chip is “1”, the phase of the composite wave rotates counterclockwise, so that the phase of the composite wave moves from point C to point D. At this time, the fact that the phase of the composite wave moves from the point C to the point D means that the baseband signal I is increased, and is expressed as “I”.

If the point D is the starting point (the starting point of the phase rotation), when the value of the chip is "0", the phase of the composite wave rotates clockwise, so that the phase of the composite wave changes from the point D to the point C. Move to a point. At this time, the fact that the phase of the composite wave moves from the point D to the point C is to decrease the baseband signal I, and is expressed as "-I". On the other hand, when the value of the chip is “1”, the phase of the composite wave rotates counterclockwise, so that the phase of the composite wave moves from point D to point A. At this time, the reason why the phase of the composite wave moves from the point D to the point A is to increase the baseband signal Q, which is expressed as “Q”.

As described above, the meaning of indicating data by increasing or decreasing the baseband signal I and the baseband signal Q differs depending on which point is used as a reference for rotation. For example, when increasing the baseband signal I, "0" means moving from point B to point A, while "1" means moving from point C to point D. . For this reason, the result of encoding the data of the spread code differs depending on how to take the reference of rotation.

For example, the spread code "111110"
When "1110100" is used, the spreading code "11111011101" indicates "1" as transmission data.
00 "and the transmission code indicating" 0 "is the spreading code" 0000010001011 ". At this time, as a spreading code “11111011110100”, that is, as a spread-coded phase rotation sequence of data “1” (although the starting point of point A has been described above and repeated), the starting point of point A: [−I, −Q , I, Q, -I, I, -I,-
Q, I, -I, I, -I, Q] Point B origin: [-Q, I, Q, -I, -Q, Q, -Q,
I, Q, -Q, Q, -Q, -I] C point origin: [I, Q, -I, -Q, I, -I, I, Q,
-I, I, -I, I, -Q] Point D origin: [Q, -I, -Q, I, Q, -Q, Q,-
I, -Q, Q, -Q, Q, I]

Similarly, the spreading code “000001000
1011 ”, that is, a phase-rotated sequence of data“ 0 ”that is spread-encoded (although the A-point origin has been described above and will be repeated), the A-point origin: [−Q, −I, Q, I, − Q, Q, -Q,-
I, Q, -Q, Q, -Q, I] Point B origin: [I, -Q, -I, Q, I, -I, I,-
Q, -I, I, -I, I, Q] C point origin: [Q, I, -Q, -I, Q, -Q, Q, I,
-Q, Q, -Q, Q, -I] Point D origin: [-I, Q, I, -Q, -I, I, -I,
Q, I, -I, I, -I, -Q] As described above, the phase rotation modulation unit 4 includes the data spreading unit 3
Of the spread data DS input from the chip in accordance with the above rule for each chip.

Then, as a result of the encoding by the phase rotation sequence, the phase rotation modulation section 4 converts a series of phase data transiting through four phase points A, B, C and D into Q
Output to the PSK modulator / demodulator 5. At this time, for example, in the case of the point A, the data output to the I channel and the Q channel are a signal “1” and a signal “1”, respectively. In the case of the point D, data output to the I channel and the Q channel are a signal “1” and a signal “−1”, respectively. The signal “1” and the signal “−1” used here are each indicated by a predetermined voltage value, and indicate information on the amplitude of the I-channel and Q-channel signals. The QPSK modem 5
Based on the data of each of the input I-channel and Q-channel signals of the phase rotation sequence, a signal in which the phase of the carrier is modulated is generated, and the encoded signal is radiated from the antenna 6 to space as a radio wave.

Next, the details of the part of the QPSK modulator / demodulator 5 that performs the transmission process will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of the QPSK modulation / demodulation unit 5 in FIG. In this figure, the buffer 20
The buffer 21 shapes the waveform of the phase rotation sequence data input from the I channel and the Q channel, and outputs the data to the low-pass filter 22 and the low-pass filter 23, respectively. The low-pass filter 22 is a buffer 2
Unnecessary harmonics in the data signal of the I-channel phase rotation sequence input from 0 are removed and output to the amplifier 24. Similarly, the low-pass filter 23 removes unnecessary harmonics in the Q-channel phase rotation sequence data signal input from the buffer 21, and
Output to

The amplifier 24 adjusts the level of the signal of the data of the phase rotation sequence of the I channel input from the low-pass filter 22 to a predetermined value, and outputs the signal to the QPSK modulator 26. The amplifier 25 adjusts the level of the signal of the data of the phase rotation sequence of the Q channel input from the low-pass filter 23 to a predetermined value, and outputs the signal to the QPSK modulator 26. The PLL circuit 31 generates a local synthesized wave having a frequency substantially the same as that of another spread code communication device of the transmission partner by the control signal of the microcontroller 1 according to the VCO.
(Voltage-controlled oscillator). And
The switch 33 switches whether to supply the synthesized wave output from the VCO 32 to the QPSK modulation unit 26 or the QPSK demodulation unit 34 according to a control signal of the microcontroller 1.

The QPSK modulating section 26 changes the amplitude of each of the modulated signal I component and the modulated signal Q component for each chip of the spread data DS based on the input phase rotation sequence data. Also, the QPSK modulation section 26 has a VCO
The phase of the carrier is changed based on the I component of the modulation signal and the Q component of the modulation signal,
An electric signal Do (encoded signal, composite wave) of the phase-phase modulated wave is generated and output to the amplifier 27. The amplifier 27
The electric signal Do input from the SK modulator 26 is changed to a predetermined voltage and output to the low-pass filter 28. The low-pass filter 28 removes unnecessary harmonics of the electric signal Do input from the amplifier 27 and outputs the same to the switch 29.

The switch 29 determines whether the electric signal Do input from the low-pass filter 28 is output to the antenna 6 (transmission) or the electric signal Di is input from the antenna 6 to the band-pass filter 35 (reception). The control is performed by a control signal from the control unit 1. Antenna 6
Radiates the electric signal Do input from the low-pass filter 28 into the space as radio waves through the switch 29.

Next, the receiving section in the spread code communication apparatus according to the first embodiment will be described with reference to FIGS. The antenna 6 receives the radio wave, converts the electric wave into an electric signal Di (combined wave) of a four-phase modulated wave, and outputs the electric signal Di to the switch 29. The switch 29 outputs an electric signal Di input to the band-pass filter 35 according to a control signal from the microcontroller 1. The band pass filter 35 is
Only a predetermined frequency band of the input electric signal Di is passed and output to the linear amplifier 36. The linear amplifier 36 amplifies the level of the input electric signal Di within a predetermined voltage range, and outputs the amplified signal to the band-pass filter 37.

The band-pass filter 37 passes only a predetermined frequency band of the input electric signal Di,
Output to the amplifier 38. The amplifier 38 amplifies the input electric signal Di to a predetermined voltage level and outputs the amplified electric signal Di to a low-pass filter 39. The low-pass filter 39 is
An extra harmonic in the input electric signal Di is removed, and the signal is output to the QPSK demodulation unit 34 via the AGC amplifier 49.

The QPSK demodulator 34 converts the input electric signal Di into a baseband signal I (demodulated signal) which is an in-phase component and a baseband signal which is an quadrature component with respect to a local carrier generated by the VCO 32. The band signal Q (demodulated signal) is supplied to the linear amplifier 40 and the linear amplifier 41, respectively.
Output to The linear amplifier 40 amplifies the input baseband signal I to a predetermined voltage level and outputs the same to the low-pass filter 42. Similarly, the linear amplifier 41
The input baseband signal Q is amplified to a predetermined voltage level and output to the low-pass filter 43.

The low-pass filter 42 removes unnecessary harmonic components generated at the time of demodulation contained in the input baseband signal I and outputs the result to the amplifier 44. Similarly,
The low-pass filter 43 removes unnecessary harmonic components generated at the time of demodulation contained in the input baseband signal Q, and outputs the result to the amplifier 45. Amplifier 44 amplifies the input baseband signal I to a predetermined voltage level, and outputs the amplified voltage to A / D converter 46. Similarly, the amplifier 45 amplifies the input baseband signal Q to a predetermined voltage level and outputs the same to the A / D converter 47.

The A / D converter 46 converts the input baseband signal I at a predetermined sampling rate.
For example, sampling is performed at a chip rate (a transmission cycle of a chip of spread data chips), twice or four times the chip rate, and the analog voltage value of the sampled baseband signal I is converted into a digital voltage. Is converted to a value DVI, and the signal difference calculator 7 (see FIG. 1)
Output to Here, the obtained voltage signal DVI represents the amplitude of the baseband signal I at the time when it is extracted by sampling. Similarly, the A / D converter 47 converts the input baseband signal Q
Sampling is performed at a chip rate in data transmission, twice or four times the chip rate, an analog voltage value of the sampled baseband signal Q is converted to a digitally indicated voltage value DVQ, and a signal difference is calculated. Output to the arithmetic unit 7 (see FIG. 1). here,
The obtained voltage signal DVQ represents the amplitude of the baseband signal Q at the time of sampling. Here, in oversampling performed at a rate twice or four times the chip rate, whether the sampling ratio is doubled or quadrupled is selected depending on a balance between transmission / reception performance and a circuit scale. .

Next, in FIG. 1, the signal difference calculator 7
The input voltage signal DVI is subtracted from the previously sampled voltage signal DVI, and a voltage difference signal DSI is output to the matched filter 8 as a voltage difference between the two. The voltage difference signal DSI indicates a direction in which the phase of the baseband signal I is shifted (a rotation direction of the phase). That is, depending on the polarity of the subtraction result, the voltage difference signal DSI indicates whether the value of the baseband signal I sampled this time has increased, has not changed, or has decreased with respect to the baseband signal I sampled last time. Can be determined. Thereby, the signal difference calculator 7 outputs the voltage difference signal DSI as data on which the rotation direction of the phase of the received carrier wave is estimated.

The signal difference calculator 7 converts the input voltage signal DVQ into a voltage signal DV sampled last time.
It subtracts from Q and outputs a voltage difference signal DSQ to the matched filter 8 as a voltage difference between the two. This voltage difference signal DSQ
Indicates the direction in which the phase of the baseband signal Q is shifted. That is, depending on the polarity of the subtraction result, the voltage difference signal DSQ indicates whether the value of the baseband signal Q sampled this time has increased, has not changed, or has decreased with respect to the baseband signal Q sampled last time. Can be determined. Thereby, the signal difference calculator 7
Outputs a voltage difference signal DSQ as data on which the rotation direction of the received carrier wave is estimated.

Here, in FIG. 1, the signal difference calculator 7
For example, as a first operation method for obtaining the voltage difference signal DSI, the input voltage signal DVI is subtracted from the previously sampled voltage signal DVI, and the voltage difference signal DSI (variation ΔI ) Is output to the matched filter 8. At this time, the voltage signal D sampled at the sampling point in FIG.
The relation between VI and the voltage difference signal DSI is DSI1 = DVI5-DVI1 DSI2 = DVI6-DVI2 DSI3 = DVI7-DVI3...

Here, DSI1, DSI2, DSI3,...
Is a voltage difference signal D sequentially output from the signal difference calculation circuit 7.
It shows the voltage value of SI. Also, DVI1 to DVI3,
DVI5 to DVI7 are provided by the A / D converter 46 shown in FIG.
A voltage value obtained by A / D (analog / digital) conversion is shown by sampling at sampling point P1, sampling point P2, sampling point P3, sampling point P5, sampling point P7, and sampling point P7 shown in FIG. I have.

Similarly, the signal difference calculator 7 subtracts the input voltage signal DVQ from the previously sampled voltage signal DVQ as a first calculation method for obtaining the voltage difference signal DSQ, for example. Voltage difference signal D as voltage difference
SQ (change amount ΔQ) is output to the matched filter 8.
At this time, the relationship between the voltage signal DVQ sampled at the sampling point in FIG. 3A and the voltage difference signal DSQ is as follows: It has become.

Here, DSQ1, DSQI2, DSQ3,
.. Indicate the voltage values of the voltage difference signal DSQ sequentially output from the signal difference calculation circuit 7. DVQ1 to DVQ
3, DVQ5 to DVQ7 are provided by the A / D converter 47 when the sampling point PP1, the sampling point PP2, the sampling point PP3, the sampling point PP5, and the sampling point PP shown in FIG.
7, a voltage value obtained by A / D (analog / digital) conversion by sampling at a sampling point PP7.

As a second method of calculating the voltage difference signal DSI, the voltage difference signal DVI obtained by quadrupling oversampling is supplied to the signal difference calculator 7 instead of the configuration for calculating the voltage difference signal DSI described above. It is also possible to subtract from the previously sampled voltage signal DVI while thinning out at a predetermined interval, and output the voltage difference signal DSI (variation ΔI) to the matched filter 8 as the voltage difference between them. At this time, the relationship between the voltage signal DVI and the voltage difference signal DSI sampled at the sampling point in FIG. It has become.

That is, in the second operation method, unlike the first operation method, the voltage signals DVI sampled at all the sampling points are not used continuously. DVI4 and DVI1 used to determine DSI1 are not used in subsequent calculations. In this case, sampling points used for calculation are thinned out as compared with the first calculation method. According to the second calculation method, the signal difference calculator 7 can obtain the voltage difference signal DSI at a calculation speed 1/2 that of the first method (double oversampling). Here, DSI1, DSI2, DSI3,... Indicate voltage values of the voltage difference signal DSI sequentially output from the signal difference calculator 7. Also, DVI1, DVI3 to DVI
6, DVI8 is sampled by the A / D converter 46 at the sampling point P1, sampling point P3, sampling point P4, sampling point P5, sampling point P6, and sampling point P8 shown in FIG. analog/
(Digital) conversion.

Similarly, as a second operation method of the voltage difference signal DSQ, as in the above-described second operation method of the voltage difference signal DSI, the signal difference calculator 7 is obtained by four times oversampling. While thinning out the voltage signal DVQ at a predetermined interval, the previously sampled voltage signal DVQ
, And a voltage difference signal DSQ (change amount ΔQ) can be output to the matched filter 8 as a voltage difference between the two. At this time, the voltage signal DVQ sampled at the sampling point in FIG.
, And the voltage difference signal DSQ, DSQ1 = DVQ4-DVQ1 DSQ2 = DVQ6-DVQ3 DSQ3 = DVQ8-DVQ5...

That is, in the second operation method, unlike the first operation method, the voltage signals DVQ sampled at all the sampling points are not used continuously, but as shown in the above-mentioned equation. DVQ4 and DVQ1 used to determine DSQ1 are not used in subsequent calculations. In this case, sampling points used for calculation are thinned out as compared with the first calculation method. According to the second calculation method, the signal difference calculator 7 can obtain the voltage difference signal DSQ at a calculation speed 1/2 that of the first method. Here, DSQ1, DSQ2, DSQ
.. Indicate the voltage values of the voltage difference signal DSI sequentially output from the signal difference calculator 7. Also, DVQ1, DV
Q3 to DVQ6 and DVQ8 are provided by the A / D converter 47,
Sampling point PP1, sampling point PP3, sampling point PP4 shown in FIG.
Sampling point PP5, sampling point P
P6 indicates a voltage value obtained by sampling at A / D (analog / digital) conversion at the sampling point PP8.

Further, there is shown a circuit configuration in a case where sampling is performed at a rate similar to the chip rate of the baseband signal I and the baseband signal Q without oversampling. At this time, the relationship between the voltage signal DVI sampled at the sampling point in FIG. 3B and the voltage difference signal DSI is DSI1 = DVI2-DVI1 DSI2 = DVI3-DVI2...

Here, DSI1, DSI2, DSI3,...
Is a voltage difference signal D sequentially output from the signal difference calculation circuit 7.
It shows the voltage value of SI. Also, here DVI1 ~
The A / D converter 46 samples the voltage at the sampling point P1b, the sampling point P2b, the sampling point P3b,... Shown in FIG. 3B, and outputs the voltage value obtained by the A / D (analog / digital) conversion. Is shown.

Similarly, the signal difference calculator 7 subtracts the input voltage signal DVQ from the previously sampled voltage signal DVQ as a first calculation method for obtaining the voltage difference signal DSQ, for example. Voltage difference signal D as voltage difference
SQ (change amount ΔQ) is output to the matched filter 8.
At this time, the relationship between the voltage signal DVQ sampled at the sampling point in FIG. 3B and the voltage difference signal DSQ is as follows: DSQ1 = DVQ2-DVQ1 DSQ2 = DVQ3-DVQ2.

Here, DSQ1, DSQI2, DSQ3,
.. Indicate the voltage values of the voltage difference signal DSQ sequentially output from the signal difference calculation circuit 7. DVQ1 to DVQ3
Means that the A / D converter 47 determines that the sampling point PP1b and the sampling point PP2 shown in FIG.
b, sampling points PP3b,... indicate voltage values obtained by A / D (analog / digital) conversion.

However, in order to perform highly accurate decoding, A / D conversion is performed at a sampling rate (double oversampling) that is at least twice the chip rate of the baseband signal I and the baseband signal Q. It is desirable. When double oversampling is performed, the relationship between the voltage signal DVI sampled at the sampling point in FIG. 3C and the voltage difference signal DSI is as follows: DSI1 = DVI3−DVI1 DSI2 = DVI4−DVI2 DVI3---

Here, DSI1, DSI2, DSI3, DSI
.., SI4, DSI5,... Indicate the voltage values of the voltage difference signal DSI sequentially output from the signal difference calculation circuit 7. Also,
Here, DVI1 to DVI5 correspond to the A / D converter 46.
Are the sampling points P1c, P2c, and P3 shown in FIG.
c, sampling points P4c, sampling points P5c,... indicate voltage values obtained by A / D (analog / digital) conversion.

Similarly, the signal difference calculator 7 subtracts the input voltage signal DVQ from the previously sampled voltage signal DVQ as a first calculation method for obtaining the voltage difference signal DSQ, for example. Voltage difference signal D as voltage difference
SQ (change amount ΔQ) is output to the matched filter 8.
At this time, the relationship between the voltage signal DVQ sampled at the sampling point in FIG. 3C) and the voltage difference signal DSQ is as follows: DSQ1 = DVQ3−DVQ1 DSQ2 = DVQ4−DVQ2 DSQ3 = DVQ5−DVQ3. .

Here, DSQ1, DSQI2, DSQ3,
DSQI4, DSQ5,... Indicate the voltage values of the voltage difference signal DSQ sequentially output from the signal difference calculation circuit 7. The A / D converter 47 converts the DVQ1 to DVQ5 into the sampling points PP1c, PP2c, and PP3 shown in FIG.
c, sampling points PP4c, sampling points PP5c,... indicate voltage values obtained by A / D (analog / digital) conversion.

In FIG. 1, matched filter 8 encodes based on input voltage difference signal DSI and voltage difference signal DSQ by transmission data transmitted from another spread code communication apparatus, that is, encodes based on rotation direction. The decoding of the signal is performed. At this time, the matched filter 8
It is detected whether or not the data in the rotation direction matches the spread data obtained by spreading the transmission data with the voltage difference signal DSI and the voltage difference signal DSQ. Here, it is assumed that the phase rotation sequence in the encoding is indicated by paragraph number 0025 and paragraph number 0026.

That is, the matched filter 8 outputs the input data sequence DD 1 [DSI 1, DSI 2, DSI 3, D 3] of the voltage difference signal DSI input from the signal difference calculator 7 in time series.
DSI4, DSI5, DSI6, DSI7, DSI8,
DSI9, DSI10, DSI11, DSI12, DS
I13,...] And the data string [D
SQ1, DSQ2, DSQ3, DSQ4, DSQ5, D
SQ6, DSQ7, DSQ8, DSQ9, DSQ10,
, DSQ11, DSQ12, DSQ13,...], For example, each phase rotation for encoding data “1” and data “0” used for encoding by the transmitted spread code communication apparatus. The data is rearranged into a data format corresponding to the series, for example, as shown in paragraph number 0025 and paragraph number 0026.

That is, in response to the encoding of the data of "1", the data string [DSI1, DSI1
SQ2, DSI3, DSQ4, DSI5, DSI6, D
SI7, DSQ8, DSI9, DSI10, DSI1
, DSI12, DSQ13] and an input data string DD2 [DSQ1, DSI2, DS corresponding to the data string D2.
Q3, DSI4, DSQ5, DSQ6, DSQ7, DS
I8, DSQ9, DSQ10, DSQ11, DSQ1
2, DSI13]. On the other hand, in response to the encoding of the data “0”, the input data sequence D3 corresponding to the data sequence D3
D3 [DSQ1, DSI2, DSQ3, DSI4, DS
Q5, DSQ6, DSQ7, DSI8, DSQ9, DS
Q10, DSQ11, DSQ12, DSI13], and an input data string DD4 [DSI corresponding to the data string D4.
1, DSQ2, DSI3, DSQ4, DSI5, DSI
6, DSI7, DSQ8, DSI9, DSI10, DS
I11, DSI12, DSQ13].

The data sequence D1 described above indicates a phase rotation sequence indicating data "1" starting from points A and C, and the data sequence D2 indicates a phase rotation indicating data "1" starting from points B and D. The rotation sequence is shown. Similarly, a data sequence D3 indicates a phase rotation sequence indicating data “0” starting from points A and C, and a data sequence D4 indicates a phase rotation sequence indicating data “0” starting from points D and B. Is shown.

Next, the matched filter 8 multiplies each voltage difference signal by a code indicating the rotation direction of each of the phase rotation sequences corresponding to the input data sequence DD1 and the input data sequence DD2, and outputs the data of the data sequence. Is added. That is, the code {-1, -1,1,1, -1,1, -1, -1,-) of the phase rotation sequence used for encoding the data of "1" starting from the point A.
1, 1, −1, 1, −1, 1} to an input data sequence DD1 [DSI1, DSQ2, DSI
3, DSQ4, DSI5, DSI6, DSI7, DSQ
8, DSI9, DSI10, DSI11, DSI12,
DSQ13], the corresponding voltage difference signals are multiplied, and a data sequence (spread data) [-DSI1, -DSQ2, DSI
3, DSQ4, -DSI5, DSI6, -DSI7,-
DSQ8, DSI9, -DSI10, DSI11, -D
SI12, DSQ13] are added (despreading). As a result, the addition result is output as correlation data MP for matching (correlation).

Also, the code {-1, 1, 1, 1, of the phase rotation sequence used for encoding the data of "1" starting from the point B.
-1, -1,1, -1,1,1, -1,1, -1, -1,-
1} to an input data sequence DD2 corresponding to the data sequence D2.
[DSQ1, DSI2, DSQ3, DSI4, DSQ
5, DSQ6, DSQ7, DSI8, DSQ9, DSQ
10, DSQ11, DSQ12, DSI13] are multiplied by the corresponding voltage difference signals to form a data string [-DSQ1, DSI
SI2, DSQ3, -DSI4, -DSQ5, DSQ
6, -DSQ7, DSI8, DSQ9, -DSQ10,
DSQ11, -DSQ12, -DSI13]. As a result, the addition result is output as correlation data MP for matching (correlation).

Further, regarding the decoding of the encoding of the data of "1" starting from the point C, the data string D
1 multiplied by each element, the code code {1, 1, in which the polarity of the code of the phase rotation sequence with the point A as the reference for rotation is inverted.
-1, -1,1, -1,1,1, -1, -1, -1, -1,1,
-1} multiplied by each voltage difference signal of the data sequence corresponding to the input data sequence DD1 [DSQ1, DSI
2, -DSQ3, -DSI4, DSQ5, -DSQ6
DSQ7, DSI8, -DSQ9, DSQ10, -DS
Q11, DSQ12, -DSI13]. As a result, the addition result is output as correlation data MP for matching (correlation).

Similarly, regarding the decoding of the encoding of the data “1” starting from the point D, the data string D
Code {1, -1,-) obtained by inverting the polarity of the code of the phase rotation sequence based on the rotation at point B, which is obtained by multiplying each element 2
1,1,1, -1,1, -1, -1, -1,1, -1,1,1,
1} multiplied by the respective voltage difference signals of the input data sequence DD2 corresponding to the data sequence D2 [DSQ1, -D
SI2, -DSQ3, DSI4, DSQ5, -DSQ
6, DSQ7, -DSI8, -DSQ9, DSQ10,
-DSQ11, DSQ12, DSI13]. As a result, the addition result is output as correlation data MP for matching (correlation).

On the other hand, the codes {-1, -1, -1,..., Of the phase rotation sequence used for encoding the data "0" starting from the point A.
1,1, -1,1, -1, -1, -1,1, -1,1, -1,
1} to the input data sequence DD3 corresponding to the data sequence D3.
[DSI1, DSQ2, DSI3, DSQ4, DSI
5, DSI6, DSI7, DSQ8, DSI9, DSI
10, DSI11, DSI12, DSQ13} are multiplied by the corresponding voltage difference signals, and the data string [−DSI1, −
DSQ2, DSI3, DSQ4, -DSI5, DSI
6, -DSI7, -DSQ8, DSI9, -DSI1
0, DSI11, -DSI12, DSQ13]. As a result, the addition result is output as correlation data MM for matching (correlation).

Also, the code of the phase rotation sequence {-1, 1, 1, 1, used for encoding "0" data, starting from point D.
-1, -1,1, -1,1,1, -1,1, -1, -1,-
1} to the input data sequence DD4 corresponding to the data sequence D4.
[DSI1, DSQ2, DSI3, DSQ4, DSI
5, DSI6, DSI7, DSQ8, DSI9, DSI
10, DSI11, DSI12. DSQ13], the corresponding chip is multiplied, and the data string [-DSI1, DSQ
2, DSI3, -DSQ4, -DSI5, DSI6,-
DSI7, DSQ8, DSI9, -DSI10, DSI
11, -DSI12, -DSQ13]. As a result, the addition result is output as correlation data MM for matching (correlation).

Further, with respect to the decoding of the encoding of the data of “0” starting from the point C,
3, a code {1, 1, −
1, -1,1, -1,1,1, -1, -1, -1, -1,1,-
1} multiplied by the data sequence of the voltage difference signal corresponding to the input data sequence DD3 [DSI1, DSQ2, -D
SI3, -DSQ4, DSI5, SI6, DSI7, D
SQ8, -DSI9, DSI10, -DSI11, DS
I12, -DSQ13]. As a result, the addition result is output as correlation data MM for matching (correlation).

Similarly, regarding the decoding of the encoding of the data “0” starting from the point B, the data string D
4 is obtained by multiplying each element of code 4 by inverting the polarity of the sign of the code of the phase rotation sequence using point D as a reference for rotation {1, −1, −
1,1,1, -1,1, -1, -1, -1,1, -1,1,1,
1} multiplied by the data sequence of the voltage difference signal corresponding to the input data sequence DD4 [DSI1, -DSQ2,-
DSI3, DSQ4, DSI5, -DSI6, DSI
7, -DSQ8, -DSI9, DSI10, -DSI1
[1, DSI12, DSQ13]. As a result, the addition result is output as correlation data MM for matching (correlation).

As described above, the matched filter 8 is provided with a storage unit for holding data of 13 chips similar to the spread code corresponding to each starting point, and when a new chip is inputted. Is shifted by one chip in the storage unit, and the oldest chip is discarded. Then, each time a new chip is input, the matched filter 8 multiplies a code of a predetermined phase rotation sequence corresponding to the position (chip) of each storage unit to calculate the above-described correlation peak. Perform processing. That is, the correlation peak is calculated each time one chip is input. In these cases, the correlation data MP and the correlation data MM output from the matched filter 8 are positive peaks, and there is no need to take absolute values in the peak synthesis circuits 9 and 10, respectively.

At this time, when the input voltage difference signal is double oversampling and quadruple oversampling, the matched filter 8 has a processing speed (corresponding to the cycle of the chip) when oversampling is not performed. Each of them operates at twice or four times the processing speed (including the rearrangement process). Furthermore, a voltage difference signal DSI that is oversampled and input in time series
Alternatively, every time the voltage difference signal DSI and the voltage difference signal DSQ are input, the voltage difference signal DSQ is thinned out for every number corresponding to a multiple of the oversampling, and the above-described input data strings DD1 to DD4 are obtained. Form. For example, the voltage difference signal D
Assuming that the SI and the voltage difference signal DSQ are input, at the time when the voltage difference signals DSI1 to DSI26 and the voltage difference signals DSQ1 to DSQ26 are input,
The input data string DD1 is the input data string DD1 [DSI
1, DSQ3, DSI5, DSQ7, DSI9, DSI
11, DSI13, DSQ15, DSI17, DSI1
9, DSI121, DSI123, DSQ25].

Then, the voltage difference signal DSI2 to the voltage difference signal DSI27 and the voltage difference signal DSQ2 to the voltage difference signal DSQ
27, the input data string DD1 [DSI2, DS] is arranged in the arrangement of the voltage difference signals corresponding to the data string D1.
Q4, DSI6, DSQ8, DSI10, DSI12,
DSI14, DSQ16, DSI18, DSI20, D
SI122, DSI124, DSQ26]. In this way, the rearrangement is performed every two chips and every time one new chip is input. Other input data strings DD2
The input data string DD4 is processed in the same manner as the above-described processing, and the corresponding data strings D2, D3, and D
4 is composed of a sequence of voltage difference signals corresponding to the four. here,
Every time a new one chip is input, the same processing is performed regardless of whether oversampling or oversampling is performed. As described above, when oversampling is performed, the voltage difference signal DSI and the voltage difference signal DSQ that are input in time series, which are obtained by multiplying the number of chips of the spreading code by a multiple of oversampling, are accumulated, and the number of multiples of sampling is calculated. The voltage difference signal DSI and the voltage difference signal DSQ, which are decimated every time, are rearranged to generate input data strings DD1 to DD4 and perform despreading processing.

Further, as described above, the matched filter 8 uses the point A as the phase rotation reference and uses the phase rotation sequence code {-1, -1, -1, 1} used for encoding "1" data. ,
1, -1,1, -1, -1, -1,1, -1,1, -1,
1} and the code {−1, 1,} of the phase rotation sequence used for encoding the data of “1” using the point B as the phase rotation reference.
1, -1, -1, -1,1, -1,1,1, -1,1, -1,
-1} is prepared, and the decoding of the encoding using the point C as the rotation reference is performed using the point A as the rotation reference of the phase.
Regarding the decoding of the encoding using the phase rotation sequence code used for encoding the data of “1” and using the point D as the phase rotation reference, the code of the phase rotation sequence using the point B as the phase rotation reference May be used. As described above, the spread data MP based on the spreading code with the points C and D as the rotation reference of the phase is output from the matched filter 8 as a negative correlation peak. Value is taken.

As described above, the matched filter 8 uses the point A as the phase rotation reference and encodes the phase rotation sequence code {-1, -1, -1,1} used for encoding "0" data. ,
1, -1,1, -1, -1, -1,1, -1,1, -1,
1} and the code {-1, 1, 1 of the phase rotation sequence used for encoding the data of "0" with the point D as the rotation reference of the phase.
1, -1, -1, -1,1, -1,1,1, -1,1, -1,
-1} is prepared, and the decoding of the encoding using the point C as the rotation reference is performed using the point A as the rotation reference of the phase.
Regarding the decoding of the encoding using the phase rotation sequence code used for encoding the data of “1” and using the point B as the phase rotation reference, the code of the phase rotation sequence using the point B as the phase rotation reference May be used.

As described above, the spread data M by the spread code using the points C and B as the phase rotation reference
Although P is output from the matched filter 8 as a negative correlation peak, the peak synthesis circuit 9 takes an absolute value. As described above, in the matched filter 8, the correlation data MP and the correlation data MM are, as described above, if the sign and the polarity of the phase rotation sequence match (the data “1” is referred to as the point A reference and the point B reference). , The data "0" and the point A reference and the point D reference), the intensity of the correlation signal of the maximum peak of the positive value is obtained, while the rotation direction of each is completely opposite polarity (data "1"). For example, if the reference is the C point reference and the D point reference, and if the data is “0”, the C point reference and the B point reference), the intensity of the correlation signal of the maximum peak having a negative value can be obtained.

Conversely, when the polarity of the sign of each chip in the data string multiplied by the sign is disjoint in the matched filter 8, that is, data “0” and data “1” are shown. If the data is not spread data, each addition result is averaged, and the peak of the correlation value output from the matched filter 8 becomes low, not limited to a positive value or a negative value.

In the matched filter 8 described above, under the program control of the microcontroller 1,
If necessary, for example, when the combination of the data of the data sequence D1 to the data sequence D4 of the phase rotation sequence, that is, when the spreading code is changed, it can be changed so as to intersect at any register part. is there. Similarly, the code of the phase rotation sequence to be multiplied by the phase rotation sequence in the matched filter 8 may be changed, if necessary, by the program control of the microcontroller 1, for example, the data of the data sequence D1 to the data sequence D4 of the phase rotation sequence. , That is, when the spreading code is changed, the polarity setting can be changed.

In the above-described decoding, the matched filter 8 performs the phase rotation sequence using the data “1” and the data “0” in the transmission data for encoding, similarly to the case where the point A is the starting point. In the case where the starting points are set to points B, C, and D, the matching (correlation) with the phase rotation sequence is performed at each timing when each chip is transferred in time series, that is, the voltage calculated by the signal difference calculator 7. Each time the difference signal DSI and the voltage difference signal DSQ are input, they are detected, and the correlation data MP and the correlation data MM are respectively detected by the peak synthesis circuit 9,
The signals are sequentially output to the peak synthesis circuit 10. Then, the peak synthesis circuit 9 is sequentially input from the matched filter 8,
The absolute values of the correlation data MP starting from the points A, B, C, and D are taken, and all of them are added, and the added data D is obtained.
P is output to the difference calculator 11. Similarly, the peak synthesizing circuit 10 sequentially inputs A from the matched filter 8,
The absolute values of the correlation data MM starting from the point B, the point C, the point D, and the point D are taken, all of them are added, and the addition data DM
Is output to the difference calculator 11.

The difference calculator 11 sequentially outputs the peak synthesizing circuit 9
Data DP inputted from the input terminal and the peak synthesizing circuit 10
And outputs the difference signal PM to the peak detection circuit 12 as the difference. The adder 13 adds the sequentially input addition data DP and the addition data DM, and outputs the addition result TM to the peak timing circuit 14 in a time series every time the addition data DP and the addition data DM are input. ing. The above-described matched filter 8, peak synthesizing circuit 9, peak synthesizing circuit 10, and difference arithmetic unit 11 have a 2 × oversampling process, compared to a case where oversampling is not performed. Works at twice the speed. By increasing the multiple of the frequency of the oversampling with respect to the chip rate, the accuracy of decoding the spread data in the despreading is improved. When the p-times oversampling is performed, the matched filter 8, the peak synthesis circuit 9, the peak synthesis circuit 10, and the difference calculator 11
Double data processing speed is required.

The peak timing circuit 14 is provided with the difference calculator 1
1 to the peak detection circuit 12, which determines whether the input difference signal PM data is either "0" or "1".
A peak detection signal G for controlling the timing of data determination processing is output. Here, the peak timing circuit 14
Has the configuration shown in FIG. FIG. 5 is a block diagram showing a configuration of the peak timing circuit 14 in FIG. In FIG. 5, a register row RG includes a register R1.
To Rn (SRAM: storage element such as static random access memory). n is a number obtained by multiplying the number of chips of the spreading code by the number corresponding to oversampling. For example, if the number of chips of the spreading code is 13, and the peak timing circuit 14
If the frequency of the oversampling is twice the chip rate at the time of input to the data, n = 13 × 2 = 26. Here, based on the configuration of FIG. 5 described above, when oversampling is not performed, the register row RG is configured by 13 registers.

The selector 50 operates in response to the control signal Sn output from the revolving counter 51 to register R in the register row RG.
1 to select one of the registers Rn. That is, the circulation counter 51 counts from 0 to n-1. For example, if the value of the control signal Sn of the circulation counter 51 is "2", the selector 50 selects the register R3. Further, the circulation counter 51 outputs a count value indicating how many times the counting from 0 to n-1 has been performed as a control signal Sm.

The addition circuit 52 reads the stored data from the register selected by the selector 50, for example, the register R1 when the control signal Sn is "0", and reads this data and the addition result input from the adder 13. TM is added to the result, output to the register R1 via the averaging circuit 53, and stored in the register R1. The timing at which the addition result TM is input from the adder 13 coincides with the count timing of the circulation counter 51. When the next addition result TM is input, the circulation counter 51 performs one-time counting processing, and the control signal is output. The value of Sn becomes "1", and the selector 50 sets the value of the register R2.
Select Then, the addition circuit 52 adds the input count result TM and the data read from the register R2, outputs the result to the register R1 via the averaging circuit 53, and stores the result in the register R1.

As described above, at the timing when the counting result TM is input in time series, the counting circuit 52
Reads data stored in the register selected by the selector 50 by the control signal Sn, adds this data to the input addition result TM, and returns the data of the addition result to the original register. Do. Then, the adder 13 performs the process of accumulative addition for each register described above every m (m is an integer of 1 or more) based on the following equation. Cumulative value Tj = (previous cumulative value Tj + (TM0 + TM1 + ...
+ TMm-1)) / 2 The accumulated value Tj is data stored in each register, and has a relationship of 0 ≦ j ≦ n. That is, the accumulated value T1
Are stored in the register R1, the cumulative value T2 is stored in the register R2,..., The cumulative value Tn is stored in the register Rn.
Is stored in When the spread code communication apparatus starts the receiving process, the registers R1 to Rn are in a reset state, and "0" is stored.

In the above equation, TM0, TM1,...
1 is a numerical value indicating the addition result TM input from the adder 13 to the addition circuit 52. Here, m is a numerical value indicating how many times the circulation counter 51 has counted from 0 to n-1. That is, the addition circuit 52 adds the data read from each register and the addition result TM input in time series to each of the registers R1 to Rn, and outputs the data of the addition result to the same register. This is a numerical value indicating how many times the return process has been performed. The peak timing circuit 14 corrects the determination timing of the difference signal PM input in time series from the difference calculator 11 to the peak detection circuit 12, but when the peak of each chip is determined in one cycle of the spread data, accurate Since the correction timing signal G cannot be obtained,
The peak is detected by taking the average of m times and utilizing the integration effect.

For example, if m is set to “3”, the process of adding the addition result TM to each register in the register row RG is the third time when the control signal Sm output from the circulation counter 51 becomes “2”. Therefore, for example, if the control signal Sm is "2" and the control signal Sn is "0", the selector 50 selects the register R1, the addition circuit 52 reads the data of the register R1, and adds the input data to this register. The result is added to the result TM, and the added data is output to the register R1 via the averaging circuit 53. At this time, since the control signal Sm is “2”, the averaging circuit 53 averages the added data input from the adding circuit 52 as １ ／, and outputs the averaged value to the register R1 as a cumulative value T1. When the control signal Sm is other than “2”, the averaging circuit 53 keeps the input added data as it is,
That is, the data is output to the register R1 without being halved. Then, the register R1 stores the input cumulative value T1.
Then, the detection circuit 54 stores the accumulated value T1 and the value "0" of the counter control signal Sn.

Next, when the addition result TM is input from the adder 13, the circulation counter 51 performs one counting and outputs the control signal Sn as "1". And selector 5
A value of 0 selects the register R2 because the control signal Sn is "1". As a result, the addition circuit 52 reads the data of the register R2, and reads the data and the input addition result TM.
And outputs the added data to the register R2 via the averaging circuit 53. At this time, the averaging circuit 53
Since the control signal Sm is “2”, the above-mentioned added data input from the adding circuit 52 is averaged as １ ／, and is output to the register R2 as a cumulative value T2. And
The register R2 stores the input cumulative value T2. Then, the detection circuit 54 compares the accumulated value T2 with the stored accumulated value T1, and determines which is larger. At this time, when the detection circuit 54 determines that the accumulated value T2 is larger than the accumulated value T1, it deletes the accumulated value T1 and stores the accumulated value T2 and the value "1" of the counter control signal Sn.

Similarly, a cumulative value of the addition result TM input in time series from the adder 13 is sequentially calculated for a register selected by the selector 50 in accordance with the value of the control signal Sn, and the average circuit is calculated. The accumulated value is obtained as 1/2 by 53 and stored in the corresponding register. The detection circuit 5
4 determines that the newly input cumulative value is larger than the cumulative value stored as the maximum value so far, deletes the cumulative value stored as the maximum value so far, and deletes the newly input cumulative value. The value of the control signal Sn of the counter indicating the register in which the value and the accumulated value are stored is stored. Then, the circulation counter 51 outputs the control signal Sn having the value of “n−1”.
Is output, the detection circuit 54 stores the maximum value of the accumulated values T1, T2,..., Tn of the registers R1 to Rn.

Thus, the peak timing circuit 14
Can detect which of the chips in the spread code for one cycle is the timing for detecting data. Then, when the next addition result TM is input, the timing correction signal G is output to the peak detection circuit 12. The timing correction signal G indicates which of the registers R1 to Rn has the maximum peak, that is, the register R
Numerical values of the control signal Sn indicating which one of the registers 1 to Rn has the largest accumulated value are included. At this time, the circulation counter 51 performs one count, and the control signal Sn becomes “0”, and the control signal Sm also becomes “0”. Then, the peak timing circuit 14 continuously performs the process of detecting the peak timing for outputting the timing correction signal G described above.

After the timing correction signal G is input from the peak timing circuit 14, the peak detection circuit 12 outputs the control signal Sn output from the circulation counter 51 of the peak timing circuit 14 and the control signal Sn included in the timing correction signal G. When the numerical values are equal, a comparison is made between the difference signal PM input from the difference calculator 11 and a judgment level set in advance. Thereby, the peak detection circuit 12 can determine whether the correlation filter 8 detects the correlation peak (data detection position) of the time-series input voltage difference signal corresponding to the spread code, which is output in the matched filter 8, and , Even if the frequencies on the transmitting side and the receiving side are slightly different,
Since the timing correction is performed once every m times of transmission data detection, it is estimated that the maximum correlation peak of the correlation data or the correlation data DM is output. It can be determined whether the data is “0” or data “1”.

At this time, when the peak detection circuit 12 determines that the difference signal PM is larger than the determination level, the correlation data DP for “1” output from the peak synthesis circuit 9 is obtained.
Is larger than the correlation data DM for “0” output from the peak synthesizing circuit 10, and outputs the determination data of “1” (bit data of transmission data) to the Viterbi decoder 15. On the other hand, when the peak detection circuit 12 determines that the difference signal PM is smaller than the determination level, the correlation data DM for “0” output from the peak synthesis circuit 10 is:
Since the correlation data DP for “1” output from the peak synthesis circuit 9 is larger than the correlation data DP for “1”, the determination data of “0” (bit data of the serial data DC) is transmitted to the Viterbi decoder 15.
Output to Note that in the peak detection circuit 12,
A method of outputting the determination data determined as “0” or “1” to the Viterbi decoder 15 is a simple method called hard decision, but the output of the peak detection circuit 12 is increased in order to further enhance the error correction capability. A soft decision method represented by a bit value may be used.

The Viterbi decoder 15 corresponds to maximum likelihood estimation using a Viterbi decoding method for selecting a trellis path that minimizes the Hamming distance or the Euclidean distance with respect to a bit string of serial data DC input in time series. It performs error correction processing, outputs each bit of the decoded serial data DC, and outputs serial data DT to the microcontroller 1 as decoded data. The spread code communication device of the present invention performs error correction of transmission data using the above-described convolutional code, so that data communication performance is improved and a communication distance can be increased.

The intensity integrating circuit 16 includes a voltage difference signal DSI and a voltage difference signal
The sum of the absolute values of SQ is calculated by AGC (Automatic Gain Control
ol) Cumulative addition is performed over a predetermined time required for control, and the cumulative value is compared with preset comparison data that defines an upper limit value and a lower limit value of the cumulative value. When the accumulated value is larger than the upper limit value of the comparison data, the intensity integration circuit 16 reduces the gain of the AGC amplifier 49 placed before the QPSK demodulator 34, and sets the conversion rate to the range of the comparison data. Adjust to enter.

When the accumulated value is smaller than the lower limit value of the comparison data, the intensity integration circuit 16 similarly increases the gain of the AGC amplifier 49 and adjusts the conversion rate to fall within the range of the comparison data. I do.

In the spread code communication apparatus according to the first embodiment described above, on the receiving side, a local synthesized wave whose phase and frequency of the synthesized wave on the transmitting side substantially match is converted into an internal VCO.
From the electrical signal Di generated and received by the
QPSK with built-in frequency conversion circuit and quadrature demodulator
The demodulator 34 extracts the base hand signal I and the baseband signal Q. At this time, if the frequency and the phase of the independently generated synthesized waves are slightly shifted between the transmitting side and the receiving side, the baseband signal I and the baseband signal Q are in the I / Q phase plane (signal space). It is observed as an operation in which the criterion for phase determination above is rotating. However, the signal encoded on the transmitting side using the phase rotation direction as described above has the phase rotating counterclockwise or clockwise, so that the phase rotation does not stop. Even if the reference of the phase rotates and shifts as time passes on the Q phase plane, the rotation speed at the shift is smaller than the rotation speed by the phase rotation coding.
If the rotation speed is sufficiently low, the direction of the phase rotation in encoding can be determined.

In the above-described spread code communication apparatus of the first embodiment, a low C /
Even in the N state, it is possible to decode transmission data with high accuracy. That is, in the spread code communication apparatus according to the first embodiment, in the low C / N state, the noise is larger than the phase rotation modulated signal level, so that the phase rotation movement due to the noise fluctuation is dominant. Even if the phase is not rotated in accordance with the encoding on the I / Q phase plane, the noise and the encoded spread data are additive, and the center of the noise distribution is coded according to the rotation direction of the phase. In order to perform the detection so as to perform a regular shift corresponding to the converted synthesized wave, the decoded spread data is correlated with the spread code by the matched filter 8 in the matched filter 8. Since there is no need to reproduce information such as the frequency from the synthesized wave, it is possible to reproduce the transmission data even in a low C / N state, and to transmit the data from a long distance by the above-described effect. That can be reproduced transmission data from weak radio waves, it is possible to extend the communication distance.

Therefore, the spread code communication apparatus according to the first embodiment operates in the same manner as in the despreading in the spread spectrum communication, by changing the amplitude of the signal received in time series (the voltage output from the signal The correlation between the difference signal DSI and the voltage difference signal DSQ) and the spreading code makes it possible to detect each bit of the transmission data coded according to the rotation direction of the phase by the integration effect, and to accurately transmit the transmission data transmitted by the transmission side. Since reproduction is performed by decoding by the matched filter 8, the spread data input in time series can be correlated in real time for each chip, and can be synchronized in a short time with a short preamble, And the data can be reproduced at high speed by the correlation processing, and the frequency of the composite wave used for data transmission / reception can be increased. It can be used for such packet communication that require fast Do communication speed.

Further, the spread code communication apparatus according to the first embodiment defines an operation in which the phase of the encoded signal rotates counterclockwise on the I / Q phase plane as data “1”, and conversely Since the operation such that the phase rotates clockwise is defined as data "0" and coding is performed, the phase is not fixed on the I / Q phase plane, and the phase does not fly diagonally. Even when the noise fluctuation becomes dominant, even if the phase reference is rotated and shifted on the I / Q phase plane, the rotation speed of the phase shift is set to a value sufficiently smaller than the rotation speed by the phase rotation modulation. By setting the speed of the phase rotation in the encoding, it is possible to detect the rotation direction of the phase of the encoded signal as an operation of smoothly rotating left and right through a low-pass filter.

Further, since the spread code communication apparatus of the present invention performs encoding using the rotation of the phase of the carrier, the allowable level of the frequency shift of the carrier between transmission and reception can be set to a large level. Communication can be performed sufficiently with the accuracy of the crystal oscillation circuit, and a stable receiving circuit that is resistant to fluctuations in characteristics due to operating temperature can detect the rotation direction of the phase even in a low C / N state. The transmitted data can be reproduced by the despreading process by the matched filter 8.

Next, an example of an operation of transmitting transmission data in the spread code communication apparatus according to the first embodiment will be described with reference to FIGS. The microcontroller 1 transmits, for example, an 8-bit data signal DR “1, 0, 0, 0, 1, 1, 1, 1, from another circuit (not shown) as transmission data.
It is assumed that "0" has been input. Thereby, the microcontroller 1 follows the data signal DR “1,0,0,0,1,1,1,1” according to the program stored in the internal storage unit.
0 ”transmission processing is started. Then, the microcontroller 1 transmits a data signal DR “1, 0, 0, 0, 1, 1, which is parallel transmission data to be transmitted to another spread code communication device.
1, 1, 0 ”is converted to the serial data DT“ 1000111 ”.
0 "and output to the convolutional encoder 2.

Thus, the convolutional encoder 2 performs, for example, as a process of adding an error correction code, a convolution operation of each bit constituting the input serial data DT “10001110” with, for example, a plurality of preceding bits. Then, output signals [0, 1], output signals [1, 0], output signals [0,
0], output signal [1, 0], output signal [0, 0], output signal [0, 1], output signal [1, 1], output signal [0,
1] are output in time series with the output signal G0 first and then the output signal G1 later, and the serial data DC "0"
"110001000011101" to the data spreading unit 3.

The data spreading section 3 outputs the serial data DC “011000” output from the convolutional encoder 2.
"1000011101" is subjected to spectrum spreading for each bit, encoded, and output to the phase rotation modulation unit 4 as spread data DS. That is, the data spreading unit 3 outputs, for example, the serial data DC “0110001000011”.
In order from the left end of “101”, one bit input in time series is converted into a 13-chip spreading code “111110111010”.
By "0", the spectrum is sequentially spread. At this time,
Since the value of the leftmost bit is “0”, the data spreading unit 3
The spread data DS “000001” is used as the spread data.
0001011 "and the value of the second bit from the left end is" 1 ", so that the spread data D
S “11111011110100” is converted to the phase rotation modulator 4
To the order of the bits of the serial data DC (from the left end)
And output in chronological order.

Then, the phase rotation modulation section 4 outputs the spread data DS “11111011” input from the data spread section 3.
"10100" is sequentially encoded for each chip from the left end in accordance with the value of the chip. For example, based on the point A (see FIG. 2), the spread data DS “1111101”
Since the value of the leftmost chip of “110100” is “1”, the phase rotates counterclockwise, and the phase of the carrier moves from point A to point B. At this time, the phase shifts from point A to point B because the baseband signal I is reduced.
"-I". Next, since the value of the second chip from the right is also “1”, the phase rotates counterclockwise, so that the phase of the carrier moves from point B to point C. At this time, the phase shift from the point B to the point C is “−Q” in order to reduce the baseband signal Q.

Similarly, as a result of encoding for 13 chips, if the spread data DS of bits “1” in the serial data DC is “11111011110100”, when the point A is used as a reference for rotation in encoding, the point A Move from A → B → C → D → A → B → A → B → C → D → C → D
→ C → B}, and [-I, -Q, I, Q, -I, I,
-I, -Q, I, -I, I, -I, Q]. Also, in the serial data DC, since the second bit from the left end is “0”, the spread data DS is “0000010001011”. At this time, point B becomes a reference for rotation in encoding. The movement of ｛B → A → D → C → B → A → B → A → D →
C → D → C → D → A}, and [-Q, -I, Q, I,
-Q, Q, -Q, -I, Q, -Q, Q, -Q, I] are generated.

As a result, the phase rotation modulation section 4 outputs to the QPSK modulation / demodulation section 5 data of the amplitude components of the baseband signal I and the baseband signal Q corresponding to a series of phase points. Here, the phase rotation modulation unit 5 outputs the phase rotation sequence [−
I, -Q, I, Q, -I, I, -I, -Q, I, -I,
I, -I, Q], and outputs the amplitude data to the I channel and the Q channel in order from the leftmost data. That is, the phase rotation modulating unit 4 sends [1, -1, -1, 1, 1, -1, 1, -1, -1, -1,
, 1, -1, -1, -1,...], And outputs [1, 1, -1, -1, -1,.
1,1,1,1, -1, -1, -1, -1, -1, -1, -1,1,
..] Are output. The QPSK modulation / demodulation unit 5 generates a modulation signal by phase modulation based on the data sequence of the amplitude signals of each of the input I-channel and Q-channel of the phase rotation sequence, and radiates the modulation signal as a radio wave from the antenna 6 to space. I do.

Next, an example of the operation of receiving transmission data in the spread code communication apparatus according to the first embodiment will be described with reference to FIGS. The antenna 6 receives a radio wave, converts it into an electric signal Di, and outputs the electric signal Di to the QPSK modulation / demodulation unit 5. Thereby, the QPSK modulation / demodulation unit 5 outputs the electric signal Di.
To remove low frequency noise and harmonics contained in
The phase demodulation is performed independently, and two series of baseband signals I and Q are output as demodulated outputs of two reference synthesized waves having phases different by π / 2. And
The QPSK modulator / demodulator 5 converts an analog voltage value of the baseband signal Q sampled at a predetermined sampling rate into a digitally indicated voltage value DVQ,
This voltage value DVQ is output to the signal difference calculator 7, and the analog voltage value of the sampled baseband signal I is
The signal is converted into a digital voltage value DVI, and this voltage value DVI is output to the signal difference calculator 7.

Next, the signal difference calculator 7 converts the input voltage signal DVI into the previously sampled voltage signal DV.
It subtracts from I and outputs a voltage difference signal DSI to the matched filter 8 as a voltage difference between the two. Similarly, the signal difference calculator 7 subtracts the input voltage signal DVQ from the previously sampled voltage signal DVQ, and outputs a voltage difference signal DSQ to the matched filter 8 as a voltage difference between the two.

The matched filter 8 uses the voltage difference signal DSI and the voltage difference signal DSQ input in time series from the signal difference calculator 7 at points A,
Rearranged into data formats corresponding to each of the phase rotation sequences using the points B, C and D as the rotation reference, ie,
In response to the encoding of the data “1”, the input data sequence DD
1 [DSI1, DSQ2, DSI3, DSQ4, DSI
5, DSI6, DSI7, DSQ8, DSI9, DSI
10, DSI11, DSI12, DSQ13] and an input data string DD2 [DSQ1, DSI2, DSQ3, D
SI4, DSQ5, DSQ6, DSQ7, DSI8, D
SQ9, DSQ10, DSQ11, DSQ12, DSI
13], and in response to the encoding of the data “0”, the input data sequence DD3 [DSQ1, DSI2, DSQ3, DQ3
SI4, DSQ5, DSQ6, DSQ7, DSI8, D
SQ9, DSQ10, DSQ11, DSQ12, DSI
13] and an input data string DD4 [DSI1, DSQ
2, DSI3, DSQ4, DSI5, DSI6, DSI
7, DSQ8, DSI9, DSI10, DSI11, D
SI12, DSQ13].

Here, when the point A is the starting point, the phase rotation sequence used by the transmitting spread code communication apparatus for encoding the data of "1" in the transmission data is [-I, -Q, I,
Q, -I, I, -I, -Q, I, -I, I, -I, Q]
And the phase rotation sequence used for encoding the data “0” is [−Q, −I, Q, I, −Q, Q, −Q, −I, Q, −
Q, Q, -Q, I], and paragraphs 0025 and 002.
6, the matched filter 8 generates the voltage difference signal DSI and the voltage difference signal DSQ input in time series.
, The correlation value of the transmitted encoded data sequence is detected. At this time, the matched filter 8 outputs the data string D1, the data string D2, the data string D3, and the data string D3.
The numerical value of the voltage difference signal is multiplied by the code indicating the rotation direction of each of the phase rotation sequences corresponding to 4 and the numerical value of the voltage difference signal corresponding to the chip of the data sequence is added for each data sequence.

That is, for example, the starting point is point A.
Code of phase rotation sequence used for encoding data of "1" {-1, -1,1,1, -1, -1, -1, -1, -1,1,-
[1,1, -1,1] to the input data sequence DD1 [DSI
1, DSQ2, DSI3, DSQ4, DSI5, DSI
6, DSI7, DSQ8, DSI9, DSI10, DS
I11, DSI12, DSQ13], and multiply the data by the data string [-DSI1, -DSQ2, DS
I3, DSQ4, -DSI5, DSI6, -DSI7,
-DSQ8, DSI9, -DSI10, DSI11,-
DSI12, DSQ13]. As a result, the addition result is output as correlation data MP for matching (correlation).

Similarly, when the starting point is point A, "0"
Of the phase rotation sequence used to encode the data
-1,1,1, -1,1, -1, -1, -1,1, -1,1,1,
−1, 1} to the input data sequence DD3 [DSI1, DSQ
2, DSI3, DSQ4, DSI5, DSI6, DSI
7, DSQ8, DSI9, DSI10, DSI11, D
SI12, DSQ13], and multiply the data strings [-DSI1, -DSQ2, DSI3, D
SQ4, -DSI5, DSI6, -DSI7, -DSQ
8, DSI9, -DSI10, DSI11, -DSI1
2, DSQ13].
As a result, the addition result is output as correlation data MM for matching (correlation).

In the above-described decoding, similarly to the case where the point A is the starting point, the reference of rotation in the phase rotation sequence using data “1” and data “0” in the transmission data for encoding is point B, Matching (correlation) with the phase rotation sequence at points C and D is detected, and correlation data MP and correlation data MM are output to the peak synthesis circuit 9 and the peak synthesis circuit 10, respectively. As a result, even if the signal level of the input data is buried in the noise level, as a result of the despreading in the spread spectrum communication, the amount of rotation change in the time series of the received signal and the rotation direction corresponding to the spreading code By taking a correlation with, the integration effect can be obtained, and the peak of the received transmission data can be detected.

That is, in the matched filter 8,
Since the spread data having a weak signal level has a high correlation with the spreading code, a signal level sufficiently higher than the noise level can be obtained as a correlation peak. If a high correlation cannot be obtained in the matched filter 8, the spread data is averaged, and a low correlation peak is output.

The peak synthesizing circuit 9 takes the absolute values of the correlation data MP starting from the points A, B, C, and D, which are input from the matched filter 8, and adds them all. And outputs the addition data DP to the difference calculator 11. Similarly, the peak synthesizing circuit 10 takes the absolute values of the correlation data MM input from the matched filter 8 and having the points A, B, C, and D as starting points, and adds all of them to add. The data DM is output to the difference calculator 11. This makes it possible to increase the data level of the correlation peak with respect to the noise level.

Further, the peak synthesizing circuit 9 calculates the points A, B,
The correlation data having the maximum value among the correlation data MP starting from the points C and D may be output as the maximum data DP. Similarly, the peak synthesizing circuit 9 outputs points A, B,
The correlation data having the maximum value among the correlation data MM starting from the points C and D may be output as the maximum data DM. Thereby, the correlation data having the highest correlation peak data level, that is, the correlation data having the highest correlation can be used in the next difference calculator 11. As described above, the spread code communication apparatus according to the present invention is capable of providing the spread code communication apparatus even if the reference coordinate axes of the I / Q phase plane indicating the phases of the carrier waves on the transmitting side and the receiving side are shifted with time (the carrier wave by the VCO 32). (The variation of the frequency over time), and the determination timing for determining the correlation peak difference signal PM is always corrected, so that the value of the transmission data can be accurately decoded.

Next, the difference calculator 11 sequentially adds the added data (maximum data) DP inputted from the peak synthesizing circuit 9.
And the difference between the sum data (maximum data) DM input from the peak synthesis circuit 10 and the difference signal PM as the difference.
Is output to the peak detection circuit 12. At the same time, adder 13
Are sequentially inputted addition data DP and addition data DM
Is added, and the addition result TM is output to the peak timing circuit 14 in time series each time the addition data DP and the addition data DM are input.

At this time, the peak timing circuit 14
The timing at which the addition result TM input from the difference calculator 11 is cumulatively added for each chip unit of the spread data over m periods of the spread data, and the peak detection circuit 12 makes a determination,
That is, the difference signal PM is “0” in bit units of the transmission data.
Or the timing of determining whether the value is “1” is m
Correction is made for each cycle. In the matched filter 8, the correlation peaks between the spread code and the input voltage difference signal DSI and voltage difference signal DSQ are determined at points A and B with respect to data "0" and data "1" in the transmission data. point,
The phase rotation sequence is output with the point C and the point D as the starting point of the phase rotation. At this point, the timing of the correlation peak in one cycle of the spread data is unknown.

Therefore, as described above, in the peak detection circuit 12, at the timing of the chip where the correlation peak appears in one cycle of the spreading code, the difference signal PM and
A comparison is made with a previously set determination level to determine whether the difference signal PM from the difference calculator 11 is data “0” or data “1” in the transmission data. At this time, the peak detection circuit 12 compares the preset level of data “0” and the level of data “1” with the difference signal PM, and determines whether the correlation data is “0” or “1”. Is determined.

However, as for the relationship between the frequencies of the synthesized waves on the transmitting side and the receiving side, the receiving side has
Since it is not known which of the points, points B, C and D is the starting point of the phase rotation, the difference signal PM
It is necessary to detect the timing of determining whether the data is “0” or “1”. In addition, the frequency of the system clock, which is the processing speed of the receiving side, and the frequency of the transmitting side are approximately one. Since the determination timing detected above shifts with the passage of time, the shift in the determination timing for determining the difference signal PM is greater than or equal to an allowable value. I have. Accordingly, the receiving side uses the internally generated local chip rate (frequency: corresponding to the system clock of the microcomputer) which substantially matches the transmitting side, thereby determining the correlation data PM over time. Even if the timing is shifted, it is possible to correct the difference in the determination timing in real time. At this time, if the deviation of the determination timing becomes large, the actual correlation peak portion is not determined, and accurate determination cannot be performed.

For example, at this time, if the transmitting side sequentially transmits the serial data DC “0110001000011101”, the peak detection circuit 12 sequentially converts the difference signal PM input from the difference calculator 11 to “0” at the above determination timing. ”Or data“ 1 ”, and as a result of the determination, data“ 1 ”, data“ 0 ”,..., Data“ 0 ”are determined from the left end, respectively, and the serial data DC“ 011000100001
1101 "to the Viterbi decoder 15. (Alternatively, a multi-bit soft decision output is performed instead of the hard decision that determines “0” and “1”.)

Then, the Viterbi decoder 15 sequentially decodes and inputs the serial data DC “011000”.
Each bit of the transmission data of "1000011101" is input, a predetermined number of bits are accumulated, and a signal obtained as the next signal is obtained by using a Viterbi decoding method of selecting a trellis path that minimizes the Hamming distance or the Euclidean distance. The correct state is estimated from the combination with the stored signal, and serial data DT as transmission data is output to the microcontroller 1. For example, "010101010
After the preamble signal of "1", the serial data DC
When each bit of “0110001000011101” is sequentially input from the left end, the Viterbi decoder 15
As the decoding result, the serial data DT [1000111]
0] from the left end to the microcontroller 1.
Then, the microcontroller 1 converts the input serial data DT [1, 0, 0, 0, 1, 1, 1, 0] into
Output to an external circuit at a predetermined timing.

Although the first embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and a design within a range not departing from the gist of the present invention. Modifications and the like are included in the present invention. For example, a second embodiment having the configuration shown in FIG. 6 may be adopted. That is, the spread code communication apparatus according to the second embodiment is configured to perform the spread spectrum multiple times in the first embodiment,
For example, the configuration is such that the phase rotation sequence in the first embodiment is the first spreading sequence, and the second spreading sequence is used to further increase the spreading factor and improve the reception performance.
In the configuration of the second embodiment, components having the same configuration as that of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

At this time, as the operation on the transmitting side, the convolutional encoder 2 performs Viterbi encoding of the serial data DT from the microcomputer 1 and converts the serial data DT from the microcomputer 1 into serial data DC to the data spreading unit 17 as in the first embodiment. Output. Then, as shown in FIG.
One bit of the transmission data is spread with, for example, a 13-chip second spreading code “11111100110101”. At this time, the second spreading code used is an M sequence (Maximum Length Co).
A spreading code such as de), Gold sequence, or Barker sequence having good autocorrelation characteristics is suitable.

The data spreading section 17 outputs the spread transmission data, that is, serial data DD, to the data spreading section 3 sequentially in chip units. Thus, the data spreading unit 3 spreads each chip of the input spread data DD with the first spreading code, that is, the spreading code that generates the same phase rotation sequence as in the first embodiment.
Encoding is performed as a phase rotation sequence as in the first embodiment. At this time, the first spreading code used is:
It is desirable that a sequence having good autocorrelation characteristics be selected and used when combining phase rotation. Then, the data diffusion unit 3
Outputs the spread data to the phase rotation modulation unit 4. Here, from the subsequent processing in the data diffusion unit 3,
The processing until the QPSK modulation / demodulation unit 5 radiates radio waves via the antenna 6 is the same as in the first embodiment, and a description thereof will be omitted.

Next, as the operation on the receiving side, the operation from the reception of the radio wave by the antenna 6 to the output of the spread data DD by the peak detection circuit 12 is the same as the operation of receiving the radio wave by the antenna 6 of the first embodiment. After that, the peak detection circuit 1
2 (including processing of oversampled voltage difference signals in signal difference calculator 7, matched filter 8,..., Peak detection circuit 12, and peak timing circuit 14). Therefore, the description is omitted. At this time, the despreading in the matched filter 8 is performed using the same first spreading code as in the first embodiment. However, the peak detection circuit 12
Does not judge whether the difference signal PM is “0” or “1”, and keeps the information of the difference signal PM having the maximum peak corresponding to the first spreading code, D
D is output to the matched filter 18.

Then, the matched filter 18 sequentially
Despreading of the input spread data DD is performed by the second spread code, and correlation data is output to the peak detection circuit 30 for each chip. Here, as shown in FIG. 8, the matched filter 18 has a spread code of 13 chips.
Registers, that is, registers SR1 to SR
Reference numeral 13 denotes a shift register SR connected in series. Each time a chip of spread data DD is inputted, the shift register SR is shifted rightward by one chip. FIG. 8 is a block diagram showing a configuration of the matched filter 18 in FIG. The chip value stored in the register SR13 is discarded because the shift register shifts the data of each register rightward when the new chip value is input to the register SR1. Then, the registers SR1 to S
Multipliers G1, G2, and G3 correspond to each register of R13.
, G12, G13 are provided. The code corresponding to the spreading code set in each multiplier is multiplied by the value of the chip stored in the register and output to the correlation adder 100.

For example, if the spectrum is spread by a 13-chip second spreading code “11111100110101”, a code string {1, 1, 1, 1, 1, −1, −1 corresponding to the second spreading code is obtained. , 1,1, -1,
1, −1, 1} are input in chronological order, multiplied by each of the 13 chips of the spread data DD stored in each register, and the result of each multiplication is calculated by the correlation adder 100.
Output to Then, the correlation adder 100 includes a multiplier G
1 to the multiplication result input from the multiplier G13,
The signal is output to the peak detection circuit 30 as a correlation peak.

Accordingly, the matched filter 18 outputs the obtained correlation data to the peak timing circuit 19 every time each chip of the spread data DD is input. Therefore, the matched filter 18 outputs 1 of the spread data DD.
Each time a chip is input, one cycle of the spreading code (13
In the result of addition (i.e., the integration result) of the respective multiplied values of (chip), a positive correlation peak is output when the data corresponds to data "1", and a negative correlation peak is output when the data corresponds to data "0". The correlation peak is output. Further, when the spread data DD is input with a disperse value with respect to the spread code, an addition result (integration result) of the multiplied values is averaged, and no correlation peak is output.

In FIG. 6, a peak timing circuit 19
Detects the determination timing by accumulating the correlation data in the same manner as the peak timing circuit 14, and outputs the determination timing to the peak detection circuit 30 as a determination timing signal. The detection of the determination timing in the peak timing circuit 19 is performed by the peak timing circuit 1
As in the case of No. 4, the process is performed for each of a plurality of cycles (m cycles) of the chip spread by the first spreading code.

The peak detection circuit 30, like the peak detection circuit 12, applies a predetermined chip of a cycle of the first spread code to the predetermined chip based on the determination timing corrected for each of a plurality of cycles from the peak timing circuit 19. At the corresponding determination timing, the preset data “0”
And the level of data “1” are compared with the correlation data, and it is determined whether the correlation data is “0” or “1”. As a result, the peak detection circuit 30 outputs the determined data to the serial data D.
As C, it is output to the Viterbi decoder 15. Subsequent processing is the same as in the first embodiment, and a description thereof will not be repeated.

As described above, the spread code communication apparatus according to the second embodiment has the same effect as that of the first embodiment, and the overall spreading factor in the communication processing is equal to the first spreading code and the first spreading code. 2 and a spreading code of, for example, 13 chips.
Eventually, one bit of data becomes a 169 spread chip (see FIG. 7), and it is possible to configure a correlation circuit (matched filter circuit) that obtains a large spreading factor with a relatively small-scale circuit. It also has the effect. For this reason,
The second embodiment uses the matched filter 8 and the matched filter 18 for despreading of spread data,
Efficient data communication that does not require a redundant header or the like in intermittent packet communication or the like can be realized.

In addition, the spread code communication apparatus according to the second embodiment can increase the spreading factor of transmission data by a relatively small-scale circuit. Since the integration of the potential difference signal DSI and the potential difference signal DSQ) is performed in two stages, that is, the first spreading code and the second spreading code, the level of the received signal can be increased (extracted). Since the transmission data can be received even in a low C / N state buried in, the range in which data can be transmitted can be expanded (communication distance can be extended).

In the first and second embodiments described above, the composite wave signal of the input analog signal is converted into an A / D converter 46 and an A / D converter 4.
7, a correlation operation or the like is performed as a digital signal. However, in the first and second embodiments, an analog matched filter circuit based on a sample-and-hold circuit or the like that samples an analog signal and holds data as it is as a sampled analog signal The same effect as the above-described effect can be obtained by applying the above.

Further, in a digital circuit, as a third embodiment, in particular, the matched filter 18 in the second embodiment is replaced by a sliding correlator 55 shown in FIG.
It can be configured in place of. FIG. 9 is a block diagram illustrating a configuration of a sliding correlator used as a correlator that performs despreading, instead of the matched filter 18 according to the second embodiment. At this time, the sliding correlator 55 shown in FIG. 9 is replaced with the matched filter 18. The peak detection circuit 30 and the peak timing circuit 19 perform the same processing as in the second embodiment, and determine the correlation peak from the sliding correlator 55.

Since the spreading code has 13 chips, the code shift register 50 has a code string {-1, 1, -1, 1, 1, 1, -1, -1, -1 of a code corresponding to each chip. ,
−1, −1, 1, 1} are stored, and the output terminal is a cyclic shift register connected to the input terminal.
By shifting (circulating) the code sequence one bit at a time, the code is output to the sliding correlator 55 in the order of the code sequence (from the left end to the right end). The code shift register 50 shifts thirteen times, so that the code sequence circulates. Therefore, the code shift register 50 returns to the initial state, that is, the sequence of the code sequence.

The sliding correlator 55 includes an integrating circuit 60 (not shown) therein, and outputs the signal while rotating the code shift register 50 once each time one chip is input from the peak detection circuit 12 to the spread data DD. The multiplication data is input and multiplied, and the multiplied data is added to the accumulation circuit 60 and accumulated.

That is, the sliding correlator 55
For example, if the code shift register 50 is in the initial state and a chip of the spread data DD is input, and if a code "-1" is input from the code shift register 50, "-1" is input to this chip to the integrating circuit 60. , Add and accumulate. When the code shift register 50 shifts by one chip and outputs the second code “1”, the sliding correlator 55 adds the “1” to the chip of the second input spread data by the integrating circuit 60. The multiplication is performed, and the multiplication result is added to the accumulation circuit 60 and accumulated.

As described above, the sliding correlator 5
5 is a code string from the code shift register 50 to a chip string of the sequentially input spread data DD.
1,1,1, -1, -1, -1, -1, -1, -1,1,1}
Are sequentially multiplied, and the result of the multiplication is added to the integrating circuit 60 and accumulated.

When the code shift register 50 shifts by one bit and outputs the last code "1", the sliding correlator 55 multiplies the last chip of the 13 chips of the spread data DD by "1". Then, the multiplication result is added to the accumulation circuit 60 and accumulated. This means that the integrating circuit 60 has added the data obtained by multiplying the data of the chips of the thirteen pieces of spread data DD by the respective codes.
Peak detection circuit 30 using integrated data as correlation data MP
Output to Then, the sliding correlator 55 deletes the data stored in the integrating circuit 60 and sets the data to “0”. By repeating the above-described processing, the sliding correlator 55 performs despreading by multiplying the spread data DD input in time series from the P-notation detection circuit 12 by the code of the code string.

Then, the peak timing circuit 19 compares the absolute value of the correlation peak and a preset value for one cycle of the second spreading code (the second spreading code) in order to detect the timing of determining the correlation peak. The cumulative addition (integration process) of the diffusion data DD corresponding to the code chip number) is completed, and the accumulated values are sequentially compared for each storage unit to be reset, and the absolute value of the peak is set in advance. It is determined whether the value is greater than the value. At this time, when the spread data DD has a correlation of data “1” with respect to the second spread code, the matched filter 18 outputs a positive (+) signal.
The correlation peak of the value of is output. On the other hand, when the spread data DD has a correlation of data “0” with respect to the second spread code, the matched filter 18 outputs a correlation peak of a negative (−) value. Then, the peak detection circuit 30 determines whether the value of the input correlation peak is data “0” or data “1”, and sequentially determines the determination result (ie, “0” of the despread result). Is output as serial data DC to the Viterbi decoder 15 (see FIG. 6). The third embodiment has the same effects as those of the first and second embodiments in a spread code communication apparatus. In addition, when a high-speed correlation operation is not required, the above-described sliding is performed. The use of the correlator simplifies the circuit configuration of the correlator part, so that the circuit scale can be reduced and the power consumption during correlation can be greatly reduced.

[0137]

According to the spread code communication apparatus of the present invention, since a carrier frequency correction circuit is not required between the transmitting and receiving apparatuses, the required C / N level can be reduced by the effect of the spread rate of the spread spectrum. As a result, the communication distance can be increased with the same transmission intensity. In addition, since the encoding is performed using the rotation of the phase of the synthesized wave, the allowable level of the frequency deviation of the synthesized wave between transmission and reception can be set to a large level. This makes it possible to configure a stable receiving circuit that is resistant to fluctuations in characteristics due to operating temperature. According to another spread code communication apparatus of the present invention, by performing two-stage spread spectrum, it is possible to increase the spreading factor in a relatively small-scale data spreading circuit. Since the level of the signal can be increased, transmission data can be received even in a low C / N state buried in noise, and communication is intermittent by using a matched filter for despreading of spread data. Efficient data communication that does not require a redundant header or the like in packet communication or the like can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a spread code communication device according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram showing encoding based on chip values of phase rotation modulation.

FIG. 3 is a conceptual diagram showing a sampling process of a baseband signal I or a baseband signal Q.

FIG. 4 is a block diagram showing a configuration of a QPSK modulation / demodulation unit 5 in FIG.

FIG. 5 is a block diagram showing a configuration of a peak timing circuit 14 in FIG.

FIG. 6 is a block diagram illustrating a configuration example of a spread code communication device according to a second embodiment of the present invention.

FIG. 7 is a conceptual diagram illustrating the concept of two-stage spread spectrum in the second embodiment.

8 is a block diagram illustrating a configuration of a matched filter 18 in FIG.

FIG. 9 is a block diagram showing a configuration of a sliding correlator used as a correlator instead of the matched filter 18 in FIG. 6 in the third embodiment.

FIG. 10 is a conceptual diagram illustrating a reference deviation of an I / Q phase plane between a transmitting side and a receiving side.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Microcontroller 2 Convolutional encoder 3,17 Data spreading part 4 Phase rotation modulation part 5 QPSK modulation / demodulation part 6 Antenna 7 Signal difference calculator 8,18 Matched filter 9,10 Peak synthesis circuit 11 Difference calculator 12,30 Peak detection Circuit 13 Adder 14, 19 Peak timing circuit 15 Viterbi decoder 16 Intensity integration circuit 20, 21 Buffer 22, 23, 28, 39, 42, 43 Low-pass filter 24, 25, 27, 38, 44, 45 Amplifier 29, 33 Switch 35, 37 Band-pass filter 36, 40, 41 Linear amplifier 26 QPSK modulator 34 QPSK demodulator 46, 47 A / D converter 49 AGC amplifier

Claims (5)

[Claims] 1. A data spreading means for spreading transmission data with a predetermined spreading code and outputting the spread data as spread data, an encoding means for coding the spread data in a rotation direction of a phase of a waveform, and outputting as a coded signal. A transmitting device having transmitting means for transmitting the coded signal; receiving means for receiving the coded signal; decoding means for obtaining the spread data from the rotation direction of the phase of the coded signal; and the spread data. And a despreading means for despreading the transmission data based on the spreading code to reproduce the transmission data. 2. The decoding means extracts a phase of the coded signal in a time series, detects a rotation direction of the extracted phase based on a phase of a coded signal received immediately before, and 2. The spread code communication device according to claim 1, wherein the spread data is output using the direction as data. 3. The despreading means decodes the rotation direction data input in time series, respectively, based on a predetermined rule, and calculates the correlation between the decoded rotation direction data and the spreading code. 3. The spread code communication apparatus according to claim 1, wherein the transmission data is reproduced by detecting and despreading. 4. The spread code communication according to claim 1, wherein said despreading means performs despreading of said spread data by a matched filter based on said spread code. apparatus. 5. A first data spreading means for spreading transmission data by a predetermined first spreading code and outputting the spread data as first spread data;
A second data spreading unit that spreads the second spread data as a second spread data, and an encoding unit that codes the second spread data according to the rotation direction of the phase of the waveform, and outputs the second spread data as a coded signal. A transmitting device having transmitting means for transmitting the coded signal; a receiving means for receiving the coded signal; a decoding means for obtaining the spread data from a rotation direction of a phase of the coded signal; 2 for despreading the second spread data based on the second spread code and reproducing the first spread data.
And a first despreading means for despreading the first spread data based on the expanded first spreading code and reproducing the transmission data. Communication device.