JP2001144196A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-performance and reliable semiconductor device that can reduce collector diffusion resistance, without impairing the reliability of a transistor. SOLUTION: On a semiconductor substrate 1, an NPN transistor (a region 1A) and a MOS transistor (a region 1B) are mounted mixedly. In the collector take-out region (plug-in diffusion layer 4) of the NPN transistor, a recessed part 4A is provided, thus forming a collector at a lower position than an emitter and a base. Also, a diffusion layer 12 is formed, where the diffusion layer 12 is the same as the source/drain diffusion layers 23 and 24 of the MOS transistor which are formed simultaneously, thus reducing the spacing between a collector take-out electrode 9 and an impurity region below the electrode 9, and at the same time, increasing the concentration of impurities directly below the electrode, and hence reducing collector diffusion resistance without having to add manufacturing processes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an element structure for improving characteristics of an NPN transistor, and a method of manufacturing a semiconductor device for obtaining the element structure.

[0002]

2. Description of the Related Art FIG. 4 is a cross-sectional view showing a structure of a conventional semiconductor device on which an NPN transistor is mounted. This semiconductor device includes an N + buried layer 20, an epitaxial layer 30, and a plug-in diffusion layer 4 in a semiconductor substrate 10 corresponding to an NPN transistor region formed on the semiconductor substrate 10.
0, an isolation diffusion layer 120 is provided. In addition, the base diffusion layer 5
0A and a graft base diffusion layer 50B are provided, and an emitter diffusion layer 60 is provided above the base diffusion layer 50A.

On the upper surface of the semiconductor substrate 10, two layers of S
The iO 2 -based insulating films 70A and 70B are formed.
A base extraction electrode 80 is provided at a position corresponding to the graft base diffusion layer 50B and a collector extraction electrode 90 is provided at a position corresponding to the plug-in diffusion layer 40 so as to penetrate the two-system insulating films 70A and 70B. . An emitter electrode portion 100 is formed in an upper layer of the emitter diffusion layer 60, and an emitter extraction electrode 110 is formed corresponding to the emitter electrode portion 100 so as to penetrate the insulating film 70B.

[0004]

By the way, in the NPN transistor having the above-described structure, the saturation voltage, which is one of the transistor characteristics, is related to the collector diffusion resistance. The lower the collector diffusion resistance, the lower the saturation voltage. Thus, the minimum operating voltage of the transistor can be reduced. Therefore, increasing the collector concentration and the plug-in diffusion layer concentration is an effective means. On the other hand, if the concentration of the collector and the concentration of the plug-in diffusion layer are increased, crystal defects are generated, which causes a problem in reliability. Therefore, the diffusion layer is formed under the condition that no crystal defects occur. However, as the performance of the transistor is improved, it is necessary to further reduce the collector diffusion resistance.

Accordingly, an object of the present invention is to reduce the collector diffusion resistance without impairing the reliability of the transistor,
An object of the present invention is to provide a semiconductor device with high performance and high reliability.

[0006]

In order to achieve the above object, the present invention provides a semiconductor device having a MOS transistor and an NPN transistor mounted on a semiconductor substrate, wherein the semiconductor substrate has a collector extraction region for the NPN transistor. Having a recess, wherein the collector extraction electrode of the NPN transistor is an emitter extraction electrode;
And formed at a position lower than the base extraction electrode.

In the semiconductor device of the present invention as described above, N
By providing a collector extraction electrode in a recess formed in the collector extraction region of the PN transistor, the collector extraction electrode is formed at a position lower than the emitter extraction electrode and the base extraction electrode. Therefore, the diffusion layer of the collector extraction region provided in the semiconductor substrate is arranged in a state close to the collector extraction electrode. As a result, the collector diffusion resistance can be reduced without impairing the reliability of the transistor. Become.

The present invention is also a method of manufacturing a semiconductor device in which an NPN transistor is mounted on a semiconductor substrate together with a MOS transistor.
A first step of forming a gate insulating film by patterning the first interlayer insulating film, opening an area where the MOS transistor is to be formed, and forming the first interlayer insulating film. A second step of patterning the film to open an emitter take-out window and a collector take-out window of the NPN transistor; forming a semiconductor film over the entire surface of the semiconductor substrate; patterning the semiconductor film to form the MOS transistor; A third step of forming a gate electrode portion, an emitter electrode portion of the NPN transistor, and forming a concave portion in the collector extraction region; and forming an impurity in the source and drain regions of the MOS transistor and the collector extraction region of the NPN transistor. And covering the entire surface of the semiconductor substrate with a second interlayer insulating film. A fifth step of patterning the two interlayer insulating films to open connection holes respectively facing the source and drain extraction regions of the MOS transistor, the emitter electrode portion, the base extraction region, and the collector extraction region of the NPN transistor; A sixth step of forming each extraction electrode for filling each connection hole, forming a concave portion in the collector extraction region in the third step, and replacing the collector extraction electrode of the NPN transistor with an emitter extraction electrode; And formed at a position lower than the base extraction electrode.

In the method of manufacturing a semiconductor device of the present invention as described above, the collector extraction electrode is provided in the concave portion formed in the collector extraction region of the NPN transistor, so that the collector extraction electrode becomes the emitter extraction electrode and the base extraction electrode. It is formed at a lower position. Therefore, the diffusion layer of the collector extraction region provided in the semiconductor substrate is arranged in a state close to the collector extraction electrode. As a result, the collector diffusion resistance can be reduced without impairing the reliability of the transistor. Become. Also, the gate electrode portion of the MOS transistor,
In addition, in the process of forming the emitter electrode portion of the NPN transistor, a concave portion can be formed in the collector extraction region, so that the collector diffusion resistance can be reduced without adding a manufacturing process. Further, in the step of introducing impurities into the source and drain regions of the MOS transistor, the impurities can be introduced into the collector extraction region of the NPN transistor at the same time, so that the collector diffusion resistance can be more effectively reduced without adding a manufacturing step. Become.

The present invention is also a method of manufacturing a semiconductor device having an NPN transistor mounted on a semiconductor substrate,
A first step of forming a first interlayer insulating film on the semiconductor substrate and patterning the first interlayer insulating film to open an emitter extraction window and a collector extraction window of the NPN transistor; A semiconductor film is formed on the entire surface of the substrate, and the semiconductor film is patterned to form the NP.
While forming the emitter electrode portion of the N transistor,
A second step of forming a recess in the collector extraction region;
A third step of introducing an impurity into the collector extraction region of the NPN transistor, and covering the entire surface of the semiconductor substrate with a second interlayer insulating film, patterning the first and second interlayer insulating films, A fourth step of opening a connection hole facing each of the emitter electrode portion, the base extraction region, and the collector extraction region of the NPN transistor; and a fifth step of forming each extraction electrode filling the connection hole, In the second step, a concave portion is formed in the collector extraction region, and the collector extraction electrode of the NPN transistor is formed at a position lower than the emitter extraction electrode and the base extraction electrode.

In the method of manufacturing a semiconductor device according to the present invention as described above, the collector extraction electrode is provided in the concave portion formed in the collector extraction region of the NPN transistor, so that the collector extraction electrode becomes the emitter extraction electrode and the base extraction electrode. It is formed at a lower position. Therefore, the diffusion layer of the collector extraction region provided in the semiconductor substrate is arranged in a state close to the collector extraction electrode. As a result, the collector diffusion resistance can be reduced without impairing the reliability of the transistor. Become. Further, in the step of forming the emitter electrode portion of the NPN transistor, a concave portion can be formed in the collector extraction region, so that the collector diffusion resistance can be reduced without adding a manufacturing step.

[0012]

Embodiments of a semiconductor device according to the present invention will be described below. In recent years, many semiconductor integrated circuits have a bipolar transistor and a MOS transistor mixedly mounted. In this embodiment, however, the advantage is taken advantage of by placing the collector extraction region of the NPN transistor at a position lower than the emitter or base. By forming the same diffusion layer as the source / drain diffusion layer of the MOS transistor formed at the same time, the collector diffusion resistance can be reduced without adding a manufacturing process. That is, according to the present embodiment, the distance between the collector extraction electrode and the impurity region can be reduced, and the impurity concentration immediately below the electrode can be increased, and the collector diffusion resistance can be reduced as compared with the conventional example. Becomes possible. Thus, a high-performance and highly reliable semiconductor device can be provided.

FIG. 1 shows an NPN according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a structure of a semiconductor device including a transistor and an NMOS transistor. This semiconductor device includes an NPN transistor region 1A formed on a semiconductor substrate 1.
The semiconductor substrate 1 has an N + buried layer 2, an epitaxial layer 3, and a plug-in diffusion layer 4. A base diffusion layer 5A and a graft base diffusion layer 5B are provided on the upper layer of the epitaxial layer 3, and the base diffusion layer 5A
An emitter diffusion layer 6 is provided in the upper layer.

On the upper surface of the semiconductor substrate 1, two layers of S
The iO 2 -based insulating films 7A and 7B are formed, and a base extraction electrode 8 is provided at a position corresponding to the graft base diffusion layer 5B so as to penetrate the SiO 2 -based insulating films 7A and 7B. In addition, a concave portion 4A is formed on the upper surface of the plug-in diffusion layer 4, which is a collector extraction region,
A high concentration diffusion layer 12 is formed on the upper surface of the recess 4A. Then, a collector extraction electrode 9 is provided via the high concentration diffusion layer 12. An emitter electrode portion 10 is formed on the upper layer of the emitter diffusion layer 6, and an emitter extraction electrode 11 is formed corresponding to the emitter electrode portion 10 so as to penetrate the insulating film 7B.

In this semiconductor device, an N + buried layer 21 and a PWell layer 2 are formed in the semiconductor substrate 1 corresponding to the NMOS transistor region 1B formed on the semiconductor substrate 1.
2 Further, a source diffusion layer 23 and a drain diffusion layer 24 are formed above the PWell layer 22 in correspondence with the source and drain regions. On the semiconductor substrate 1, a gate electrode portion 25 is provided between the source diffusion layer 23 and the drain diffusion layer 24 via a gate oxide film 29, and the source diffusion layer 23 and the drain diffusion layer 24 A source electrode 26 and a drain electrode 27 are provided through the insulating film 7B. Further, an isolation diffusion layer 30 is provided between the NPN transistor region 1A and the NMOS transistor region 1B.

FIGS. 2 and 3 show NPN according to the present embodiment.
FIG. 4 is a cross-sectional view illustrating a process of manufacturing the transistor and the NMOS transistor. First, in the step shown in FIG. 2A, the N + buried layers 2, 21, the epitaxial layer 3, the element isolation diffusion layer 30 are formed in the NPN transistor region 1A and the NMOS transistor region 1B on the surface of the semiconductor substrate 1.
(Also used as the PWell layer 22 of the NMOS transistor), the plug-in diffusion layer 4, the base diffusion layer 5A and the graft base diffusion layer 5B of the NPN transistor, and the like, and the first SiO2 based insulating film 7A is formed on the surface thereof by the CVD method or the like. Form.

Next, in the step shown in FIG.
The SiO2 insulating film 7A in the S transistor region 1B is subjected to reactive ion etching (RI
The gate oxide film 29 having a thickness of 15 to 50 nm is formed by thermal oxidation at 800 to 900 ° C. by the method E).
Next, in the step shown in FIG.
A by RIE using resist patterning
Opening the emitter and collector formation regions of the NPN transistor, a Poly-Si film 31 is deposited. Next, the gate region of the NMOS transistor in the Poly-Si film 31 and the NP
As + or Pho is applied to the emitter region of the N transistor.
s + is increased by 1 at an implantation energy of about 50 to 100 keV.
The implantation is performed at a dose of × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² .

Next, in the step shown in FIG.
The gate electrode portion 25 of the NMOS transistor and the emitter electrode portion 10 of the NPN transistor are processed on the y-Si film 31 by RIE. At this time, the collector extraction region of the NPN transistor has a recess 4A formed on the upper surface of the plug-in diffusion layer 4 due to overetching during RIE. Next, in the step shown in FIG. 3E, the source of the NMOS transistor is
As + is rotationally implanted into the drain formation region and the collector extraction region of the NPN transistor at an implantation energy of about ²⁰ to 100 keV and a dose of about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² . Also, by performing this ion implantation by oblique implantation, an ion implantation region is also formed on the side wall of the collector extraction region of the NPN transistor, and by performing rotational implantation, shadowing is affected by the direction of the side wall. No more.

Next, in the step shown in FIG.
A second insulating film 7B is deposited by a CVD method, and
0-1000 ° C for 10-60 minutes, or 1000-
This is performed by a short-time heat treatment at 1200 ° C. for several seconds. Or
These two methods are performed in combination. Next, FIG.
In the step shown in (F), an NPN transistor, an NMOS
A pattern for extracting each electrode of the transistor is formed by a lithography process, and a barrier metal such as Ti,
A conductive material film such as Al is sequentially deposited and metal wiring (electrode 8,
9, 11, 26, 27) are formed. Although a passivation film and the like are finally required, they are well-known technologies and will not be described.

As described above, in the present embodiment, the NPN
By providing the recess 4A by etching the diffusion layer of the collector extraction region 4 of the transistor, the distance to the collector extraction electrode 11 is reduced, and the electrode 11
Can be increased by the high concentration diffusion layer 12, and the collector diffusion resistance can be reduced as compared with the conventional case. Further, since the process is shared with the NMOS transistor, the manufacturing cost can be reduced.

Although the embodiment of the present invention has been described above, the present invention is not limited to this embodiment.
Within the scope of the technical idea of the present invention, the process conditions and the like can be appropriately changed. In the above embodiment, the case where the NPN transistor and the NMOS transistor are provided on the semiconductor substrate has been described. However, the present invention can be similarly applied to a case where the MOS transistor is not mounted.

[0022]

As described above, in the semiconductor device according to the present invention, the collector extraction electrode is provided in the concave portion formed in the collector extraction region of the NPN transistor, so that the collector extraction electrode becomes the emitter extraction electrode and the base extraction electrode. Formed at a lower position. Therefore, the diffusion layer of the collector extraction region provided in the semiconductor substrate is arranged in a state close to the collector extraction electrode. As a result, the collector diffusion resistance can be reduced without impairing the reliability of the transistor. Become.

In the method of manufacturing a semiconductor device according to the present invention, a collector extraction electrode is provided in a concave portion formed in a collector extraction region of an NPN transistor.
This collector extraction electrode is an emitter extraction electrode,
And at a position lower than the base extraction electrode.
Therefore, the diffusion layer of the collector extraction region provided in the semiconductor substrate is arranged in a state close to the collector extraction electrode. As a result, the collector diffusion resistance can be reduced without impairing the reliability of the transistor. Become.

Further, in the step of forming the gate electrode portion of the MOS transistor and the emitter electrode portion of the NPN transistor, a concave portion can be formed in the collector extraction region, so that the collector diffusion resistance can be reduced without adding a manufacturing process. Reduction is possible. Further, in the step of introducing impurities into the source and drain regions of the MOS transistor, the impurities can be introduced into the collector extraction region of the NPN transistor at the same time, so that the collector diffusion resistance can be more effectively reduced without adding a manufacturing step. Become.

In the method of manufacturing a semiconductor device according to the present invention,
By providing the collector extraction electrode in the concave portion formed in the collector extraction region of the NPN transistor, the collector extraction electrode is formed at a position lower than the emitter extraction electrode and the base extraction electrode. Therefore, the diffusion layer of the collector extraction region provided in the semiconductor substrate is arranged in a state close to the collector extraction electrode. As a result, the collector diffusion resistance can be reduced without impairing the reliability of the transistor. Become. Further, in the step of forming the emitter electrode portion of the NPN transistor, a concave portion can be formed in the collector extraction region, so that the collector diffusion resistance can be reduced without adding a manufacturing step.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor device illustrated in FIG. 1;

FIG. 3 is a sectional view illustrating a manufacturing step of the semiconductor device illustrated in FIG. 1;

FIG. 4 is a cross-sectional view showing a structure of a conventional semiconductor device.

[Explanation of symbols]

1 ... semiconductor substrate, 1A ... NPN transistor region,
1B ... NMOS transistor area, 2, 21 ... N +
Buried layer, 3 ... Epitaxial layer, 4 ... Plug-in diffusion layer, 4A ... Recess, 5A ... Base diffusion layer, 5B
…… Graft base diffusion layer, 6 …… Emitter diffusion layer, 7
A, 7B: SiO2 insulating film, 8: Base extraction electrode, 9: Collector extraction electrode, 10: Emitter electrode portion, 11: Emitter extraction electrode, 12: High concentration diffusion layer, 22: PWell Layer 23 source diffusion layer 24 drain diffusion layer 25 gate electrode part
26 ... source electrode, 27 ... drain electrode, 29 ...
Gate oxide film, 30... Element isolation diffusion layer.

Claims (13)

[Claims] 1. A semiconductor device having a MOS transistor and an NPN transistor mounted on a semiconductor substrate, wherein the semiconductor substrate has a recess in a collector extraction region of the NPN transistor, and a collector extraction electrode of the NPN transistor includes: A semiconductor device, which is formed at a position lower than an emitter extraction electrode and a base extraction electrode. 2. The semiconductor device according to claim 1, wherein the electrode extraction regions of the MOS transistor and the NPN transistor are formed by reactive ion etching. 3. The semiconductor according to claim 1, wherein a collector extraction electrode of said NPN transistor is connected to a collector diffusion layer via a same diffusion layer as a source / drain diffusion layer of said MOS transistor. apparatus. 4. A method of manufacturing a semiconductor device in which an NPN transistor is mounted on a semiconductor substrate together with a MOS transistor, comprising: forming a first interlayer insulating film on the semiconductor substrate; A first step of patterning a film to open a region where the MOS transistor is to be formed and forming a gate insulating film; an emitter extracting window of an NPN transistor by patterning the first interlayer insulating film; A second step of opening a take-out window; forming a semiconductor film on the entire surface of the semiconductor substrate; patterning the semiconductor film to form a gate electrode portion of the MOS transistor and an emitter electrode portion of the NPN transistor And a third step of forming a recess in the collector extraction region; and a source and a drain of the MOS transistor. And the region,
A fourth step of introducing an impurity into the collector extraction region of the NPN transistor; and covering the entire surface of the semiconductor substrate with a second interlayer insulating film, patterning the first and second interlayer insulating films, MO
Source and drain extraction region of S transistor, NP
A fifth step of opening connection holes facing each of the emitter electrode portion, the base extraction region, and the collector extraction region of the N transistor; and a sixth step of forming each extraction electrode filling each of the connection holes.
A concave portion is formed in the collector extraction region in the third step, and the collector extraction electrode of the NPN transistor is formed at a position lower than the emitter extraction electrode and the base extraction electrode. A method for manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 4, wherein the recess in the collector extraction region is formed by over-etching when etching the semiconductor film in the third step. 6. The method according to claim 5, wherein the etching of the semiconductor film is performed by reactive ion etching. 7. The method according to claim 4, wherein the first interlayer insulating film and the second interlayer insulating film are made of a SiO 2 material. 8. The method for manufacturing a semiconductor device according to claim 4, wherein each of the extraction electrodes is formed using a laminated film in which a barrier metal and a conductive material film are sequentially laminated. 9. A method for manufacturing a semiconductor device having an NPN transistor mounted on a semiconductor substrate, comprising: forming a first interlayer insulating film on the semiconductor substrate; and patterning the first interlayer insulating film. A first step of opening an emitter take-out window and a collector take-out window of the NPN transistor; forming a semiconductor film over the entire surface of the semiconductor substrate; patterning the semiconductor film to form an emitter electrode portion of the NPN transistor; Forming a recess in the collector extraction region, introducing a impurity into the collector extraction region of the NPN transistor, covering the entire surface of the semiconductor substrate with a second interlayer insulating film. Patterning the first and second interlayer insulating films to form the NP
A fourth step of opening a connection hole facing each of the emitter electrode portion, the base extraction region, and the collector extraction region of the N transistor; and a fifth step of forming each extraction electrode filling the connection hole.
A concave portion is formed in the collector extraction region in the second step, and the collector extraction electrode of the NPN transistor is formed at a position lower than the emitter extraction electrode and the base extraction electrode. A method for manufacturing a semiconductor device, comprising: 10. A recess in the collector take-out region,
10. The method of manufacturing a semiconductor device according to claim 9, wherein the semiconductor film is formed by over-etching when etching the semiconductor film in the second step. 11. The method according to claim 10, wherein the etching of the semiconductor film is performed by reactive ion etching. 12. The method of manufacturing a semiconductor device according to claim 9, wherein said first interlayer insulating film and said second interlayer insulating film are made of a SiO 2 material. 13. The method of manufacturing a semiconductor device according to claim 9, wherein each of said extraction electrodes is formed using a laminated film formed by sequentially laminating a barrier metal and a conductive material film.