JP2001144187A - Semiconductor manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily from an accurate bipolar transistor and capacity, without impairing reliability of the gate insulation film of a MISFET. SOLUTION: Gate electrodes 109b and 109c of a CMOS and a lower electrode 109d of capacity are formed at the same time, an insulating film 112 is deposited, a base region 113 of an NPN transistor is formed, and an active region 114 is opened. A polycrystalline silicon film 115 is deposited, the sidewall of the polycrystalline silicon film 115 is formed on the gate electrode sidewall of a PMOS through selective etching, and an external base region 120a of the NPN transistor and a source/drain region 120b of the PMOS are formed at the same time. Also, the sidewall of the polycrystalline silicon film 115 is formed on the gate electrode sidewall of an NMOS, and a collector take-out layer 121a of the NPN transistor and a source/drain region 121c of the NMOS are formed at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MISFET
And a semiconductor manufacturing method for forming a bipolar transistor and a capacitor on the same substrate.

[0002]

2. Description of the Related Art In recent years, in order to meet demands for miniaturization of electric appliances and reduction in the number of parts, LSIs have been increasing in size and function. In particular, an analog / digital hybrid LSI has become essential. 12 to 22 are cross-sectional views showing respective laminated structures at key points in a conventional process in which a CMOS transistor, an NPN transistor, and a capacitor are formed on the same substrate. Hereinafter, a conventional example will be described with reference to FIG.

First, in FIG. 12, an N + collector buried layer 1100 of an NPN transistor is selectively formed on a P-type substrate 1000 by, for example, photolithography and arsenic ion implantation, and the photoresist is stripped. Then, an N-type epitaxial layer 1101 is formed thereover. Next, in FIG. 13, for example, by selective oxidation,
After forming the OCOS layer 1102, a buffer layer 1103 of Si02 is formed by, for example, thermal oxidation. Next, FIG.
4, the N-Well region 1 of the PMOS transistor is formed by, for example, photolithography and phosphorus ion implantation.
104 and collector extraction layer 110 of NPN transistor
4e is formed at the same time, and the photoresist is removed.

For example, the P-W of an NMOS transistor is formed by photolithography and boron ion implantation.
The cell region 1105 and the element isolation layer 1105e are formed at the same time, and the photoresist is removed. Next, in FIG.
For example, a polycrystalline silicon film 1106 containing a high concentration of phosphorus and, for example, a silicon nitride 1107 are sequentially deposited by, for example, CVD. Next, in FIG. 16, the insulating film 1107 and the polycrystalline silicon film 1106 are sequentially etched by, for example, photolithography and dry etching to form a capacitor insulating film 1107f and a capacitor lower electrode 1106f. Buffer layer 1103
Is etched to remove the photoresist. Next, the gate insulating film 1108 of the CMOS transistor and the lower electrode side wall insulating film 1108f of the capacitor are formed by, for example, thermal oxidation. Next, in FIG. 17, after forming the base region 1200 of the NPN transistor by, for example, photolithography and boron ion implantation, the insulating film 1108 is etched with, for example, a hydrofluoric acid solution to open the active region 201 of the NPN transistor. The resist is stripped.

Next, in FIG. 18, a polycrystalline silicon film 1109 containing a high concentration of phosphorus is deposited by, for example, CVD. Next, in FIG. 19, the polysilicon film 1109 is etched by, for example, photolithography and dry etching, and the gate electrode 110 of the NMOS transistor is etched.
9c, the gate electrode 1109b of the PMOS transistor and the polysilicon emitter region 11 of the NPN transistor.
09e and a capacitor upper electrode 1109f are formed, and the photoresist is removed. Further, for example, the LDD region 1110 of the PMOS transistor and the link base region 1110e of the NPN transistor are simultaneously formed by photolithography and boron ion implantation, and the photoresist is stripped. Further, the LDD region 11 of the NMOS transistor is formed by, for example, photolithography and arsenic ion implantation.
11 is formed, and the photoresist is removed.

Next, in FIG. 20, for example, after depositing a silicon oxide film by CVD, the gate electrode 1109b of the CMOS transistor is formed by dry etching, for example.
1109c, a polysilicon emitter region 1109e of an NPN transistor, upper and lower electrodes 1109f, 11
06f, sidewalls 1116b, 111
6c, 1116e, 1116f1, and 1116f2 are formed. The source / drain region 1120b of the PMOS transistor and the external base region 1120e of the NPN transistor are simultaneously formed by, for example, photolithography and boron ion implantation, and the photoresist is removed. The source / drain regions 1121c of the NMOS transistor are formed by, for example, photolithography and arsenic ion implantation, and the photoresist is stripped. Next, in FIG. 21, an interlayer insulating film 1122 is formed by a known method.
Is formed, and an emitter region 1123e of the NPN transistor is formed by, for example, RTA. Next, in FIG. 22, the electrodes 1124b, 112 of each element are shown by a known method.
4c, 1124e2, 1124e3, 1124f1, 1
124f2 is formed. Thereafter, a passivation film or the like is formed by a known method, but the description is omitted.

[0007]

In the prior art, as shown in FIG. 16, when the gate insulating film 1108 is formed by thermal oxidation, the lower electrode 1106 of the capacitor is formed.
An insulating film 1108f is also formed on the side wall of f. However, since the impurity is heavily doped in the lower electrode 1106f of the capacitor, the impurity is diffused outward during the thermal oxidation, and the reliability of the gate insulating film 1108 is reduced. In addition, since the insulating film 1107f of the capacitor is exposed to an oxidizing atmosphere, there is a problem that manufacturing variation in the capacitance value increases. In addition, as shown in FIGS. 17 and 18, a photolithography step for forming an NPN transistor is performed between the formation of a gate electrode material (1109 and the like) after the formation of the gate insulating film 1108; There is a problem that the reliability of the film 1108 is reduced.

In removing the photoresist, NPN
Although a native oxide film is formed in the active region of the transistor, it is difficult to remove the native oxide film without etching the gate insulating film. And this natural oxide film
There is a problem that the characteristics of the NPN transistor are seriously affected. Further, as shown in FIG. 20, external base region 1120e of the NPN transistor is formed in a self-aligned manner with respect to polycrystalline silicon emitter region 1109e, so that boron is also introduced into polycrystalline silicon emitter region 1109e. The heat treatment affects the profiles of the emitter region 1123e and the base region 1200 of the NPN transistor, causing a problem that manufacturing variations of the NPN transistor increase.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor manufacturing method capable of easily forming a high-precision bipolar transistor and a capacitor without impairing the reliability of a gate insulating film of a MISFET.

[0010]

According to the present invention, there is provided a semiconductor manufacturing method in which a MISFET, a bipolar transistor, and a capacitor are formed on the same semiconductor substrate, wherein a gate insulating film of the MISFET is formed on the semiconductor substrate. A first step of performing MISF on the semiconductor substrate.
A second step of forming a gate electrode of the ET and a lower electrode of the capacitor, a third step of covering the entire semiconductor substrate with a first insulating film, and a base of the bipolar transistor via the first insulating film. Fourth doping of the region with impurities
A step of etching the first insulating film and the gate insulating film to expose a surface of the semiconductor substrate corresponding to an active region of the bipolar transistor; and covering the entire semiconductor substrate with a polycrystalline silicon film. A sixth step of etching the polycrystalline silicon film as an emitter region and an upper electrode of a capacitor of the bipolar transistor; and an external base region and a MISF of the bipolar transistor using the polycrystalline silicon film as a mask.
An eighth step of doping the source / drain regions of the ET with impurities.

According to the semiconductor manufacturing method of the present invention, a gate insulating film of a MISFET is formed on a semiconductor substrate in a first step, and a gate electrode of the MISFET and a lower electrode of a capacitor are formed in a second step. In the step, the entire semiconductor substrate is covered with the first insulating film. Thereafter, in a fourth step, an impurity in the base region of the bipolar transistor is doped through the above-described first insulating film, and in a fifth step, the first impurity is doped.
Is etched to expose the surface of the semiconductor substrate corresponding to the active region of the bipolar transistor. Then, in a sixth step, the entire semiconductor substrate is covered with a polycrystalline silicon film, and in a seventh step, the polycrystalline silicon film is etched as an emitter region of the bipolar transistor and an upper electrode of the capacitor. In addition, the eighth
In the step, impurities are doped into the external base region of the bipolar transistor and the source / drain region of the MISFET using the polycrystalline silicon film as a mask. Through the steps described above, according to the present invention, a highly accurate bipolar transistor and a capacitor can be easily formed without impairing the reliability of the gate insulating film of the MISFET transistor.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the semiconductor manufacturing method according to the present invention will be described below. An embodiment of the present invention relates to a method of manufacturing a semiconductor device in which a CMOSFET, a bipolar transistor, and a capacitor are formed on the same substrate, and is characterized by the following steps. First, after a gate electrode of a CMOS transistor and a lower electrode of a capacitor are formed simultaneously, a first insulating film is deposited for the capacitor, a base region of the NPN transistor is formed, and an active region of the NPN transistor is opened.

Next, the emitter contact of the NPN transistor, the upper electrode of the capacitor, and the LD of the CMOS transistor
A polycrystalline silicon film is deposited for the D spacer, and the polycrystalline silicon film is etched by covering the emitter contact and the collector contact of the NPN transistor, the NMOS transistor region and the capacitor region with the photoresist, and etching the polycrystalline silicon film.
A sidewall (LDD spacer) of a polycrystalline silicon film is formed on the side wall of the gate electrode of the S transistor, and the external base region of the NPN transistor and the source / drain of the PMOS transistor are simultaneously formed.

Further, the active region of the NPN transistor, the PMOS transistor region, and the upper electrode of the capacitor are covered with a photoresist and the polysilicon film is etched, and the side wall (LDD) of the polysilicon film is formed on the side wall of the gate electrode of the NMOS transistor. Spacer), and the collector extraction layer of the NPN transistor and the NMOS
The source / drain of the transistor is formed simultaneously. By adopting such a process, a high-precision NPN transistor and a capacitor can be easily formed without deteriorating the reliability of the gate insulating film of the CNOS transistor.

Next, a specific example according to the present embodiment will be described with reference to the drawings. 1 to 11 are cross-sectional views each showing a laminated structure at a key step in a process in which a CMOS transistor, an NPN transistor, and a capacitor are formed on the same substrate. First, in FIG. 1, NPs are selectively formed on a P-type substrate 10 by, for example, photolithography and arsenic ion implantation.
An N + collector buried layer 100 of the N transistor is formed, and the photoresist is stripped. Next, an N-type epitaxial layer 101 is formed thereon. Next, in FIG.
After the LOCOS layer 102 is formed by, for example, the selective oxidation method, the buffer 103 of Si02 is formed by, for example, thermal oxidation.

Next, in FIG. 3, the N-well region 104 of the PMOS transistor and the collector extraction layer 104a are simultaneously formed by photolithography and phosphorus ion implantation, and the photoresist is stripped. Also, for example, by photolithography and boron ion implantation,
The P-Well region 105 of the NMOS transistor and the element isolation layer 105a are simultaneously formed, and the photoresist is stripped. Next, in FIG. 4, the gate insulating film 108 of the CMOS transistor is formed by, for example, thermal oxidation. And
For example, a polycrystalline silicon film 109 containing phosphorus at a high concentration is deposited by CVD.

Next, in FIG. 5, for example, the polycrystalline silicon film 109 is formed by photolithography and dry etching.
Is etched, and the gate electrode 1 of the NMOS transistor is etched.
09c, the gate electrode 109b of the PMOS transistor and the lower electrode 109d of the capacitor are formed, and the photoresist is removed. The LDD region 1 of the PMOS transistor is formed by, for example, photolithography and boron ion implantation.
10 is formed, and the photoresist is removed. Further, an insulating film 112 of, for example, silicon nitride is deposited by, for example, CVD. Next, in FIG. 6, after the base region 113 of the NPN transistor is formed by, for example, photolithography and boron ion implantation, the insulating film 112 and the gate insulating film 108 are sequentially etched by, for example, dry etching to form the active region of the NPN transistor. An opening 114 is formed, and the photoresist is removed. Also,
For example, after removing the natural oxide film at the opening of the active region 114 of the NPN transistor with a hydrofluoric acid solution, the polycrystalline silicon film 1 containing a high concentration of phosphorus by, for example, CVD.
15 is deposited.

Next, in FIG. 7, the polycrystalline silicon film 115 is etched by a first dry etching with the emitter contact and the collector contact of the NPN transistor, the NMOS transistor region and the capacitor region covered with, for example, a photoresist. Thereby, the NPN
Polycrystalline silicon emitter region 115a of transistor
And a sidewall (spacer) 115b of the polycrystalline silicon film 115 on the side wall of the gate electrode of the PMOS transistor
To form Then, the external base region 120a of the NPN transistor is
The source / drain regions 120b of the MOS transistors are formed simultaneously. Next, in FIG. 8, the side wall 115b on the side wall of the gate electrode of the PMOS transistor is removed by, for example, the second dry etching under a condition having less anisotropy than the first dry etching of FIG. Thereafter, the photoresist is stripped.

In FIG. 9, while the active region of the NPN transistor, the PMOS transistor region, and the upper electrode of the capacitor are covered by, for example, a photoresistor, the polycrystalline silicon films 115c, 115a1,.
By etching 115d1, a sidewall (spacer) of polycrystalline silicon (not shown) is formed on the upper electrode 115d of the capacitor and the gate electrode side wall of the NMOS transistor. Then, the collector extraction layer 121a of the NPN transistor and the source / drain region 121c of the NMOS transistor are simultaneously formed by, for example, arsenic ion implantation, and the sidewall of the gate electrode side wall of the NMOS transistor is etched as in the process of FIG. Remove
Thereafter, the photoresist is stripped. In FIG. 10, an interlayer insulating film 122 is formed by a known method, for example, RTA.
Thereby, the emitter region 123 of the NPN transistor is formed. In FIG. 11, the electrode 1 of each element is shown by a known method.
24b, 124c, 124a1, 124a2, 124a
3, 124d1 and 124d2 are formed. Thereafter, a passivation film or the like is formed by a known method.
The description below is omitted.

According to the above-described embodiment of the present invention, when the gate insulating film 108 is oxidized, the substrate having a concentration corresponding to the well region of the CMOS transistor is exposed. A gate insulating film can be formed. Further, since the gate electrode material 109 is deposited without passing through another step after the oxidation of the gate insulating film 108, the cleanness of the gate insulating film below the gate electrode can be maintained better than in the conventional example. After the deposition of the capacitor insulating film material 112, the electrode material (polycrystalline silicon film 115) is deposited without going through the thermal oxidation step, so that the manufacturing variation of the capacitance value can be reduced as compared with the conventional example.

Since the native oxide film on the surface of the substrate can be removed before forming the polycrystalline silicon film 115, which is the emitter contact material of the NPN transistor, the interface state between the polycrystalline silicon and the substrate is more stable than in the conventional example. Can be done. The external base region of the NPN transistor can be formed in a self-aligned manner with respect to the polysilicon emitter region as in the conventional example. However, since the polysilicon emitter region is covered with the photoresist, the external base region is different from the conventional example. No boron is introduced into the polysilicon emitter region. In the conventional example, the formation of the buried layer 100 of the NPN transistor, the formation of the lower electrode 106f of the capacitor, and the
Although three masks need to be added for the opening of the active region 201 of the N transistor, according to the present embodiment, the formation of the buried layer 100 of the NPN transistor and the opening of the opening of the active region 114 of the NPN transistor are performed. Therefore, it can be realized by adding two masks, and the manufacturing cost can be reduced by reducing the number of masks.

[0022]

As described above, in the semiconductor manufacturing method of the present invention, the gate insulating film of the MISFET is formed on the semiconductor substrate, and then the gate electrode of the MISFET and the lower electrode of the capacitor are formed. The whole was covered with a first insulating film (first to third steps). Therefore, when the gate insulating film is oxidized, the substrate having a concentration corresponding to the well region of the MIS transistor is exposed, so that a higher quality gate insulating film can be formed as compared with the conventional example. Further, since the gate electrode material is deposited after the oxidation of the gate insulating film without going through another process, the cleanness of the gate insulating film below the gate electrode can be maintained better than in the conventional example.

Further, according to the present invention, after forming the first insulating film, the whole semiconductor substrate is covered with a polycrystalline silicon film through an impurity doping process for the base region of the bipolar transistor and an exposing step of the active region of the bipolar transistor. Then, the emitter region of the bipolar transistor and the upper electrode of the capacitor are formed (third to seventh steps). Therefore, after forming the first insulating film, which is a material of the insulating film of the capacitor, the upper electrode material is deposited without going through the thermal oxidation step, so that the manufacturing variation of the capacitance value can be reduced as compared with the conventional example.

Before the formation of the polycrystalline silicon film, which is the emitter contact material of the bipolar transistor, in the step of exposing the active region of the bipolar transistor (fifth step), the gate oxide film and the gate electrode are etched by etching the gate electrode. Since the natural oxide film can be removed, the interface state between the polycrystalline silicon film and the substrate can be stabilized as compared with the conventional example. Therefore, in the present invention, MI
A highly accurate bipolar transistor and a capacitor can be easily formed without deteriorating the reliability of the gate insulating film of the SFET.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a sectional view illustrating a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 7 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 8 is a cross-sectional view showing a step of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 10 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 11 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 12 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 13 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 14 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 15 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 16 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 17 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 18 is a cross-sectional view showing a manufacturing step of a semiconductor device according to a conventional example.

FIG. 19 is a cross-sectional view showing a manufacturing step of a semiconductor device according to a conventional example.

FIG. 20 is a cross-sectional view showing a manufacturing step of a semiconductor device according to a conventional example.

FIG. 21 is a cross-sectional view showing a manufacturing step of a semiconductor device according to a conventional example.

FIG. 22 is a cross-sectional view showing a manufacturing step of a semiconductor device according to a conventional example.

[Explanation of symbols]

10: P-type substrate, 100: N + collector buried layer, 101: N-type epitaxial layer, 102: LO
COS layer, 103 buffer, 104 N-Wel
l region, 104a ... collector extraction layer, 105 ... P
-Well region, 105a ... device isolation layer, 108 ...
Gate insulating film, 109, 115... Polycrystalline silicon film,
109b, 109c ... gate electrode, 109d ... lower electrode, 112 ... insulating film, 113 ... base region, 11
4 Active region 115a Polycrystalline silicon emitter region 115b Side wall (spacer) 115d Upper electrode 120a External base region 120b 121c Source / drain region
121a ... collector extraction layer, 122 ... interlayer insulating film, 123 ... emitter region, 124b, 124c, 1
24a1, 124a2, 124a3, 124d1, 12
4d2 ... electrodes.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8249

Claims (5)

[Claims] 1. A semiconductor manufacturing method in which a MISFET, a bipolar transistor, and a capacitor are formed on the same semiconductor substrate, wherein: a first step of forming a gate insulating film of the MISFET on the semiconductor substrate; A second step of forming a gate electrode and a lower electrode of a capacitor; a third step of covering the entire semiconductor substrate with a first insulating film; and a step of forming a base region of a bipolar transistor via the first insulating film. A fourth step of doping impurities, a fifth step of etching the first insulating film and the gate insulating film, and exposing a surface of the semiconductor substrate corresponding to an active region of the bipolar transistor; 6th covering with polycrystalline silicon film
And etching the polycrystalline silicon film as an upper electrode of an emitter region and a capacitor of a bipolar transistor.
And a eighth step of doping impurities into the external base region of the bipolar transistor and the source and drain regions of the MISFET using the polycrystalline silicon film as a mask. 2. The method according to claim 1, wherein the gate electrode of the MISFET and the lower electrode of the capacitor are formed in the same step. 3. The LDD according to claim 1, wherein said polycrystalline silicon film is used as a mask when said polycrystalline silicon film is etched as an emitter region and an upper electrode of a capacitor of said bipolar transistor in said seventh step. 3. The method according to claim 1, wherein the semiconductor device has a structure. 4. The bipolar transistor is an NPN transistor, and the MISFET is a CMOSFET.
4. The semiconductor manufacturing method according to claim 3, wherein 5. After forming an emitter region of an NPN transistor and a spacer of a PMOS transistor by the polycrystalline silicon film formed in the sixth step,
Doping impurities into the external base region of the transistor and the source and drain regions of the PMOS transistor,
5. The method according to claim 4, wherein after the spacer of the NMOS transistor is formed by the polycrystalline silicon film, impurity doping is performed on the collector extraction layer of the NPN transistor and the source and drain regions of the NMOS transistor. .