JP2001144140A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JP2001144140A
JP2001144140A JP32190399A JP32190399A JP2001144140A JP 2001144140 A JP2001144140 A JP 2001144140A JP 32190399 A JP32190399 A JP 32190399A JP 32190399 A JP32190399 A JP 32190399A JP 2001144140 A JP2001144140 A JP 2001144140A
Authority
JP
Japan
Prior art keywords
chip
thin film
adhesive
film layer
adhesive thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32190399A
Other languages
Japanese (ja)
Other versions
JP4180206B2 (en
Inventor
Hideo Senoo
尾 秀 男 妹
Yuichi Iwakata
方 裕 一 岩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lintec Corp
Original Assignee
Lintec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lintec Corp filed Critical Lintec Corp
Priority to JP32190399A priority Critical patent/JP4180206B2/en
Publication of JP2001144140A publication Critical patent/JP2001144140A/en
Application granted granted Critical
Publication of JP4180206B2 publication Critical patent/JP4180206B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

PROBLEM TO BE SOLVED: To provide a method that efficiently manufactures a high reliability product by preventing the generation of voids during the manufacturing of a semiconductor device for sealing resin. SOLUTION: In this manufacturing method for a semiconductor device an adhesive thin film layer on the circuit side of a semiconductor wafer, at which a circuit is formed on the surface and the semiconductor wafer is cut and separated into an individual chip every circuit. The individual chip is loaded on the prescribed position of a substrate for mounting a chip via the adhesive thin film layer, and the individual chip is bonded and fixed to the substrate for mounting the chip, securing the continuity between the individual chip and the substrate for mounting the chip.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
方法に関し、さらに詳しくは樹脂封止半導体装置の製造
時に、ボイドの発生を防止し、信頼性の高い製品を効率
良く製造しうる方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of efficiently manufacturing a highly reliable product by preventing generation of voids in manufacturing a resin-sealed semiconductor device. .

【0002】[0002]

【従来の技術】一般的に、半導体装置は、回路面を保護
するために、樹脂により封止されている。従来このよう
な樹脂封止された半導体装置は、個々のICチップをそ
れぞれ別個にリードフレームにマウントした後、一つ一
つを金型を用いて樹脂封止することにより製造されてい
る。
2. Description of the Related Art Generally, a semiconductor device is sealed with a resin in order to protect a circuit surface. Conventionally, such a resin-sealed semiconductor device has been manufactured by mounting individual IC chips individually on a lead frame and then sealing each one with a resin using a mold.

【0003】より具体的には、次の手法が現在行われて
いる。 (1)ICチップとリードフレームとを金線等を用いて
接続し、その後樹脂封止する。 (2)導通用突起物が形成されているリードフレームに
ICチップを載置し、導通用突起物を介してICチップ
とリードフレームとを接続し、その後樹脂封止する。 (3)異方導電性フィルムあるいは異方導電性ペースト
を介してICチップとリードフレームとを接続し、その
後樹脂封止する。
[0003] More specifically, the following method is currently being implemented. (1) The IC chip and the lead frame are connected by using a gold wire or the like, and then, resin sealing is performed. (2) The IC chip is mounted on the lead frame on which the conductive projections are formed, and the IC chip and the lead frame are connected via the conductive projections, followed by resin sealing. (3) The IC chip and the lead frame are connected via an anisotropic conductive film or an anisotropic conductive paste, and then are sealed with a resin.

【0004】しかし、上記(1)の方法では、金線を含
めてモールドしなければならないため、チップサイズに
比べて半導体装置が大き過ぎ、携帯電話などの小型機器
には用いられにくいという問題があった。このため、半
導体装置のサイズがチップサイズとほぼ同等の大きさに
できる(2)あるいは(3)の方法が用いられてくるよ
うになった。
However, in the above method (1), since the molding must be performed including the gold wire, there is a problem that the semiconductor device is too large compared to the chip size, and it is difficult to use the semiconductor device in a small device such as a mobile phone. there were. For this reason, the method (2) or (3), which allows the size of the semiconductor device to be substantially equal to the chip size, has been used.

【0005】しかしながら、上記(2)の方法において
は、導通用突起物の高さの分だけ、ICチップとリード
フレームとの間に空間があり、樹脂封止を行っても、こ
の空間に樹脂が充分に侵入せず、ボイドが発生すること
がある。このため、樹脂封止の前に、ICチップとリー
ドフレームとの間に絶縁性接着剤を充填する必要があっ
た。
[0005] However, in the method (2), there is a space between the IC chip and the lead frame by the height of the conductive projection. May not penetrate sufficiently and voids may occur. Therefore, it is necessary to fill an insulating adhesive between the IC chip and the lead frame before resin sealing.

【0006】また上記(3)の方法では、微小なICチ
ップに、異方導電性フィルムを貼付あるいは異方導電性
ペーストを塗布する必要があり、やはり作業工程上煩雑
である。特に異方導電性ペーストは、一定量を塗布する
ことが困難であり、製品毎にペーストの量が異なり、製
品特性にバラツキがでる虞もある。
In the above method (3), it is necessary to attach an anisotropic conductive film or apply an anisotropic conductive paste to a minute IC chip, which is also complicated in the work process. In particular, it is difficult to apply a constant amount of the anisotropic conductive paste, and the amount of the paste differs for each product, which may cause variations in product characteristics.

【0007】[0007]

【発明が解決しようとする課題】本発明は、上記のよう
な従来技術に鑑みてなされたものであって、樹脂封止半
導体装置の製造時に、ボイドの発生を防止し、信頼性の
高い製品を効率良く製造しうる方法を提供することを目
的としている。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned prior art, and is intended to prevent the occurrence of voids during the production of a resin-encapsulated semiconductor device and to provide a highly reliable product. It is an object of the present invention to provide a method capable of efficiently producing a.

【0008】[0008]

【課題を解決するための手段】本発明に係る半導体装置
の製造方法は、表面に回路が形成された半導体ウエハの
回路面に、接着性薄膜層を形成し、該半導体ウエハを、
回路毎に個別のチップに切断分離し、該個別のチップを
該接着性薄膜層を介して、チップ搭載用基板の所定位置
に載置し、該個別のチップと該チップ搭載用基板との導
通を確保しながら該個別のチップを該チップ搭載用基板
に接着固定することを特徴としている。
According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an adhesive thin film layer on a circuit surface of a semiconductor wafer having a circuit formed on a surface;
Cut and separated into individual chips for each circuit, place the individual chips at predetermined positions on the chip mounting substrate via the adhesive thin film layer, and conduct the electric conduction between the individual chips and the chip mounting substrate. The individual chips are bonded and fixed to the chip mounting substrate while ensuring the above conditions.

【0009】本発明においては、半導体ウエハを個別の
チップに切断分離する前に、該接着性薄膜層により半導
体ウエハの回路面を保護しながら該半導体ウエハの裏面
研削を行なってもよい。また、前記接着性薄膜層が片面
に剥離性シートを有し、該接着性薄膜層の剥離性シート
が形成されていない面を介して、該接着性薄膜層を半導
体ウエハの回路面に貼付することにより、半導体ウエハ
の回路面に接着性薄膜層を形成し、個別のチップを、チ
ップ搭載用基板に載置する前に、該剥離性シートを接着
性薄膜層から剥離することもできる。
In the present invention, before cutting and separating the semiconductor wafer into individual chips, the back surface of the semiconductor wafer may be ground while protecting the circuit surface of the semiconductor wafer with the adhesive thin film layer. Further, the adhesive thin film layer has a peelable sheet on one side, and the adhesive thin film layer is attached to a circuit surface of a semiconductor wafer through a surface of the adhesive thin film layer on which the peelable sheet is not formed. This makes it possible to form the adhesive thin film layer on the circuit surface of the semiconductor wafer, and to peel off the peelable sheet from the adhesive thin film layer before placing the individual chips on the chip mounting substrate.

【0010】さらに、本発明においては、前記接着性薄
膜層を異方導電性接着剤で形成してもよい。また、前記
接着性薄膜層は絶縁性接着剤からなるものであってもよ
く、この場合、チップの回路上および/またはチップ搭
載用基板上に導通用突起物を有するものを用い、該接着
性薄膜層を加熱により流動化させて該導通用突起物を介
してチップとチップ搭載用基板との間に導通を確保する
こともできる。
Further, in the present invention, the adhesive thin film layer may be formed of an anisotropic conductive adhesive. Further, the adhesive thin film layer may be made of an insulating adhesive. In this case, an adhesive thin film layer having a conductive projection on a chip circuit and / or a chip mounting substrate is used. The thin film layer can be fluidized by heating to secure conduction between the chip and the chip mounting substrate via the conduction protrusion.

【0011】このような本発明に係る半導体装置の製造
方法によれば、樹脂封止半導体装置の製造時に、ボイド
の発生を防止し、信頼性の高い製品を効率良く製造でき
る。
According to the method of manufacturing a semiconductor device according to the present invention, it is possible to prevent voids from occurring at the time of manufacturing the resin-encapsulated semiconductor device and efficiently manufacture a highly reliable product.

【0012】[0012]

【発明の実施の形態】以下、本発明について図面を参照
しながらさらに具体的に説明する。本発明に係る半導体
装置の第1の製造方法においては、まず図1または図4
に示すように、表面に回路が形成された半導体ウエハ1
の回路面に、接着性薄膜層12(または22)を形成す
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described more specifically with reference to the drawings. In the first method of manufacturing a semiconductor device according to the present invention, first, FIG.
As shown in FIG. 1, a semiconductor wafer 1 having a circuit formed on its surface
The adhesive thin film layer 12 (or 22) is formed on the circuit surface.

【0013】半導体ウエハ1としては、従来より用いら
れているシリコン半導体ウエハ、ガリウム・ヒ素半導体
ウエハなどが挙げられるが、これらに限定されず、種々
の半導体ウエハを用いることができる。ウエハ表面への
回路の形成は、エッチング法、リフトオフ法などの従来
より汎用されている方法を含む、様々な方法により行う
ことができる。半導体ウエハの回路形成工程において、
所定の回路が形成される。
Examples of the semiconductor wafer 1 include a conventionally used silicon semiconductor wafer and a gallium / arsenic semiconductor wafer, but are not limited thereto, and various semiconductor wafers can be used. The formation of the circuit on the wafer surface can be performed by various methods including a conventionally widely used method such as an etching method and a lift-off method. In a circuit formation process of a semiconductor wafer,
A predetermined circuit is formed.

【0014】この回路形成工程においては、ウエハ裏面
に酸化物被膜が形成されることがあるが、このような酸
化物被膜は、必要に応じ、後述するウエハ裏面の研削に
より除去される。接着性薄膜層は、異方導電性接着剤ま
たは絶縁性接着剤からなる。図1に示す接着性薄膜層1
2は、異方導電性接着剤からなる(以下、この場合を
「異方導電性接着剤層12」と略記する)。異方導電性
接着剤は、バインダーポリマー中に導電性粒子を含む接
着剤であり、圧着前には接着性薄膜層中の導電性粒子同
士は互いに接触しない範囲でバインダー樹脂中に存在
し、接着性薄膜層を介してチップとチップ搭載用基板と
を圧着すると、電極としての導電性突起物が接着性薄膜
層を圧縮し、接着性薄膜層の厚さ方向にのみ導電性粒子
が接触し、異方導電性を発現するものである。
In this circuit forming step, an oxide film may be formed on the back surface of the wafer, and such an oxide film is removed by grinding the back surface of the wafer as described later, if necessary. The adhesive thin film layer is made of an anisotropic conductive adhesive or an insulating adhesive. Adhesive thin film layer 1 shown in FIG.
2 is made of an anisotropic conductive adhesive (hereinafter, this case is abbreviated as “anisotropic conductive adhesive layer 12”). Anisotropic conductive adhesive is an adhesive containing conductive particles in a binder polymer.Before pressing, the conductive particles in the adhesive thin film layer are present in the binder resin within a range where they do not come into contact with each other and adhere. When the chip and the chip mounting substrate are pressure-bonded through the conductive thin film layer, the conductive protrusions as electrodes compress the adhesive thin film layer, and the conductive particles contact only in the thickness direction of the adhesive thin film layer, It develops anisotropic conductivity.

【0015】バインダー樹脂として用いられる材料は、
通常の接着剤として使用されている樹脂が特に制限され
ることなく用いられ、熱硬化性のものであっても、熱可
塑性のものであってもよい。また、貼付時に感圧接着性
であり、後に加熱によって硬化する、いわゆる粘接着剤
を使用してもよい。熱硬化性のバインダー樹脂として
は、たとえばエポキシ樹脂、アクリル樹脂、ポリイミド
樹脂、フェノール樹脂、尿素樹脂、メラミン樹脂、レゾ
ルシノール樹脂等が用いられ、好ましくはエポキシ樹
脂、アクリル樹脂が用いられる。
The material used as the binder resin is
Resins used as ordinary adhesives are used without any particular limitation, and may be thermosetting or thermoplastic. Further, a so-called pressure-sensitive adhesive which is pressure-sensitive adhesive at the time of application and is cured by heating later may be used. As the thermosetting binder resin, for example, an epoxy resin, an acrylic resin, a polyimide resin, a phenol resin, a urea resin, a melamine resin, a resorcinol resin, or the like is used, and preferably, an epoxy resin or an acrylic resin is used.

【0016】熱可塑性のバインダー樹脂としては、たと
えばポリエステル樹脂、ポリ酢酸ビニル、ポリビニルア
ルコール、ポリビニルブチラール、ポリ塩化ビニル、ポ
リメタクリレート、ポリアクリレート、ポリスチレン、
ポリエチレン、ポリアミド、セルロース、ポリイソブチ
レン、ポリビニルエーテル、ポリイミド樹脂、各種のホ
ットメルト系接着剤等が用いられ、好ましくはポリエス
テル樹脂、ポリイミド樹脂が用いられる。
Examples of the thermoplastic binder resin include polyester resin, polyvinyl acetate, polyvinyl alcohol, polyvinyl butyral, polyvinyl chloride, polymethacrylate, polyacrylate, polystyrene, and the like.
Polyethylene, polyamide, cellulose, polyisobutylene, polyvinyl ether, polyimide resin, various hot melt adhesives and the like are used, and polyester resin and polyimide resin are preferably used.

【0017】粘接着剤としては、たとえば常温で感圧接
着性を有するバインダー樹脂と熱硬化性樹脂との混合物
が挙げられる。常温で感圧接着性を有するバインダー樹
脂としては、たとえばアクリル樹脂、ポリエステル樹
脂、ポリビニルエーテル、ウレタン樹脂、ポリアミド等
が挙げられる。熱硬化性樹脂としては、前述の熱硬化性
のバインダー樹脂と同様の樹脂があげられ、バインダー
樹脂よりも比較的低分子量のものが使用できる。また粘
接着剤には後述の剥離性シートとの剥離性を制御するた
め、ウレタン系アクリレートオリゴマーなどの紫外線硬
化性樹脂を配合することが好ましい。紫外線硬化性樹脂
を配合すると、紫外線照射前は剥離性シートが接着性薄
膜層とよく密着し、紫外線照射後は剥離しやすくなる。
Examples of the adhesive include a mixture of a binder resin having a pressure-sensitive adhesive property at room temperature and a thermosetting resin. Examples of the binder resin having pressure-sensitive adhesive properties at room temperature include acrylic resin, polyester resin, polyvinyl ether, urethane resin, polyamide and the like. Examples of the thermosetting resin include resins similar to the above-described thermosetting binder resins, and those having a relatively lower molecular weight than the binder resin can be used. Further, in order to control the releasability from a releasable sheet to be described later, it is preferable to blend an ultraviolet curable resin such as a urethane acrylate oligomer in the adhesive. When an ultraviolet curable resin is blended, the peelable sheet adheres well to the adhesive thin film layer before the ultraviolet irradiation, and becomes easily peeled after the ultraviolet irradiation.

【0018】導電性粒子として用いられる材料は、金、
銀、銅、ニッケル、アルミニウム等の金属あるいは合金
の粉体や繊維状体やカーボンブラックあるいは、ポリア
ニリン、ポリピロール等の導電性高分子の粉体や繊維状
体が用いられる。これらの材料は、それぞれ単独で用い
てもよく、また複数種を組み合わせて用いてもよい。ま
た、粉体等の形状についても、導電性材料単独で形成さ
れているものであってもよく、またスチレン、アクリル
等の樹脂にコーティングあるいはメッキしたものであっ
てもよい。粉体あるいは繊維状体の大きさは、1〜20
μm程度が好ましい。
Materials used as the conductive particles are gold,
Powders or fibrous materials of metals or alloys such as silver, copper, nickel, and aluminum, and fibrous materials, carbon black, and conductive polymers such as polyaniline and polypyrrole are used. Each of these materials may be used alone, or a plurality of them may be used in combination. Further, the shape of the powder or the like may be formed of a conductive material alone, or may be formed by coating or plating a resin such as styrene or acrylic. The size of the powder or fibrous body is 1 to 20
It is preferably about μm.

【0019】このような導電性粒子は、上記バインダー
樹脂100重量部に対して、1〜500重量部程度の割
合で用いられる。異方導電性接着剤層12の膜厚は、好
ましくは1〜100μm程度であり、特に好ましくは1
0〜50μm程度である。図4に示す接着性薄膜層22
は、絶縁性接着剤からなるなる(以下、この場合を「絶
縁性接着剤層22」と略記する)。
Such conductive particles are used in an amount of about 1 to 500 parts by weight based on 100 parts by weight of the binder resin. The thickness of the anisotropic conductive adhesive layer 12 is preferably about 1 to 100 μm, particularly preferably 1 to 100 μm.
It is about 0 to 50 μm. The adhesive thin film layer 22 shown in FIG.
Is composed of an insulating adhesive (hereinafter, this case is abbreviated as “insulating adhesive layer 22”).

【0020】絶縁性接着剤は、導電性粒子を含まない以
外は、前記異方導電性接着剤と同様であり、また熱硬化
性のものであっても、熱可塑性のものであっても、また
粘接着剤からなるものであってもよい。すなわち、熱硬
化性絶縁性接着剤層22は、前述した熱硬化性のバイン
ダー樹脂を主成分としてなり、導電性粒子を含まないも
のであり、また、熱可塑性絶縁性接着剤層22は、前述
した熱可塑性のバインダー樹脂を主成分としてなり、導
電性粒子を含まないものである。
The insulating adhesive is the same as the above-described anisotropic conductive adhesive except that it does not contain conductive particles, and may be either a thermosetting one or a thermoplastic one. Further, it may be made of an adhesive. That is, the thermosetting insulating adhesive layer 22 contains the above-described thermosetting binder resin as a main component and does not include conductive particles. It contains a thermoplastic binder resin as a main component and does not contain conductive particles.

【0021】また粘接着性の絶縁性接着剤層22は、前
述した粘接着剤を主成分としてなり、導電性粒子を含ま
ないものである。絶縁性接着剤層22の膜厚は、好まし
くは1〜200μm程度であり、特に好ましくは10〜
70μm程度である。なお、本発明においては、図1ま
たは図4に示すように、接着性薄膜層12または22の
片面に、剥離性シート11または21が貼着されていて
もよい。
The adhesive adhesive layer 22 has the above-mentioned adhesive as a main component and does not contain conductive particles. The thickness of the insulating adhesive layer 22 is preferably about 1 to 200 μm, particularly preferably 10 to 200 μm.
It is about 70 μm. In the present invention, as shown in FIG. 1 or FIG. 4, a peelable sheet 11 or 21 may be attached to one surface of the adhesive thin film layer 12 or 22.

【0022】接着性薄膜層は所定の工程を剥離性シート
を積層した形で使用され、その後剥離性シートからウエ
ハまたはチップに転写される。剥離性シートは、たとえ
ば接着性薄膜層をウエハに貼付する際に、張力により変
形しないように補強のために用いられる。また、研削工
程や切断分離工程の際に接着性薄膜層の表面を保護する
こともできる。
The adhesive thin film layer is used in a form in which a peelable sheet is laminated in a predetermined step, and is then transferred from the peelable sheet to a wafer or a chip. The peelable sheet is used for reinforcement, for example, when the adhesive thin film layer is attached to the wafer so as not to be deformed by tension. In addition, the surface of the adhesive thin film layer can be protected during the grinding step or the cutting / separating step.

【0023】剥離性シートとしては、従来より粘着テー
プ等の基材として用いられている各種の薄層品が特に制
限されることなく用いられ、たとえば紙、金属箔や、ポ
リエチレンテレフタレート、ポリエチレン、ポリスチレ
ン、ポリプロピレン、ナイロン、ウレタン、ポリ塩化ビ
ニリデン、ポリ塩化ビニルなどの合成樹脂フィルムが用
いられる。また、これらの積層品であってもよい。
As the releasable sheet, various thin layer products conventionally used as a substrate such as an adhesive tape are used without any particular limitation. Examples thereof include paper, metal foil, polyethylene terephthalate, polyethylene, and polystyrene. Synthetic resin films of polypropylene, nylon, urethane, polyvinylidene chloride, polyvinyl chloride and the like are used. Further, a laminate of these may be used.

【0024】本発明では、接着性薄膜層を剥離性シート
表面から剥離し、チップ等への転写容易にするために、
これら剥離性シートの表面に、必要に応じシリコーン樹
脂やアルキッド樹脂などで離型処理を施してもよい。こ
のような剥離性シート11または21の表面張力は、40
mN/m以下であることが好ましく、さらに20〜40mN/mの範
囲にあることが好ましく、特に30〜35mN/mの範囲にある
ことが好ましい。
In the present invention, in order to peel the adhesive thin film layer from the surface of the peelable sheet and to facilitate transfer to a chip or the like,
The surface of these releasable sheets may be subjected to a release treatment with a silicone resin or an alkyd resin, if necessary. The surface tension of such a peelable sheet 11 or 21 is 40
It is preferably not more than mN / m, more preferably in the range of 20 to 40 mN / m, and particularly preferably in the range of 30 to 35 mN / m.

【0025】剥離性シートの表面張力が40mN/mより大き
いと、接着性薄膜層の剥離性シートへの密着性が高くな
り、チップ体への転写ができないことがある。一方、20
mN/m未満では、研削工程で剥離性シートと接着性薄膜層
の間に研削水が侵入しウエハを破損するおそれがあり、
また接着性薄膜層の性状によっては剥離性シート上に接
着性薄膜層を形成できないことがある。
If the surface tension of the releasable sheet is greater than 40 mN / m, the adhesiveness of the adhesive thin film layer to the releasable sheet will increase, and transfer to the chip may not be possible. Meanwhile, 20
If it is less than mN / m, the grinding water may enter between the peelable sheet and the adhesive thin film layer in the grinding process and damage the wafer,
Further, depending on the properties of the adhesive thin film layer, the adhesive thin film layer may not be formed on the peelable sheet.

【0026】上記のような剥離性シート11または21
の厚さは、通常5〜300μmであり、好ましくは10
〜200μmである。本発明の半導体装置の製造方法に
おいては、接着性薄膜の形成工程、切断分離工程、チッ
プの接着固定工程が行なわれる。また、所望により裏面
研削工程が行なわれても良い。
The peelable sheet 11 or 21 as described above
Is usually from 5 to 300 μm, preferably from 10 to 300 μm.
200200 μm. In the method of manufacturing a semiconductor device according to the present invention, a step of forming an adhesive thin film, a step of cutting and separating, and a step of bonding and fixing chips are performed. Further, a back surface grinding step may be performed if desired.

【0027】接着性薄膜層12または22の半導体ウエ
ハ1への形成は、貼付装置による貼付によって行なわれ
る。貼付の際の圧力は、貼付装置の貼付方法(ゴムロー
ラー式、真空密着式)により適宜に設定されるが、加圧
条件が弱過ぎるとウエハに接着性薄膜層が密着しないこ
とがあり、また強過ぎるとウエハを破損することがあ
る。
The formation of the adhesive thin film layer 12 or 22 on the semiconductor wafer 1 is performed by sticking with a sticking device. The pressure at the time of sticking is appropriately set according to the sticking method of the sticking device (rubber roller type, vacuum contact type), but if the pressing condition is too weak, the adhesive thin film layer may not adhere to the wafer, If too strong, the wafer may be damaged.

【0028】貼付温度は、使用する接着性薄膜層の性質
による。通常は、バインダー樹脂の可塑化温度以上18
0℃以下の温度が好ましい。なお、粘接着剤を使用した
場合は、常温で貼付できる。貼付温度が高過ぎると、ウ
エハの研削後、ウエハに反りを発生させるおそれがあ
る。またウエハの回路面に設けられる導通用突起物の高
さが50μm以上となるようなウエハの回路面の凹凸が
大きい場合は、標準の加圧条件よりも強い条件または高
い貼付温度で貼付を行ない、ウエハ回路面に密着させる
ことが好ましい。
The application temperature depends on the properties of the adhesive thin film layer used. Normally, the plasticization temperature of the binder resin is 18
Temperatures below 0 ° C. are preferred. When an adhesive is used, it can be stuck at room temperature. If the sticking temperature is too high, the wafer may be warped after the wafer is ground. In the case where the irregularities on the circuit surface of the wafer are large such that the height of the conductive projection provided on the circuit surface of the wafer is 50 μm or more, the bonding is performed under stronger conditions than the standard pressing conditions or at a higher bonding temperature. It is preferable that the wafer be brought into close contact with the wafer circuit surface.

【0029】本発明においては、半導体ウエハ1の切断
分離等の各種の所要工程をウエハ1の回路面に接着性薄
膜層12または22が貼着された状態で行なう。また、
切断分離に先立ち、必要に応じ、半導体ウエハ1の裏面
研削を行なってもよい。半導体ウエハ1の裏面研削工程
は、回路形成時においてウエハ裏面に形成される酸化物
被膜を除去し、ウエハの厚さを所定の厚さまで研削する
工程である。裏面研削は、たとえば研削装置等の従来公
知の方法により行いうる。本発明においては、接着性薄
膜層が、裏面研削時において、ウエハ回路面の保護シー
トとしての機能をも発現する。
In the present invention, various necessary steps such as cutting and separating the semiconductor wafer 1 are performed with the adhesive thin film layer 12 or 22 adhered to the circuit surface of the wafer 1. Also,
Prior to the cutting and separation, the back surface of the semiconductor wafer 1 may be ground if necessary. The backside grinding step of the semiconductor wafer 1 is a step of removing an oxide film formed on the backside of the wafer during circuit formation and grinding the wafer to a predetermined thickness. The back surface grinding can be performed by a conventionally known method such as a grinding device. In the present invention, the adhesive thin film layer also functions as a protective sheet for the wafer circuit surface when grinding the back surface.

【0030】次に、ウエハの切断分離を行う。ウエハの
切断分離は、通常のダイシング装置を用いて行なわれ
る。この際、ウエハの裏面にダイシングテープを貼着
し、これを介して円形のフレームに固定してダイシング
が行なわれる。続いて、ピックアップ装置やチップボン
ダーを用いて切断分離されたチップを個別にチップトレ
ー等に回収する。
Next, the wafer is cut and separated. The wafer is cut and separated using a normal dicing apparatus. At this time, dicing tape is adhered to the back surface of the wafer, and the wafer is fixed to a circular frame via the dicing tape to perform dicing. Subsequently, the chips cut and separated using a pickup device or a chip bonder are individually collected in a chip tray or the like.

【0031】このような所要の工程を経て、図2または
図5に示すように、回路面に接着性薄膜層が形成された
チップ2が得られる。本発明において接着性薄膜層は、
剥離性シートを用いる場合は、剥離性シートの剥離面上
に接着剤の組成物を塗布し、必要に応じて乾燥するか、
薄膜状にキャスト成形した後、剥離性シートを積層して
形成される。また剥離性シートを用いない場合は、キャ
スト成形等により製造される。
Through such required steps, a chip 2 having an adhesive thin film layer formed on a circuit surface is obtained as shown in FIG. 2 or FIG. In the present invention, the adhesive thin film layer is
When using a releasable sheet, apply the adhesive composition on the release surface of the releasable sheet, or dry if necessary,
After being cast into a thin film, it is formed by laminating release sheets. When a peelable sheet is not used, it is manufactured by cast molding or the like.

【0032】接着性薄膜層に剥離性シートが積層されて
いる場合、剥離性シートは、切断分離された個別のチッ
プを、チップ搭載用基板に載置する前に、接着性薄膜層
から剥離される。剥離性シートを接着性薄膜層から剥離
する方法としては、幅広の粘着シートを剥離性シートの
全面に貼り付けた後に鋭角で引き剥がすことなどにより
行なわれる。剥離性シートの剥離は切断分離の後に行な
うことが好ましいが、切断分離の前であってもよい。
When a peelable sheet is laminated on the adhesive thin film layer, the peelable sheet is peeled from the adhesive thin film layer before the cut and separated individual chips are placed on the chip mounting substrate. You. As a method of peeling the peelable sheet from the adhesive thin film layer, a wide pressure-sensitive adhesive sheet is attached to the entire surface of the peelable sheet and then peeled off at an acute angle. The peeling of the releasable sheet is preferably performed after cutting and separating, but may be performed before cutting and separating.

【0033】次いで、本発明に係る半導体装置の製造方
法においては、チップ2を、接着性薄膜層を介して、チ
ップ搭載用基板30上に載置し、チップ2の固着を行う
(図3または図6参照)。チップ2には、表面に所定の
回路が形成され、さらに回路表面にチップ搭載基板30
と導通するための電極が形成されている。該電極は、好
ましくは金、銅、ハンダ等の導電材料からなる突起物
(導通用突起物31)からなり、その高さおよび径は、
通常10〜100μm程度である。またチップ2の回路
面の電極以外の部分は絶縁被膜が形成されている。
Next, in the method of manufacturing a semiconductor device according to the present invention, the chip 2 is mounted on the chip mounting substrate 30 via the adhesive thin film layer, and the chip 2 is fixed (FIG. 3 or FIG. 3). See FIG. 6). A predetermined circuit is formed on the surface of the chip 2, and the chip mounting substrate 30 is further formed on the circuit surface.
And an electrode for conducting with the electrode. The electrode is preferably made of a projection (conduction projection 31) made of a conductive material such as gold, copper, or solder.
Usually, it is about 10 to 100 μm. An insulating coating is formed on the circuit surface of the chip 2 other than the electrodes.

【0034】チップ搭載用基板30は、たとえばポリイ
ミドなどの絶縁性で耐熱性のシート材料上に、銅箔等の
導電材料で形成された回路が積層されている。この回路
は図8に示すように、チップの電極に相対する端部と、
外部装置と導通するための電極用端部を継ぐ複数個の配
線からなる。接着性薄膜層に絶縁性接着剤を用いる場合
は、チップの電極に相対する端部に導通用突起物31’
を設けることが好ましい。この突起物は、上記のチップ
上の突起物と同様に、金、銅、ハンダ等の導電材料から
なり、その高さおよび径は、通常10〜100μm程度
である。
The chip mounting substrate 30 has a circuit made of a conductive material such as copper foil laminated on an insulating and heat-resistant sheet material such as polyimide. This circuit, as shown in FIG. 8, has an end facing the electrode of the chip,
It is composed of a plurality of wirings connecting the electrode ends for conducting with an external device. When an insulating adhesive is used for the adhesive thin film layer, a conductive projection 31 ′ is attached to the end of the chip opposite to the electrode.
Is preferably provided. The protrusions are made of a conductive material such as gold, copper, or solder similarly to the protrusions on the chip, and the height and diameter thereof are usually about 10 to 100 μm.

【0035】接着性薄膜層が異方導電性接着剤からなる
場合には、チップ2をチップ搭載用基板30に載置後、
圧着することで、異方導電性接着剤層12の厚さ方向へ
の導電性が発現し、チップ2とチップ搭載用基板30と
の導通が確保される。この場合、チップ2およびチップ
搭載用基板30は、導通用突起物31を及び31’の両
方を有するものであってもよく、またどちらか一方のみ
有するものであってもよい。図3に示したものは、導通
用突起物31を有するチップ2を用いた例である。
When the adhesive thin film layer is made of an anisotropic conductive adhesive, after the chip 2 is mounted on the chip mounting substrate 30,
By performing pressure bonding, conductivity in the thickness direction of the anisotropic conductive adhesive layer 12 is developed, and conduction between the chip 2 and the chip mounting substrate 30 is ensured. In this case, the chip 2 and the chip mounting substrate 30 may have both the conductive projections 31 and 31 ′, or may have only one of them. FIG. 3 shows an example in which a chip 2 having a conductive projection 31 is used.

【0036】なお、異方導電性接着剤層12が、熱硬化
性異方導電性接着剤または粘接着剤型異方導電性接着剤
からなる場合には、チップ2を該異方導電性接着剤層1
2を介してチップ搭載用基板30上に載置した後、該異
方導電性接着剤の硬化温度以上に加熱して、チップ2の
固着を行う。また、異方導電性接着剤層12が、熱可塑
性異方導電性接着剤からなる場合には、チップ2を該熱
可塑性異方導電性接着剤層12を介してチップ搭載用基
板30上に載置した後、熱圧着を行って、チップの固着
を行う。
When the anisotropically conductive adhesive layer 12 is made of a thermosetting anisotropically conductive adhesive or an adhesive-type anisotropically conductive adhesive, the chip 2 is attached to the anisotropically conductive adhesive. Adhesive layer 1
After being placed on the chip mounting substrate 30 through the substrate 2, the chip 2 is fixed by heating to a temperature higher than the curing temperature of the anisotropic conductive adhesive. When the anisotropic conductive adhesive layer 12 is made of a thermoplastic anisotropic conductive adhesive, the chip 2 is placed on the chip mounting substrate 30 via the thermoplastic anisotropic conductive adhesive layer 12. After mounting, the chips are fixed by thermocompression bonding.

【0037】また、前記接着性薄膜層12が絶縁性接着
剤からなる場合には、チップ2として、回路上に導通用
突起物31を有するチップを用いるか、あるいは導通用
突起物31’を有するチップ搭載用基板30を用いる。
もちろんこれらを併用してもよい。図6に示したもの
は、導通用突起物31を有するチップ2および導通用突
起物31’を有するチップ搭載用基板30を併用した例
である。
When the adhesive thin film layer 12 is made of an insulating adhesive, a chip having a conductive projection 31 on a circuit or a conductive projection 31 'is used as the chip 2. The chip mounting substrate 30 is used.
Of course, these may be used in combination. FIG. 6 shows an example in which the chip 2 having the conductive projections 31 and the chip mounting substrate 30 having the conductive projections 31 'are used in combination.

【0038】この場合には、回路面に絶縁性接着剤層2
2が転写されたチップ2を、該絶縁性接着剤層22を介
して、導通用突起物31、31’を有するチップ搭載用
基板30上に載置する。この時点では、チップ2とチッ
プ搭載用基板30との導通はとれていないので、絶縁性
接着剤22を流動化させて該導通用突起物31、31’
を介してチップ2とチップ搭載用基板30とを接続し、
導通を確保した後、チップ2の固着を行う。
In this case, the insulating adhesive layer 2 is formed on the circuit surface.
The chip 2 to which the pattern 2 has been transferred is placed on the chip mounting substrate 30 having the conductive projections 31 and 31 ′ via the insulating adhesive layer 22. At this time, the conduction between the chip 2 and the chip mounting substrate 30 has not been established, so that the insulating adhesive 22 is fluidized and the conduction protrusions 31 and 31 ′ are formed.
Is connected to the chip 2 and the chip mounting substrate 30 through
After the conduction is secured, the chip 2 is fixed.

【0039】上記絶縁性接着剤層22が、熱硬化性絶縁
性接着剤または粘接着剤型絶縁性接着剤からなる場合に
は、チップ2を該絶縁性接着剤層22を介してチップ搭
載用基板上30に載置した後、該絶縁性接着剤を硬化し
ないように加熱して、流動化させ、該導通用突起物3
1、31’を介してチップ2とチップ搭載用基板30と
の間の導通を確保した後、絶縁性接着剤の硬化温度以上
に加熱して、チップの固着を行う。
When the insulating adhesive layer 22 is made of a thermosetting insulating adhesive or a pressure-sensitive adhesive type insulating adhesive, the chip 2 is mounted via the insulating adhesive layer 22. After being placed on the substrate 30 for heating, the insulating adhesive is heated so as not to be hardened and fluidized, and the conductive protrusions 3
After securing the conduction between the chip 2 and the chip mounting substrate 30 via 1, 31 ′, the chip is fixed by heating to a temperature higher than the curing temperature of the insulating adhesive.

【0040】また、上記絶縁性接着剤層22が、熱可塑
性絶縁性接着剤からなる場合には、チップ2を該熱可塑
性絶縁性接着剤を介してチップ搭載用基板30上に載置
した後、該熱可塑性絶縁性接着剤を加熱して、流動化さ
せ、該導通用突起物31、31’を介してチップ2とチ
ップ搭載用基板30との間の導通を確保した後、該熱可
塑性絶縁性接着剤の可塑化温度未満に冷却して、チップ
の固着を行う。
When the insulating adhesive layer 22 is made of a thermoplastic insulating adhesive, the chip 2 is placed on the chip mounting substrate 30 via the thermoplastic insulating adhesive. Then, the thermoplastic insulating adhesive is heated and fluidized to secure conduction between the chip 2 and the chip mounting substrate 30 via the conduction protrusions 31 and 31 ′. The chip is fixed by cooling to below the plasticizing temperature of the insulating adhesive.

【0041】チップ2とチップ搭載用基板30との接着
固定は、フリップチップボンダー等により行うことがで
きる。フリップチップボンダーは、加熱条件、加圧条件
を精度良く設定できるものが好ましい。このような本発
明に係る半導体装置の製造方法によれば、チップ2とチ
ップ搭載用基板30とを、空間を生じることなく、密着
した状態で固着できるので、樹脂封止を行っても、ボイ
ドのない、信頼性の高い、半導体装置を得ることができ
る。
The bonding between the chip 2 and the chip mounting substrate 30 can be performed by a flip chip bonder or the like. It is preferable that the flip chip bonder can set the heating condition and the pressing condition with high accuracy. According to such a method of manufacturing a semiconductor device according to the present invention, the chip 2 and the chip mounting substrate 30 can be fixed in a tight contact state without generating a space. And a highly reliable semiconductor device can be obtained.

【0042】樹脂封止に用いられる樹脂としては、従来
より半導体装置の樹脂封止に用いられてきた種々の熱硬
化性樹脂が用いられる。このような熱硬化性樹脂として
は、具体的には、クレゾールノボラック型エポキシ、ナ
フタレン型エポキシ、ビフェニル型エポキシあるいは芳
香族多官能型エポキシを主原料とし、フェノールノボラ
ック等の一般に用いられる硬化剤およびシリカ、シリコ
ーン、カーボン、フィラー等を混合した樹脂が好ましく
用いられる。加熱硬化の条件は、使用する熱硬化性樹脂
の種類に応じて適宜に定められる。
As the resin used for resin sealing, various thermosetting resins conventionally used for resin sealing of semiconductor devices are used. As such a thermosetting resin, specifically, a cresol novolak type epoxy, a naphthalene type epoxy, a biphenyl type epoxy or an aromatic polyfunctional epoxy as a main raw material, a commonly used curing agent such as phenol novolak and silica , Silicone, carbon, a resin mixed with a filler and the like are preferably used. The conditions for heat curing are appropriately determined according to the type of thermosetting resin used.

【0043】[0043]

【発明の効果】このような本発明に係る半導体装置の製
造方法によれば、樹脂封止半導体装置の製造時に、ボイ
ドの発生を防止し、信頼性の高い製品を効率良く製造で
きる。
According to the method of manufacturing a semiconductor device according to the present invention as described above, voids can be prevented from occurring at the time of manufacturing a resin-sealed semiconductor device, and a highly reliable product can be manufactured efficiently.

【0044】[0044]

【実施例】以下本発明を実施例により説明するが、本発
明はこれら実施例に限定されるものではない。なお、半
導体装置の導通評価は、以下のようにして行なった。評
価用のチップとしては、図7に示す大きさが3mm×5mm
で、直径90μm、高さ30μmの金製バンプ(導通用突
起物)が4つ設けられた評価用ダミーチップを用いる。
バンプは、2つが一組となり、金線で導通がとられてい
る。したがって、ウエハには、上記のチップに対応する
ダミー回路が多数設けられている。
EXAMPLES The present invention will be described below with reference to examples, but the present invention is not limited to these examples. The conduction evaluation of the semiconductor device was performed as follows. As a chip for evaluation, the size shown in FIG. 7 is 3 mm × 5 mm.
Then, an evaluation dummy chip provided with four gold bumps (conduction projections) having a diameter of 90 μm and a height of 30 μm is used.
The two bumps form a set and are electrically connected by gold wires. Therefore, a large number of dummy circuits corresponding to the above chips are provided on the wafer.

【0045】またチップ搭載用基板としては、図8に示
す上記バンプの位置に対応する配線パターンを有する基
板を評価用基板として用いる。
As the chip mounting substrate, a substrate having a wiring pattern corresponding to the position of the bump shown in FIG. 8 is used as an evaluation substrate.

【0046】[0046]

【実施例1】バインダー樹脂としてアクリル樹脂10重
量部と、ウレタン系アクリレートオリゴマー10重量部
と、2,2-ジメトキシ-2-フェニルアセトン0.3重量部
と、エポキシ樹脂105重量部と、ジシアンジアミド
2.12重量部と、アクリル系ゴム微粒子5重量部と、
芳香族系ポリイソシアナート2重量部とからなる粘接着
剤組成物を、剥離性シートとして表面張力35 mN/mのポ
リエチレンフィルム(厚さ:100μm)に塗布・乾燥し、
厚さ60μmの絶縁性粘接着剤層を有する粘接着テープ
を得、これを剥離性シートを有する絶縁性接着性薄膜層
とした。
Example 1 10 parts by weight of an acrylic resin as a binder resin, 10 parts by weight of a urethane acrylate oligomer, 0.3 parts by weight of 2,2-dimethoxy-2-phenylacetone, 105 parts by weight of an epoxy resin, and dicyandiamide 2 .12 parts by weight, 5 parts by weight of acrylic rubber fine particles,
An adhesive composition comprising 2 parts by weight of an aromatic polyisocyanate is applied to a polyethylene film (thickness: 100 μm) having a surface tension of 35 mN / m as a releasable sheet and dried,
An adhesive tape having an insulating adhesive layer having a thickness of 60 μm was obtained, and this was used as an insulating adhesive thin film layer having a peelable sheet.

【0047】前記した回路パターンを有する半導体ウエ
ハ(6インチ、厚さ625μm)の回路面に、上記接着性薄
膜層を常温で圧着(テープ貼付装置:リンテック社製、
Adwill RAD-3500使用)した。半導体ウエハ裏面を研削
(研削装置:ディスコ社製、DFG-840使用)して、厚さ
を300μmにし、その後研削面にダイシングテープ(Adwi
ll G-19、リンテック社製)を貼付後、ダイシング装置
(ディスコ社製、DAD-2H/6T)を使用して回路パターン
毎に切断分離し、チップを得た。
The above-mentioned adhesive thin film layer is pressure-bonded to a circuit surface of a semiconductor wafer (6 inches, thickness: 625 μm) having the above-mentioned circuit pattern at normal temperature (tape attaching device: manufactured by Lintec Corporation).
Adwill RAD-3500 used). The back side of the semiconductor wafer is ground (grinding device: DFG-840, manufactured by Disco) to a thickness of 300 μm, and then the dicing tape (Adwi
ll G-19, manufactured by Lintec Co., Ltd., and cut and separated for each circuit pattern using a dicing apparatus (manufactured by Disco, DAD-2H / 6T) to obtain chips.

【0048】回路面側に紫外線照射(紫外線照射装置:
リンテック社製、Adwill RAD 2000m/6使用)を行い、次
いで、接着性薄膜層上の剥離性シート上に強粘着テープ
を貼付し、これを剥離することで、接着性薄膜層上の剥
離性シートを剥離し、チップの回路面に接着性薄膜層を
残存させた。得られたチップをピックアップし、チップ
トレーに収納した。
The circuit surface side is irradiated with ultraviolet light (ultraviolet irradiation device:
Lintec, Adwill RAD 2000m / 6), then apply a strong adhesive tape on the peelable sheet on the adhesive thin film layer, and peel it off to remove the peelable sheet on the adhesive thin film layer. Was removed to leave an adhesive thin film layer on the circuit surface of the chip. The obtained chips were picked up and stored in a chip tray.

【0049】次いでフリップチップボンダー(九州松下
電器産業(株)製、FB30T-M)を用い、前記評価用基板
に実装した。実装の際の、ステージ温度は60℃、ヘッ
ド温度は180℃、荷重は20N、時間は60秒とした。
実装後、150℃のオーブン中で60分保持し、粘接着
剤層を完全に硬化させた。各端子間の抵抗値を、低抵抗
率計(三菱化学製、Loresta-GP MCP-T600)を用いて測
定し、ab間およびcd間の導通と、その他の端子間の
絶縁を確認した。
Next, a flip chip bonder (FB30T-M, manufactured by Kyushu Matsushita Electric Industrial Co., Ltd.) was mounted on the evaluation board. At the time of mounting, the stage temperature was 60 ° C., the head temperature was 180 ° C., the load was 20 N, and the time was 60 seconds.
After mounting, the substrate was kept in an oven at 150 ° C. for 60 minutes to completely cure the adhesive layer. The resistance value between the terminals was measured using a low resistivity meter (Loresta-GP MCP-T600, manufactured by Mitsubishi Chemical Corporation), and continuity between ab and cd and insulation between other terminals were confirmed.

【0050】[0050]

【実施例2】アクリル樹脂10重量部と、エポキシ樹脂
80重量部と、ジシアンジアミド2重量部とからなる粘
接着剤組成物に、平均粒径6〜10μmのフレーク状銀
粉を、樹脂固形分100重量部に対し、10重量部加
え、異方導電性粘接着剤組成物を得た。得られた粘接着
剤組成物を、剥離性シートとして表面張力35 mN/mのポ
リエチレンフィルム(厚さ:100μm)に塗布・乾燥し、
厚さ40μmの異方導電性の粘接着剤層を有する粘接着
テープを得、これを剥離性シートを有する接着性薄膜層
とした。
Example 2 A flake silver powder having an average particle diameter of 6 to 10 μm was added to an adhesive composition comprising 10 parts by weight of an acrylic resin, 80 parts by weight of an epoxy resin, and 2 parts by weight of dicyandiamide, with a resin solid content of 100%. By adding 10 parts by weight to the parts by weight, an anisotropic conductive adhesive composition was obtained. The obtained adhesive composition is applied to a polyethylene film (thickness: 100 μm) having a surface tension of 35 mN / m as a peelable sheet and dried,
An adhesive tape having an anisotropic conductive adhesive layer having a thickness of 40 μm was obtained, and this was used as an adhesive thin film layer having a peelable sheet.

【0051】実施例1と同様にして、前記した回路パタ
ーンを有する半導体ウエハ(6インチ、厚さ625μm)の
回路面に、上記接着性薄膜層を常温で圧着した。また実
施例1と同様にして、半導体ウエハ裏面を研削して、厚
さを300μmにし、その後研削面にダイシングテープを貼
付後、回路パターン毎に切断分離し、チップを得た。次
いで、粘接着テープのポリエチレンフィルム上に強粘着
テープを貼付し、これを剥離することで、粘接着テープ
のポリエチレンフィルムを剥離し、チップの回路面に粘
接着剤層を残存させた。チップをピックアップし、チッ
プトレーに収納した。
In the same manner as in Example 1, the adhesive thin film layer was pressure-bonded to a circuit surface of a semiconductor wafer (6 inches, thickness: 625 μm) having the above-mentioned circuit pattern at normal temperature. Further, in the same manner as in Example 1, the back surface of the semiconductor wafer was ground to a thickness of 300 μm. Thereafter, a dicing tape was attached to the ground surface, and cut and separated for each circuit pattern to obtain a chip. Then, a strong adhesive tape was stuck on the polyethylene film of the adhesive tape, and by peeling it, the polyethylene film of the adhesive tape was peeled off, and the adhesive layer was left on the circuit surface of the chip. . The chips were picked up and stored in a chip tray.

【0052】次いでフリップチップボンダーを用い、前
記評価用基板に実装した。実装の際の、ステージ温度は
60℃、ヘッド温度は130℃、荷重は20N、時間は6
0秒とした。実装後、150℃のオーブン中で60分保
持し、粘接着剤層を完全に硬化させた。各端子間の抵抗
値を、低抵抗率計を用いて測定し、ab間およびcd間
の導通と、その他の端子間の絶縁を確認した。
Next, a flip chip bonder was used to mount on the evaluation board. During mounting, the stage temperature is 60 ° C, the head temperature is 130 ° C, the load is 20N, and the time is 6
0 seconds. After mounting, the substrate was kept in an oven at 150 ° C. for 60 minutes to completely cure the adhesive layer. The resistance value between each terminal was measured using a low resistivity meter, and continuity between ab and cd and insulation between other terminals were confirmed.

【0053】[0053]

【実施例3】剥離性シートとしてアルキッド系剥離剤に
より剥離処理したポリエチレンナフタレートフィルム
(厚さ25μm:融点272℃:表面張力34mN/m)の
処理面に熱可塑性ポリイミド樹脂(Tg=115℃:宇部興産
社製)からなる接着剤を塗布後、乾燥し、厚さ60μm
の絶縁性接着剤からなる接着性薄膜層を有するシートを
作成した。
Example 3 A thermoplastic polyimide resin (Tg = 115 ° C.) was applied to a treated surface of a polyethylene naphthalate film (thickness: 25 μm; melting point: 272 ° C .; surface tension: 34 mN / m) which had been subjected to release treatment with an alkyd-based release agent as a release sheet. After applying an adhesive consisting of Ube Industries, Ltd.), it is dried and has a thickness of 60 μm.
A sheet having an adhesive thin film layer made of an insulating adhesive was prepared.

【0054】実施例1と同様にして、前記した回路パタ
ーンを有する半導体ウエハ(6インチ、厚さ625μm)の
回路面に、上記接着性薄膜層を常温で圧着した。また実
施例1と同様にして、半導体ウエハ裏面を研削して、厚
さを300μmにし、その後研削面にダイシングテープを貼
付後、回路パターン毎に切断分離し、チップを得た。次
いで、接着性薄膜層上のポリエチレンナフタレートフィ
ルム上に強粘着テープを貼付し、これを剥離すること
で、接着性薄膜層上のポリエチレンナフタレートフィル
ムを剥離し、チップの回路面に接着性薄膜層を残存させ
た。得られたチップをピックアップし、チップトレーに
収納した。
In the same manner as in Example 1, the adhesive thin film layer was pressure-bonded to a circuit surface of a semiconductor wafer (6 inches, thickness: 625 μm) having the above-mentioned circuit pattern at normal temperature. Further, in the same manner as in Example 1, the back surface of the semiconductor wafer was ground to a thickness of 300 μm. Thereafter, a dicing tape was attached to the ground surface, and cut and separated for each circuit pattern to obtain a chip. Then, a strong adhesive tape is stuck on the polyethylene naphthalate film on the adhesive thin film layer, and the polyethylene naphthalate film on the adhesive thin film layer is peeled off by peeling off the adhesive tape. The layer was left. The obtained chips were picked up and stored in a chip tray.

【0055】次いでフリップチップボンダーを用い、前
記評価用基板に実装した。実装の際の、ステージ温度は
150℃、ヘッド温度は180℃、荷重は20N、時間は
60秒とした。各端子間の抵抗値を、低抵抗率計を用い
て測定し、ab間およびcd間の導通と、その他の端子
間の絶縁を確認した。
Then, using a flip chip bonder, the chip was mounted on the evaluation board. At the time of mounting, the stage temperature was 150 ° C., the head temperature was 180 ° C., the load was 20 N, and the time was 60 seconds. The resistance value between each terminal was measured using a low resistivity meter, and continuity between ab and cd and insulation between other terminals were confirmed.

【0056】[0056]

【実施例4】常温で固型のエポキシ樹脂(エポキシ当量
3000〜5000)90重量部と、常温で液状のエポ
キシ樹脂(エポキシ当量184〜194)10重量部
と、ジシアンジアミド2重量部とからなる接着剤組成物
を、溶剤で希釈した状態で、実施例3で用いた剥離性シ
ートに塗布後、乾燥し、厚さ60μmの絶縁性の接着性
薄膜層を有するシートを作成した。
Example 4 Bonding consisting of 90 parts by weight of a solid epoxy resin (epoxy equivalent: 3000 to 5000) at room temperature, 10 parts by weight of epoxy resin liquid at room temperature (epoxy equivalent: 184 to 194), and 2 parts by weight of dicyandiamide. The agent composition was diluted with a solvent, applied to the release sheet used in Example 3, and then dried to prepare a sheet having a 60 μm-thick insulating adhesive thin film layer.

【0057】実施例1と同様にして、前記した回路パタ
ーンを有する半導体ウエハ(6インチ、厚さ625μm)の
回路面に、上記接着性薄膜層を常温で圧着した。また実
施例1と同様にして、半導体ウエハ裏面を研削して、厚
さを300μmにし、その後研削面にダイシングテープを貼
付後、回路パターン毎に切断分離し、チップを得た。次
いで、接着性薄膜層上のポリエチレンナフタレートフィ
ルム上に強粘着テープを貼付し、これを剥離すること
で、接着性薄膜上のポリエチレンナフタレートフィルム
を剥離し、チップの回路面に接着性薄膜を残存させた。
得られたチップをピックアップし、チップトレーに収納
した。
In the same manner as in Example 1, the adhesive thin film layer was pressure-bonded to a circuit surface of a semiconductor wafer (6 inches, thickness: 625 μm) having the above-mentioned circuit pattern at normal temperature. Further, in the same manner as in Example 1, the back surface of the semiconductor wafer was ground to a thickness of 300 μm. Thereafter, a dicing tape was attached to the ground surface, and cut and separated for each circuit pattern to obtain a chip. Next, a strong adhesive tape is stuck on the polyethylene naphthalate film on the adhesive thin film layer, and by peeling it off, the polyethylene naphthalate film on the adhesive thin film is peeled off, and the adhesive thin film is applied to the circuit surface of the chip. It was left.
The obtained chips were picked up and stored in a chip tray.

【0058】次いでフリップチップボンダーを用い、前
記評価用基板に実装した。実装の際の、ステージ温度は
60℃、ヘッド温度は130℃、荷重は20N、時間は6
0秒とした。実装後、150℃のオーブン中で60分保
持し、粘接着剤層を完全に硬化させた。各端子間の抵抗
値を、低抵抗率計を用いて測定し、ab間およびcd間
の導通と、その他の端子間の絶縁を確認した。
Next, using a flip chip bonder, the circuit board was mounted on the evaluation board. During mounting, the stage temperature is 60 ° C, the head temperature is 130 ° C, the load is 20N, and the time is 6
0 seconds. After mounting, the substrate was kept in an oven at 150 ° C. for 60 minutes to completely cure the adhesive layer. The resistance value between each terminal was measured using a low resistivity meter, and continuity between ab and cd and insulation between other terminals were confirmed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明に係る製造方法の工程の概略を示す。FIG. 1 schematically shows the steps of the manufacturing method according to the present invention.

【図2】 本発明に係る製造方法の工程の概略を示す。FIG. 2 shows an outline of the steps of the manufacturing method according to the present invention.

【図3】 本発明に係る製造方法の工程の概略を示す。FIG. 3 shows an outline of the steps of the manufacturing method according to the present invention.

【図4】 本発明に係る他の製造方法の工程の概略を示
す。
FIG. 4 shows an outline of the steps of another manufacturing method according to the present invention.

【図5】 本発明に係る他の製造方法の工程の概略を示
す。
FIG. 5 shows an outline of the steps of another manufacturing method according to the present invention.

【図6】 本発明に係る他の製造方法の工程の概略を示
す。
FIG. 6 shows an outline of the steps of another manufacturing method according to the present invention.

【図7】 本発明の実施例で用いた評価用チップの平面
図を示す。
FIG. 7 shows a plan view of an evaluation chip used in an example of the present invention.

【図8】 本発明の実施例で用いた評価用基板の平面図
を示す。
FIG. 8 shows a plan view of an evaluation substrate used in an example of the present invention.

【符号の説明】[Explanation of symbols]

1…半導体ウエハ、2…チップ、11…剥離性シート、
12…接着性薄膜層(異方導電性接着剤層)、21…剥
離性シート、22…接着性薄膜層(絶縁性接着剤層)、
30…チップ搭載用基板、31,31’…導通用突起物
DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer, 2 ... Chip, 11 ... Peelable sheet,
12: adhesive thin film layer (anisotropic conductive adhesive layer), 21: peelable sheet, 22: adhesive thin film layer (insulating adhesive layer),
30: chip mounting substrate, 31, 31 ': conductive projection

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 表面に回路が形成された半導体ウエハの
回路面に、接着性薄膜層を形成し、 該半導体ウエハを、回路毎に個別のチップに切断分離
し、 該個別のチップを該接着性薄膜層を介して、チップ搭載
用基板の所定位置に載置し、 該個別のチップと該チップ搭載用基板との導通を確保し
ながら該個別のチップを該チップ搭載用基板に接着固定
することを特徴とする半導体装置の製造方法。
1. An adhesive thin film layer is formed on a circuit surface of a semiconductor wafer having a circuit formed on its surface, and the semiconductor wafer is cut and separated into individual chips for each circuit, and the individual chips are bonded to each other. Placed on a predetermined position of the chip mounting substrate via the conductive thin film layer, and the individual chip is bonded and fixed to the chip mounting substrate while ensuring conduction between the individual chip and the chip mounting substrate. A method for manufacturing a semiconductor device, comprising:
【請求項2】 半導体ウエハを個別のチップに切断分離
する前に、該接着性薄膜層により半導体ウエハの回路面
を保護しながら該半導体ウエハの裏面を研削することを
特徴とする請求項1記載の半導体装置の製造方法。
2. The semiconductor wafer according to claim 1, wherein the back surface of the semiconductor wafer is ground while protecting the circuit surface of the semiconductor wafer with the adhesive thin film layer before cutting and separating the semiconductor wafer into individual chips. Of manufacturing a semiconductor device.
【請求項3】 前記接着性薄膜層が片面に剥離性シート
を有し、該接着性薄膜層の剥離性シートが形成されてい
ない面を介して、該接着性薄膜層を半導体ウエハの回路
面に貼付することにより、半導体ウエハの回路面に接着
性薄膜層を形成し、 個別のチップを、チップ搭載用基板に載置する前に、該
剥離性シートを接着性薄膜層から剥離することを特徴と
する請求項1または2に記載の半導体装置の製造方法。
3. The adhesive thin film layer has a peelable sheet on one side, and the adhesive thin film layer is connected to a circuit surface of a semiconductor wafer through a surface of the adhesive thin film layer on which the peelable sheet is not formed. To form an adhesive thin film layer on the circuit surface of the semiconductor wafer, and to separate the chip from the adhesive thin film layer before placing the individual chips on the chip mounting substrate. The method for manufacturing a semiconductor device according to claim 1, wherein:
【請求項4】 該接着性薄膜層が異方導電性接着剤から
なることを特徴とする請求項1〜3の何れかに記載の半
導体装置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 1, wherein said adhesive thin film layer is made of an anisotropic conductive adhesive.
【請求項5】 該接着性薄膜層が絶縁性接着剤からな
り、チップの回路上および/またはチップ搭載用基板上
に導通用突起物を有し、該接着性薄膜層を加熱により流
動化させて該導通用突起物を介してチップとチップ搭載
用基板との間に導通を確保することを特徴とする請求項
1〜3の何れかに記載の半導体装置の製造方法。
5. The adhesive thin film layer is made of an insulating adhesive, has conductive projections on a chip circuit and / or a chip mounting substrate, and makes the adhesive thin film layer fluidized by heating. 4. The method of manufacturing a semiconductor device according to claim 1, wherein conduction is ensured between the chip and the chip mounting substrate through the conduction protrusion.
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