JP2001135730A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a wide channel region of a memory cell transistor and easily ensure an amount of current flowing a channel in reading necessary for a multilevel control technology even if a micro-patterning is advanced in a floating gate type semiconductor memory device. SOLUTION: A semiconductor memory device has a diffusion layer 3, which is formed straight on a semiconductor substrate 1 and becomes a source region and a drain region, silicon oxide film 7 to be a gate insulating film, floating gate electrode 15, control gate electrode 13, first interlayer dielectric 9, erasing gate electrode 17, tunneling insulating film 16, second interlayer dielectric 11, and a side wall insulating film 14. An element isolating insulating film 6 is arranged, only under the erasing gate electrode 17 between respective memory cells and an element isolating insulating 6 is omitted which is arranged also between the erasing gate electrodes 17 in a conventional semiconductor memory device. This can ensure a wide channel region of a transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a floating gate type EEPROM (Elease) having an erase gate electrode.
critically Erasable Pro
GramableRead Only Memory)
And a method of manufacturing the same.

[0002]

2. Description of the Related Art As an electrically rewritable nonvolatile memory, an EEPROM having a floating gate structure is well known. In this EEPROM, a floating gate electrode is formed via a gate insulating film on a channel region sandwiched between a source region and a drain region formed on a semiconductor substrate, and furthermore, a control is performed on the floating gate electrode via an interlayer insulating film. It has a structure in which a gate electrode is formed.

A description will be given of an example of a writing method of this EEPROM. A voltage is applied to a drain region and a control gate electrode to generate hot electrons in a channel region near a drain of a semiconductor substrate, and the hot electrons are accelerated to a floating gate electrode. This is done by injection. An example of a method for reading the EEPROM is to apply a voltage to the drain region and the control gate electrode and sense (or detect) the amount of current flowing between the source and drain depending on the amount of charge stored in the floating gate electrode. ).
As an erasing method of the EEPROM, a method of electrically erasing by emitting electrons from the floating gate electrode to a source region, a drain region, or a channel region by utilizing a tunneling phenomenon, or a method of electrically erasing the floating gate electrode is used. A separate erase gate electrode is disposed so as to sandwich a tunneling insulating film between the two (see, for example, JP-A-4-340767), an erase voltage is applied to the erase gate electrode, and electrons are transferred from the floating gate electrode to the erase gate. There has been proposed a method of performing erasing by tunneling an electrode.

An EEPROM uses a state corresponding to a threshold voltage (hereinafter referred to as Vt) value of a control gate electrode determined depending on an amount of electric charge stored in each floating gate electrode as a memory. In order to increase the capacity of the device, a multi-value control technique has been proposed in which a plurality of Vt of the floating gate electrode are set instead of the conventional two values of “0” and “1”.

The structure of a floating gate type semiconductor memory device having an erase gate electrode and a method of manufacturing the same as a conventional example will be described below with reference to a schematic plan layout pattern of the semiconductor memory device of FIG. 8 and FIGS.
The process will be described with reference to the schematic sectional views in the order of the steps. 9 to 14, (a) is a cross section taken along the line II ′ of FIG. 8, (b) is a cross section taken along the line II-II ′ of FIG. 8, and (c) is a cross section of FIG.
3 shows a cross section taken along the line III-III ′.

The memory cells of the EEPROM are shown in FIGS.
As shown in FIG. 4, an N-type diffusion layer 3 of a source / drain region serving as a bit line is formed on the surface of a P-type semiconductor substrate 1 so as to be long in the vertical direction. And an electrode structure composed of a three-layer polysilicon film of a floating gate electrode 15, a control gate electrode 13, and an erase gate electrode 17 with a gate oxide film interposed therebetween.

Next, a method of manufacturing the above-described semiconductor memory device will be described with reference to FIGS. First, FIG.
As shown in FIG. 1C, a resist mask pattern 2 for forming N-type diffusion layers of source and drain regions serving as bit lines is formed on one main surface of the semiconductor substrate 1 and arsenic ions are implanted using the mask as a mask. I do. Next, FIGS. 10 (a) to 10 (c)
As shown in FIG.
Is removed, and an N-type diffusion layer 3 is formed by a heat treatment to form source and drain regions serving as bit lines in the memory cell portion. Thereafter, a first silicon oxide film 4 is deposited by a CVD technique, and then a resist mask pattern 5 for element isolation formation is formed.

[0010] Next, as shown in FIGS. 11A to 11 C, the first silicon oxide film 4 is etched by an anisotropic dry etching technique to form an element isolation insulating film 6.
The resist mask pattern 5 for element isolation formation is removed.
Next, a second silicon oxide film 7 is formed on the surface of the semiconductor substrate 1 by thermal oxidation, and a first polycrystalline silicon film 8 is deposited thereon. Next, in order to form the vertical outline of the floating gate electrode 15 shown in FIG. 8 of the first polycrystalline silicon film 8 and the second silicon oxide film 7 thereunder by photoetching technology, Portions are selectively etched away.

Next, as shown in FIGS. 12A to 12C, a first interlayer insulating film 9 made of a silicon oxide film is deposited by a CVD technique. Next, a second polycrystalline silicon film 10 and then a second interlayer insulating film 11 made of a silicon oxide film are sequentially formed, and a resist mask pattern 12 for forming a control gate electrode is formed by photolithography.

Next, as shown in FIGS. 13A to 13C, the second interlayer insulating film 11 is etched by a dry etching technique using the resist mask pattern 12 as a mask to form a resist mask pattern for forming a control gate electrode. The second polycrystalline silicon film 10 is etched by dry etching using the second interlayer insulating film 11 as a mask to form a control gate electrode 13 serving as a word line. Next, a third interlayer insulating film made of a silicon oxide film is deposited on the entire surface. Thereafter, a sidewall insulating film 14 made of a third interlayer insulating film is formed on the control gate electrode 13 and a sidewall portion of the second interlayer insulating film 11 above the control gate electrode 13 by an anisotropic overall etching technique.

Next, as shown in FIGS. 14A to 14C, the side wall insulating film 14 and the second interlayer insulating film 11 are formed.
Is used as a mask to etch the first polycrystalline silicon film 8 by an anisotropic dry etching technique having a high selectivity to oxide film to form a horizontal contour of the floating gate electrode 15 in FIG. The electrode 15 is completed. At this time, the side surface of the floating gate electrode 15 is exposed, and the exposed portion is oxidized to form a tunneling insulating film 16. Then, erase gate electrode 1 made of a polycrystalline silicon film is formed to cover tunneling insulating film 16.
7 is formed.

It is to be noted that a subsequent metal wiring process mainly composed of an aluminum alloy in the upper layer, a protective film forming process and a bonding pad forming process thereon are omitted.

[0013]

However, in the conventional floating gate type semiconductor memory device having an erase gate electrode as described above and its manufacturing method, as the miniaturization advances, the channel region of the memory cell transistor (the element in FIG. Isolation insulating film 6 and source / drain N
(18 regions defined by the dimensions of W and L) surrounded by the mold diffusion layer 3. At this time, there is a problem that the amount of current flowing through the channel at the time of, for example, a read operation decreases due to a decrease in W, that is, a channel width existing below the control gate electrode 13. This point will be further described.

Here, it is assumed that one memory cell of a semiconductor memory device can take n (n ≧ 2) memory states. In this n-value control technique, n types of memory state writing (storing) apply a constant voltage to the control gate electrode 13 and the drain region of the diffusion layer 3 to the memory cell transistor, and change the voltage application time in n ways. This can be achieved by: Hot electrons are accelerated and injected into the floating gate electrode 15 by voltage application. However, if the voltage application time is changed, the longer the time, the more hot electrons are injected. Can be injected.

On the other hand, in reading data from the memory in the n-value control technique, a constant voltage is applied to the control gate electrode 13 and the drain region of the diffusion layer 3, and the magnitude of the current flowing through the channel region 18 of the memory cell transistor at that time is determined. To determine the memory state stored. This is because n kinds of memory states are floating gate electrode 1
This is because the Vt of the memory cell transistor is determined by the amount of charge injected into 5, and the amount of current flowing corresponding to the Vt is also determined.

Here, the current values at the time of reading for each of the n states are Icell (1), Icell (2),... Icell (n). At this time, since W in the channel region of the memory cell transistor decreases, Icell (1), Icell (2),.
As the value of Icell (n) itself decreases, the difference ΔIce between each state
ll (n-1) = Icell (n) -Icell (n-1) (n.gtoreq.2) decreases, and the sensitivity becomes lower than the sensitivity of the sense amplifier for detecting the read current. Had problems.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and makes it easy to secure a large channel width of a memory cell transistor even if miniaturization is advanced in a floating gate type semiconductor memory device having an erase gate electrode. It is an object of the present invention to provide a semiconductor memory device in which a sufficient amount of current between a source and a drain of a memory cell transistor required for a multilevel control technique can be easily secured, and a method of manufacturing the same.

[0018]

According to a first aspect of the present invention, there is provided a semiconductor memory device in which a plurality of memory cell transistors are arranged vertically and horizontally on a semiconductor substrate of one conductivity type. A plurality of diffusion layers of other conductivity type, which are formed long in the vertical direction and serve as a source region and a drain region of the memory cell transistor;
An element isolation insulating film formed so as to sandwich the channel region of one memory cell transistor, and a predetermined region between the source region and the drain region, from the element isolation insulating film to the semiconductor substrate via the gate insulating film. A floating gate electrode formed over the floating gate electrode; a control gate electrode formed above the floating gate electrode; and a control gate formed on the element isolation insulating film and in contact with a side wall of the floating gate electrode via a tunneling insulating film. An erase gate electrode which is in contact with the electrode via an interlayer insulating film is provided.

According to a second aspect of the present invention, in the semiconductor memory device of the first aspect, the control gate electrode is a word line, and the diffusion layer is a bit line.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device in which a plurality of memory cell transistors are arranged in a vertical direction and a horizontal direction on a semiconductor substrate of one conductivity type. A step of forming a diffusion layer of another conductivity type which is provided in the longitudinal direction and is a source region and a drain region of a memory cell transistor; and
Forming a device isolation insulating film provided so as to sandwich the channel regions of the two memory cell transistors in adjacent directions; and, in a predetermined region between the source region and the drain region, via the first insulating film. Forming a film for a floating gate electrode on the element isolation insulating film and on the surface of the semiconductor substrate by forming a control gate electrode on the film for the floating gate electrode via a second insulating film; A step of separating the film for the gate electrode into individual floating gate electrodes, and a step of providing the floating gate electrode on the element isolation insulating film, in contact with the side wall of the floating gate electrode via the tunneling insulating film, and via the control gate electrode and the interlayer insulating film. Forming an erase gate electrode in contact with the semiconductor memory device. Method.

According to the present invention, the channel region of two memory cell transistors is formed in a region surrounded by two adjacent element isolation insulating film regions and two adjacent diffusion layers. Become. In other words, the channel region of the conventional memory cell transistor is separated on both sides by an element isolation insulating film region. By reducing the film region, the area of the channel region increases accordingly. Therefore, even if the pattern size is reduced, the read current flowing through the channel region is large, and a multi-valued memory state can be distinguished.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention and a method of manufacturing the same will now be described with reference to FIG.
7 to FIG. In addition,
2 to FIG. 7, (a) respectively show IV-
1B, a cross section taken along the line VV 'in FIG.
(C) shows a section taken along the line VI-VI 'in FIG.

As shown in FIGS. 1 and 7, a memory cell in a semiconductor memory device according to an embodiment of the present invention has N-type diffusion layers of source and drain regions serving as bit lines on the surface of a P-type semiconductor substrate 1. 3 is formed long in the vertical direction, the element isolation insulating film 6 is formed long in the horizontal direction on the semiconductor substrate 1, and a floating gate electrode 15 and a control gate electrode 13 serving as a word line are formed on these elements with a gate oxide film interposed therebetween. ,
The erasing gate electrode 17 has a structure in which three layers of polysilicon films are stacked. Erase gate electrode 17
Is formed on the element isolation insulating film 6, contacts the side wall of the floating gate electrode 15 via the tunneling insulating film 16, and is in contact with the control gate electrode 13 by the second interlayer insulating film 11 and the sidewall insulating film 14. Insulated.

The element isolation insulating film 6 conventionally exists between all the bits (memory cells) as shown in FIG. 8, whereas in the memory cell of the present embodiment, it is shown in FIGS. Thus, every other bit (memory cell) overlaps with the erase gate electrode 17.
That is, the two adjacent element isolation insulating films 6 and the two adjacent N-type diffusion layers 3 of the source and drain regions are arranged so as to surround the two channel regions 18 of the memory cell transistor. Is the feature. As is clear from this feature, as compared with the conventional layout pattern, a channel region wider by one element isolation insulating film 6 can be obtained. Therefore, even when the pattern is miniaturized, a large current value can be obtained at the time of reading. Thus, it is possible to distinguish and read a plurality of memory states written in one memory cell.

Therefore, in the semiconductor memory device of the present embodiment, the element isolation insulating film 6 is arranged only under the erase gate electrode 17, and there is a region between the memory cells where the element isolation insulating film 6 does not exist. However, even in such a configuration, in this type of storage device, if the charge is injected into the floating gate electrode 15 to write the memory state, the charge is retained, and the charge does not leak to the adjacent memory cell. . Then, the written charge determines Vt of the memory cell transistor, and the Vt of the memory cell transistor is surrounded by two adjacent element isolation insulating films 6 and two adjacent N-type diffusion layers 3 of source and drain regions. If a certain distance between the channel regions 18 is ensured, the memory state can be read normally without the memory cells interfering with each other due to the current of the memory cell transistor corresponding to Vt. The same applies to writing and erasing of memory cells, and element isolation between memory cells can be ensured. Therefore, even if the element isolation insulating film 6 does not exist, the electrical isolation of the element between the bits can be maintained.

The adjacent floating gate electrode 1
If the distance between the adjacent floating gate electrodes 15 (the distance between adjacent W ₁ ) is too small, the capacitance between the adjacent floating gate electrodes 15 increases, and the floating gate electrode 15 of the adjacent bit is increased.
, The Vt of the memory cell transistor fluctuates, and the bit information cannot be read normally. Therefore, it is necessary to secure a certain distance between adjacent floating gate electrodes 15 (that is, a distance between two channel regions 18) so that bit information can be read normally. This is the same as the distance between them (for example, about 0.1 μm or more).

Heretofore, the reason why the element isolation insulating film 6 is conventionally formed between all the memory cells is to increase the capacitance between the control gate electrode 13 and the floating gate electrode 15. That is, since both ends of the floating gate electrode 15 run on the element isolation insulating film 6, the area of the floating gate electrode 15 facing the control gate electrode 13 via the first interlayer insulating film 9 having the vertical contour is increased, The capacitance between the two increases. Thereby, the potential of the floating gate electrode 15 at the time of writing and reading can be increased.

Here, the advantage of increasing the capacitance between the control gate electrode 13 and the floating gate electrode 15 is that an operation margin at the time of writing that requires a higher potential of the floating gate electrode 15 can be secured. . On the other hand, what is currently a problem is a shortage of current between the source and drain at the time of reading in multi-value control, and an operation margin at the time of writing is secured. Therefore, the operation margin at the time of writing is reduced by eliminating the element isolation insulating film disposed between the erase gate electrodes 17 as in the present embodiment,
The amount of current between the source and the drain at the time of reading can be secured, and the advantage is large. Further, the area where the upper surface of the floating gate electrode 15 and the lower surface of the control gate electrode 13 face is larger in the structure of the present embodiment than in the conventional structure, and the capacitance between them does not decrease significantly.

Next, a method of manufacturing the semiconductor memory device according to the present embodiment will be described with reference to FIGS. First, as shown in FIGS. 2A to 2C, a resist mask pattern 2 for forming a diffusion layer serving as a bit line of a storage device is formed on one main surface of a P-type semiconductor substrate 1 by a photoresist technique. And arsenic ions are implanted at an acceleration voltage of 40 keV and a dose of 5 ×
Inject about 10 ¹⁵ / cm ² .

Next, as shown in FIGS. 3 (a) to 3 (c),
The resist mask pattern 2 for forming a diffusion layer is removed, and a heat treatment is performed, for example, at 950 ° C. for 30 minutes in a nitrogen atmosphere to a depth of 0.1 mm.
An N-type diffusion layer 3 of about 4 μm is formed, a first silicon oxide film 4 is deposited to a thickness of about 400 nm by a low pressure CVD method, and a resist mask pattern 5 for forming an element isolation insulating film is formed by a photoresist technique. Here, in the conventional manufacturing method, as shown in FIGS. 10A and 10B, a resist mask pattern 5 for forming an element isolation insulating film while leaving the first silicon oxide film 4 between all the memory cells. However, in the present embodiment, as shown in the pattern layout diagram of FIG. 1, an element isolation insulating film is formed for each memory cell except the first silicon oxide film 4 for every other memory cell. The resist mask pattern 5 is used.

Next, as shown in FIGS. 4 (a) to 4 (c),
A predetermined portion of the first silicon oxide film 4 is removed by etching using an anisotropic dry etching technique to form an element isolation insulating film 6, and then the resist mask pattern 5 is removed. Next, the surface on the semiconductor substrate 1 is oxidized by a thermal oxidation method to form a second silicon oxide film 7 of about 30 nm, and the first polycrystalline silicon is formed on the second silicon oxide film 7 by a low pressure CVD method. A film 8 is deposited to a thickness of about 300 nm. Next, a predetermined portion of the first polycrystalline silicon film 8 and a predetermined portion of the second silicon oxide film 7 under the first polycrystalline silicon film 8 are successively selectively removed by a photoetching technique. Thus, the vertical contour of the floating gate electrode 15 shown in FIG. 1 is formed.

Next, as shown in FIGS. 5 (a) to 5 (c),
A first interlayer insulating film 9 made of a silicon oxide film is deposited to a thickness of about 15 nm by a low-pressure CVD method, and is subjected to a heat treatment at 900 ° C. for densification. Next, a second polycrystalline silicon film 10 of about 300 nm and a second interlayer insulating film 11 of a silicon oxide film of about 300 nm are sequentially formed by a low pressure CVD method, and a resist mask pattern 12 for forming a control gate electrode is formed by photolithography. Is formed.

Next, as shown in FIGS. 6A to 6C,
The second interlayer insulating film 11 is etched using the resist mask pattern 12 as a mask, the resist mask pattern 12 for forming a control gate electrode is removed, and the second polycrystalline silicon film 10 is masked using the second interlayer insulating film 11 as a mask.
Is etched to form a control gate electrode 13. Next, a third interlayer insulating film made of a silicon oxide film is deposited on the entire surface by a low pressure CVD method to a thickness of about 200 nm, and the control gate electrode 13 and the second interlayer insulating film on the control gate electrode 13 are formed by anisotropic dry etching technique. A side wall insulating film 14 made of a third interlayer insulating film is formed on the side wall of the substrate 11.

Next, as shown in FIGS. 7A to 7C,
Using the second interlayer insulating film 11 and the side wall insulating film 14 as a mask, the first polycrystalline silicon film 8 is subjected to anisotropic dry etching under a condition of a high oxide film selectivity, and the floating gate electrode 15 shown in FIG. In the horizontal direction. Thus, the floating gate electrode of the adjacent memory cell is disconnected. Next, the exposed portion of the side wall of the floating gate electrode 15 obtained by the anisotropic dry etching is subjected to a thermal oxidation method, for example, thermal oxidation in a steam atmosphere at 900 ° C. to perform tunneling of a polycrystalline silicon oxide film of about 30 nm. An insulating film 16 is formed, and a third polycrystalline silicon film is deposited to a thickness of about 400 nm by a low pressure CVD method.
Thereafter, a predetermined portion is removed by etching using a photoetching technique, and an erase gate electrode 17 made of a third polycrystalline silicon film is formed so as to cover the tunneling insulating film 16.

The subsequent metal wiring step, protective film forming step and bonding pad forming step are omitted.

According to the above embodiment, the gate insulating film under the floating gate electrode 15 is formed on the surface of the semiconductor substrate 1 between the source region and the drain region, that is, between the adjacent N-type diffusion layers 3. The region where the second silicon oxide film 7 is formed, and the control gate electrode 1
3, that is, the region where the first interlayer insulating film 9 is formed, that is, the channel region of the memory cell transistor is 1 in FIG.
8 area. Here, the dimension W ₁ as shown in FIG. 1,
When W ₂ and L ₁ are defined, a comparison is made between FIG. 1 and FIG. 7, which are the layout diagram and the cross-sectional view of the present embodiment, and FIG. L
_Although it is ₁ in the related art, the element isolation insulating film 6 is present between all the memory cells, whereas in the present embodiment, only the element isolation insulating film 6 is provided every other between the memory cells. Therefore, W (FIG. 8) <W ₂ <W ₁ .

The memory cell transistor has a source / drain
Between the floating gate electrode 1 and the semiconductor substrate 1
5 facing area and control gate electrode 13 facing
Region and two transistors are connected in series
The structure is taken. W₁Is the floating gate electrode
15, the channel width of the transistor formed by _Two
Are formed by the control gate electrode 13.
The channel width of the transistor, W₁, W_TwoBoth memory
Cell current to form the channel of the
To secure, W₁, W_TwoBoth must be large
In each case, it is larger than the conventional channel width W.
Has become.

For this reason, according to the present embodiment, even when the pattern is miniaturized, a larger channel width than before can be secured, and the source-drain between the source and the drain of the memory cell transistor required for the multi-level control technique is obtained. The read current amount can be increased. As a result, each memory state can be easily distinguished from each other, and it is possible to prevent a reduction in an operation margin at the time of reading in a floating gate type semiconductor memory device having an erase gate electrode, which greatly contributes to miniaturization of the present semiconductor memory device. Can be.

[0039]

As is apparent from the above description,
According to the present invention, in a semiconductor memory device having a floating gate structure provided with an erase gate electrode, it is easy to secure a channel width of a memory cell transistor larger than before, Since the current amount between the source and the drain of the memory cell transistor required for the control technology can be easily secured, it can greatly contribute to miniaturization of a floating gate type semiconductor memory device having a large capacity erase gate electrode. .

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a step of the method for manufacturing the semiconductor memory device according to the embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a step of the method for manufacturing the semiconductor memory device according to the embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a step of the method for manufacturing the semiconductor memory device according to the embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing a step of the method for manufacturing the semiconductor memory device according to the embodiment of the present invention.

FIG. 6 is a schematic process sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment of the present invention.

FIG. 7 is a schematic process sectional view showing the method for manufacturing the semiconductor memory device according to the embodiment of the present invention.

FIG. 8 is a schematic plan view of a conventional semiconductor memory device.

FIG. 9 is a schematic process cross-sectional view showing a conventional method for manufacturing a semiconductor memory device.

FIG. 10 is a schematic process cross-sectional view showing a conventional method for manufacturing a semiconductor memory device.

FIG. 11 is a schematic cross-sectional view showing a step of the method for manufacturing a conventional semiconductor memory device.

FIG. 12 is a schematic process cross-sectional view showing a conventional method for manufacturing a semiconductor memory device.

FIG. 13 is a schematic cross-sectional view showing a step of a method for manufacturing a conventional semiconductor memory device.

FIG. 14 is a schematic process cross-sectional view showing a conventional method for manufacturing a semiconductor memory device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Diffusion layer formation resist mask pattern 3 Diffusion layer 4 First silicon oxide film 5 Element isolation insulation film formation resist mask pattern 6 Element isolation insulation film 7 Second silicon oxide film 8 First polycrystalline silicon Film 9 First interlayer insulating film 10 Second polycrystalline silicon film 11 Second interlayer insulating film 12 Resist mask pattern for forming control gate electrode 13 Control gate electrode 14 Side wall insulating film 15 Floating gate electrode 16 Tunneling insulating film 17 Erase gate electrode 18 Channel region

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) BA12 BB04 BB10 BD13 BD32 BD33 BE02 BE05 BE07 BF05 BH02 BH03 BH14 BH16

Claims (3)

[Claims] 1. A semiconductor memory device in which a plurality of memory cell transistors are arranged in a vertical direction and a horizontal direction on a semiconductor substrate of one conductivity type, wherein a source of the memory cell transistor is formed to be long in a vertical direction on a surface of the semiconductor substrate. A diffusion layer of another conductivity type serving as a region and a drain region, a plurality of diffusion layers being formed in the semiconductor substrate so as to be long in the horizontal direction and adjacent to each other in the vertical direction, and to sandwich the channel regions of the two memory cell transistors in the adjacent direction. A formed element isolation insulating film, and a floating gate electrode formed on the semiconductor substrate from above the element isolation insulating film via a gate insulating film in a predetermined region between the source region and the drain region. A control gate electrode formed above the floating gate electrode; and a control gate electrode formed on the element isolation insulating film; The semiconductor memory device characterized by providing an erasing gate electrode with contact via the side walls and the tunneling insulating film of the serial floating gate electrode in contact through the control gate electrode and the interlayer insulating film. 2. The semiconductor memory device according to claim 1, wherein the control gate electrode is a word line, and the diffusion layer is a bit line. 3. A method of manufacturing a semiconductor memory device in which a plurality of memory cell transistors are arranged in a vertical direction and a horizontal direction on a semiconductor substrate of one conductivity type, wherein the memory cell is provided to be long in a vertical direction on a surface of the semiconductor substrate. Forming a diffusion layer of another conductivity type that becomes a source region and a drain region of the transistor; and a plurality of memory cell transistors that are provided in the semiconductor substrate so as to be long in the horizontal direction and adjacent in the vertical direction and are adjacent to each other. Forming an element isolation insulating film provided so as to sandwich the channel region; and, in a predetermined region between the source region and the drain region, a first insulating film on the element isolation insulating film and Forming a film for a floating gate electrode on the surface of the semiconductor substrate; and forming a film for the floating gate electrode via a second insulating film. Forming a control gate electrode; separating the floating gate electrode film into individual floating gate electrodes; providing a sidewall of the floating gate electrode and a tunneling insulating film provided on the element isolation insulating film. Forming an erase gate electrode in contact with the control gate electrode and the control gate electrode through an interlayer insulating film.