JPH07101714B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, 1 bit is 1 bit.
The present invention relates to improvement of an electrically rewritable read-only memory EEPROM composed of individual transistors.

[Conventional technology]

In the conventional EEPROM, the basic cell is composed of two transistors as disclosed in Japanese Patent Publication No. 62-41431, for example, but there is a drawback that the chip area increases as the degree of integration increases. In order to improve this point, EEPROM that can be erased electrically in one transistor structure, that is, flash EE
A PROM has been proposed.

Fig. 3 shows, for example, IEEE Journal of Solid-State Circuits, SC-22, Volume 5, 1987, 676-6.
Page 83 (J. Solid-State Circuits, vol.SC-22, No. 5,198
7 is a plan view and a cross-sectional view showing a conventional one-transistor type flash EEPROM shown in pp.676-683). In this figure, 31 is a semiconductor substrate, 32 is a floating gate, 33 is a control gate (word line), 34 is a source diffusion region, 35 is a drain diffusion region, 36 is an aluminum wiring (bit line), 37 is an aluminum wiring 36. Contact hole for connection to drain 35, 38
Is an interlayer insulating film, 39 is a field oxide film (isolation region), 40
Is a channel stopper under the field oxide film 39, 41 is a gate oxide film between the floating gate 32 and the substrate 31, and 42 is a control gate 33.
A gate oxide film between the substrate 31 and the substrate 31, 43 is an interlayer insulating film between the control gate 33 and the floating gate 32. 3 (a) is a plan view, FIG. 3 (b) is a sectional view taken along the line AA of (a), and FIG. 3 (c) is a sectional view taken along the line BB of (a). It is a figure.

As shown in this figure, in the conventional flash EEPROM, the drain side end of the floating gate 32 has a stacked structure in which it is self-aligned with the control gate 33, and the other end of the floating gate 32 is at the control gate 33. Was covered with. Therefore, as shown in (b), the channel portion of the memory transistor has a structure in which the floating gate 32 and the control gate 33 are connected in series.

[Problems to be Solved by the Invention]

Since the conventional flash EEPROM is configured as described above, it has the following problems.

When the mask alignment between the control gate and the floating gate is deviated, the channel length of the floating gate and the area of the laminated portion of the control gate and the floating gate change, and are not constant. Therefore, the coupling capacitance of the memory cell is not constant, and the writing depth of the memory cell and the reading current vary. Further, since the channel length of the memory transistor is long, the cell area is relatively large, the channel resistance is high, and the cell current is small.

The present invention has been made to solve the above problems, and a semiconductor memory device having a small cell area, a self-aligned channel length determination, and a constant capacitive coupling ratio between a control gate and a floating gate. Aim to get.

[Means for Solving the Problems]

A semiconductor memory device according to the present invention includes a semiconductor substrate having a first conductivity type, a field oxide film for element isolation for partitioning an element formation region on a main surface of the semiconductor substrate, and a main surface of the semiconductor substrate. A first conductive layer as a floating gate electrode formed on the first conductive film via a first insulating film, and a control gate electrode formed on a side wall portion and an upper portion of the first conductive layer via a second insulating film. And a third conductive layer as a source and a drain having the second conductivity type formed on the main surface of the semiconductor substrate, and formed on the sidewall portion of the first conductive layer. The formed second conductive layer is electrically connected to the second conductive layer formed on the first conductive layer, and the first conductive layer existing in the element forming region is formed.
There is a space between the second conductive layer formed on the sidewall of the conductive layer and the second conductive layer formed on the first conductive layer existing in the element formation region. However, the second conductive layer formed on the sidewall portion of the first conductive layer existing in the element forming region does not extend above the first conductive layer existing in the element forming region. It is configured in.

[Action]

In the present invention, when the control gate is formed after the floating gate is formed, the control gate on the sidewall portion of the floating gate is formed in a self-aligned manner, so that the control gate is formed only on the sidewall portion on the source side with the substrate. Since the channel is formed, the channel length of the memory transistor is substantially determined by the floating gate length, which reduces the cell area. Further, most of the capacitive coupling ratio between the floating gate and the control gate is determined by the laminated portion between the control gate and the floating gate on the floating gate, and therefore the variation of the capacitive coupling ratio due to misalignment during pattern formation hardly occurs.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 (a) is a plan view showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 1 (b) is an AA line in FIG. 1 (a).
FIG. 1 (c) is a sectional view taken along line BB in FIG. 1 (a). In FIG. 1, 1 is a semiconductor substrate,
2 is a floating gate, 3 is a control gate (word line), 4 is a source region of the memory transistor, 5 is a drain region of the memory transistor, 6 is an aluminum wiring (bit line), 7 is a connection between the aluminum wiring 6 and the drain 5. Contact hole,
8 is an interlayer insulating film, 9 is a field oxide film (separation region),
10 is a channel stopper under the field oxide film 9, 11 is a gate oxide film between the floating gate 2 and the substrate 1, 12 is a gate oxide film between the control gate 3 and the substrate 1, 13 is between the control gate 3 and the floating gate 2. It is an interlayer insulating film.

This semiconductor memory device includes a floating gate transistor and a control gate transistor formed on the main surface of semiconductor substrate 1. Floating gate of floating gate transistor 2
Partially overlap with the drain 5 formed on the main surface of the semiconductor substrate 1 with the insulating film 11 interposed therebetween. The control gate transistor includes control gate 3 and insulating film 12 on the main surface of semiconductor substrate 1. The control gate 3 is stacked on the floating gate 2 with an interlayer insulating film 13 interposed therebetween. Further, the control gate 3 is arranged on the side wall portion of the floating gate 2 on the source side via an insulating film. Control gate 3 disposed on the side wall of floating gate 2
And the control gate 3 stacked on top of the floating gate 2,
As shown in FIG. 1 (a), they are connected at at least one place in the same word line. The floating gate transistor and the control gate transistor are arranged in series with the source 4 and the drain 5, and the floating gate 2 is located on the drain side and the control gate 3 is located on the source side. The gate insulating film 12 of the control gate transistor and the gate insulating film 11 of the floating gate transistor may have the same film thickness or different film thicknesses. The source 4 and the drain 5 have a conductivity type opposite to that of the semiconductor substrate 1, and are formed in self alignment with the control gate 3 and the floating gate 2.

Further, FIG. 2A is a 1-bit equivalent circuit diagram of the semiconductor memory device according to this embodiment, and FIG. 2B is an equivalent circuit diagram when 4 bits are arranged in an array.

Next, the operation will be described with reference to FIGS. 1 (a) to 1 (c) and FIGS. 2 (a) and 2 (b). When electrons are injected into the floating gate 2, the write voltage V _CP is applied to the control gate 3 and V _DP is applied to the drain 5, so that the source 4 and the substrate 1 are kept at the ground potential. At this time, the potential of the floating gate 2 becomes V _FP due to capacitive coupling between the control gate 3 and the floating gate 2. As a result, the control gate transistor and the floating gate transistor are turned on. And
In the vicinity of the drain end, a part of so-called channel hot electrons crosses the potential barrier of the gate insulating film 11 and rushes into the floating gate 2 and is held there. This operation is the same as the normal EPROM write operation.

When the electrons are extracted from the floating gate 2, the control gate 3 and the substrate 1 are at the ground potential, and the source 4 is in the floating state. At this time, the erase potential V _DE is applied to the drain 5,
Gate insulating film in the overlapping part of drain 5 and floating gate 26
Floating gate 2 by Fowler-Nordheim Tunneling through 11
The electrons inside are drained to the drain 5.

At the time of reading, the control gate 3 is set to the read potential V _CR and the control gate transistor is turned on. At this time, the source 4 is set to the ground potential and the voltage V _DR is applied to the drain 5. In this state, ON / OFF of the entire memory transistor is determined by whether the floating gate transistor is ON or OFF, and the binary state of the floating gate 2 is determined. In addition,
At the time of writing and reading, a predetermined voltage is applied only to the selected bit line and word line. At the time of erasing, that is, when electrons are extracted from the floating gate 2 to the drain 5,
The erase voltage V _DR is applied to all the bit lines, and all the source lines are brought into a floating state. As a result, erasing is performed on all bits at once. Further, the voltages V _CP , V _DP , V _CR , and V _DR may be the same or different.

The manufacturing process of the flash EEPROM according to this embodiment will be described with reference to FIGS. 4 (a) to 4 (f). First, the substrate 1 is prepared, and the element isolation field oxide film 9 and the channel stopper 10 are formed thereon (FIG. 4A). Next, the gate insulating film 11 is formed, and the first conductive layer 2 is formed on the gate insulating layer 11. This first conductive layer 2 is n-type doped. An insulating layer 13 having a two-layer structure of, for example, a silicon oxide film and a silicon nitride film is formed on the first conductive layer 2, and the pattern of the floating gate 2 is formed by etching (FIG. 4 (b)). After the first gate insulating film 11 in the region where the floating gate 2 does not exist is removed by etching, the second gate insulating film 12 is formed by thermal oxidation. At this time, the insulating film 13 on the floating gate 2
Since the surface is a silicon nitride film, it is hardly oxidized, but a relatively thick silicon oxide film is formed on the sidewall portion of the floating gate 2 where the insulating film 13 does not exist. Next, the second conductive layer 3 is deposited (FIG. 4 (c)). After this, the pattern of the n-type doped second conductive layer 3 is formed by photolithography and etching techniques. By using anisotropic etching for the etching at this time, the second conductive layer 3a is left on the side wall of the floating gate 2 as a so-called side wall by self-alignment (FIG. 4 (d)). Next, while leaving the photoresist 20 on the second conductive layer 3, a new photoresist is applied to cover the second conductive layer 3a on the side wall portion corresponding to the source side and the side wall portion corresponding to the drain side. After forming a photoresist pattern that does not cover the second conductive layer 3b, the second conductive layer 3b is removed by etching, and then all the photoresist is removed (fourth).
Figure (e)). Thereafter, a source region 4 and a drain region 5 having a conductivity type opposite to that of the substrate 1 are formed and an interlayer insulating film 8 is deposited according to a normal process flow. Further, contact holes 7 and aluminum wirings 6 are formed (FIG. 4 (f)), and finally a surface protective film is formed to complete the flash EEPROM according to this embodiment.

In such a flash EEPROM, the channel length of the control gate transistor is determined in a self-aligned manner, and the channel length of the memory transistor is substantially determined by the floating gate length. Therefore, the cell area is smaller than that of the conventional flash EEPROM. Become. Moreover, since the area of the laminated portion of the control gate and the floating gate is constant, the capacitive coupling ratio between the control gate and the floating gate is constant.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, a semiconductor substrate having the first conductivity type, an element isolation field oxide film for partitioning an element formation region on the main surface of the semiconductor substrate, A first floating gate electrode formed on the main surface of the semiconductor substrate via a first insulating film.
Second conductive layer and a second conductive layer on the sidewall and upper portion of the first conductive layer.
A second conductive layer as a control gate electrode formed via the insulating film and a third conductive layer as a source and drain having a second conductivity type formed on the main surface of the semiconductor substrate. The second conductive layer formed on the side wall of the first conductive layer is electrically connected to the second conductive layer formed on the first conductive layer, and the element forming region is formed. Of the second conductive layer formed on the side wall portion of the first conductive layer existing in the above and the second conductive layer formed above the first conductive layer existing in the element forming region. There is a space therebetween, and the second conductive layer formed on the side wall of the first conductive layer existing in the element forming region is an upper portion of the first conductive layer existing in the element forming region. Since it is configured so that it does not extend to the The second conductive layer to be formed on the side wall of the conductive layer can be formed in a self-aligned manner, the channel length is determined in a self-aligned manner, and the coupling capacitance due to misalignment during pattern formation can be almost eliminated. Therefore, the capacitance coupling ratio between the control gate and the floating gate can be made constant, and the semiconductor memory device suitable for high integration can be obtained without increasing the cell area.

[Brief description of drawings]

FIG. 1 is a diagram showing a flash EEPROM according to an embodiment of the present invention, FIG. 2 is a diagram showing its equivalent circuit, FIG. 3 is a diagram showing a conventional flash EEPROM, and FIG. 4 is a flash EEPROM of FIG. FIG. 6 is a diagram for explaining the manufacturing process of FIG. In the figure, 1 is a semiconductor substrate, 2 is a floating gate, 3 is a control gate, 4 is a source region, 5 is a drain region, 6 is aluminum wiring, 7 is a contact hole, 8 is an interlayer insulating film, 9
Is a field oxide film, 10 is a channel stopper, 11 is a floating gate insulating film, 12 is a control gate insulating film, and 13 is an interlayer insulating film between the floating gate and the control gate. In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 27/115 29/788 29/792 G11C 17/00 307 D (72) Inventor Watari Takenobu Noboru Mizuhohara 4-chome, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation LSI Research Institute (56) Reference JP-A 64-7569 (JP, A) JP-A 58-115865 (JP, A) JP-A 62-291180 (JP, A)

Claims (1)

[Claims] 1. A semiconductor substrate having a first conductivity type, a field oxide film for element isolation for partitioning an element formation region on a main surface of the semiconductor substrate, and a first surface on the main surface of the semiconductor substrate. A first conductive layer as a floating gate electrode formed via an insulating film, and a second conductive layer as a control gate electrode formed on a sidewall and an upper portion of the first conductive layer via a second insulating film. And a third conductive layer as a source and a drain having the second conductivity type formed on the main surface of the semiconductor substrate, and a second conductive layer formed on the sidewall of the first conductive layer. Is electrically connected to the second conductive layer formed on the first conductive layer, and is formed on the sidewall portion of the first conductive layer existing in the element formation region. The first conductive layer and the first conductive layer existing in the element forming region The second conductive layer formed on the sidewall of the first conductive layer existing in the element forming region has a gap between the second conductive layer formed on the upper part of the conductive layer and the second conductive layer. Is not extended above the first conductive layer existing in the element formation region, the semiconductor memory device.