JP2001129800A - Substrate with field-through and manufacturing method therefor - Google Patents
Substrate with field-through and manufacturing method thereforInfo
- Publication number
- JP2001129800A JP2001129800A JP31366699A JP31366699A JP2001129800A JP 2001129800 A JP2001129800 A JP 2001129800A JP 31366699 A JP31366699 A JP 31366699A JP 31366699 A JP31366699 A JP 31366699A JP 2001129800 A JP2001129800 A JP 2001129800A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- wiring
- feed
- groove
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この出願の発明は、フィード
スルー付き基板とその製造方法に関するものである。さ
らに詳しくは、マイクロマシンセンサーやアクチュエー
タ等を搭載したマイクロチップの製造において、マイク
ロデバイスをパッケージする工程を単純化することによ
り、製造の歩留まりを改善し、さらに、パッケージ工程
の加工精度や信頼性を向上するのに有用なフィードスル
ー付き基板とその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate with a feedthrough and a method for manufacturing the same. More specifically, in the manufacture of microchips equipped with micromachine sensors and actuators, the process of packaging microdevices has been simplified to improve the manufacturing yield and improve the processing accuracy and reliability of the packaging process. And a method of manufacturing the same.
【０００２】[0002]
【従来の技術とその課題】工業用製品の小型化と信号の
高速化，高機能化に伴い、多種複数のチップ状マイクロ
デバイスを１つのモジュール内に組み込むマルチチップ
モジュール技術が実用化され、多くのマイクロマシンセ
ンサーやアクチュエータの開発が盛んに行われるように
なってきている。2. Description of the Related Art With the miniaturization of industrial products, the increase in signal speed, and the sophistication of industrial products, multichip module technology for incorporating a plurality of types of chip-like microdevices into one module has been put into practical use. Micromachine sensors and actuators have been actively developed.
【０００３】従来、マイクロデバイスのパッケージにお
いては、貫通孔が穿孔されたガラス製の基板が用いられ
ている。この基板上に電極や配線を形成する際には、フ
ォトリソグラフィによるレジストの形成がなされるが、
貫通孔の位置に細心の注意が払われなければならなかっ
た。Conventionally, in a package of a micro device, a glass substrate having a through hole is used. When forming electrodes and wiring on this substrate, a resist is formed by photolithography.
Great care had to be taken in the location of the through holes.
【０００４】また、マイクロデバイスのパッケージは、
上記の貫通孔が穿孔された基板をマイクロデバイスの上
部に、電極や配線が組み込まれた基板をマイクロデバイ
スの下部に、それぞれ対向せしめ、それら２枚の基板で
マイクロデバイスを挟みこむことによりなされる。挟み
こまれるマイクロデバイスのＳｉは、上部の基板の貫通
孔を通じての外部配線との接合、および、下部の基板の
配線との接触により、電気的な導通を得ている。この接
合工程においては、基板と接合するＳｉと接合しないＳ
ｉを、それぞれ正しく形成するために、接合しないＳｉ
に相対する部分のガラス基板上には電極を配置し、これ
を基板の反対側から引き出して、接合しないＳｉと基板
とを同電位にしてシールドしていた。このとき、基板上
の電極からガラス基板の反対側への導通は必須のもので
あり、この導通が不充分である場合には接合プロセスは
失敗する。[0004] The package of the micro device is as follows.
The above-described substrate having the through-holes formed thereon is made to face the upper part of the microdevice, and the substrate having the electrodes and wirings is made to face the lower part of the microdevice, and the microdevice is sandwiched between the two substrates. . The Si of the sandwiched microdevice obtains electrical continuity by bonding with external wiring through the through hole of the upper substrate and by contact with the wiring of the lower substrate. In this bonding step, S which is not bonded to Si which is bonded to the substrate
In order to form i correctly,
An electrode was arranged on a portion of the glass substrate opposite to the above, and this was pulled out from the opposite side of the substrate, and the unbonded Si and the substrate were shielded with the same potential. At this time, conduction from the electrode on the substrate to the opposite side of the glass substrate is essential, and if the conduction is insufficient, the bonding process fails.
【０００５】このように、従来のマイクロデバイスのパ
ッケージは、複雑な工程を経てなされるものであり、工
程の簡略化による歩留まりの改善が望まれていた。ま
た、従来の穿孔されたガラス製の基板を用いた方法にお
いては、貫通孔のピッチをこれ以上狭くすることが難し
く、製品の小型化の妨げとなっていた。As described above, the package of the conventional micro device is manufactured through a complicated process, and it is desired to improve the yield by simplifying the process. Further, in the conventional method using a perforated glass substrate, it is difficult to further narrow the pitch of the through holes, which hinders miniaturization of the product.
【０００６】この出願の発明は、以上の通りの事情に鑑
みてなされたものであり、マイクロマシンセンサーやア
クチュエータ等を搭載したマイクロパッケージ製品の製
造において、マイクロデバイスのパッケージ工程の単純
化を実現し、さらには、マイクロパッケージ製品の小型
化にも貢献する新しい基板材料を提供することを課題と
している。The invention of this application has been made in view of the above-mentioned circumstances, and realizes simplification of a microdevice packaging process in manufacturing a micropackage product equipped with a micromachine sensor, an actuator, and the like. Another object is to provide a new substrate material that contributes to miniaturization of micro package products.
【０００７】[0007]
【課題を解決するための手段】この出願の発明は、上記
の課題を解決するものとして、マイクロデバイスのパッ
ケージに用いられる基板であって、基板内部に基板表面
から基板裏面を貫通する配線を具備し、この配線により
基板表面と基板裏面の間に電気的導通を有することを特
徴とするフィードスルー付き基板を提供する（請求項
１）。The present invention solves the above-mentioned problems by providing a substrate used for a package of a microdevice, wherein the substrate has a wiring penetrating from the front surface of the substrate to the back surface of the substrate. Further, there is provided a substrate with a feed-through, wherein the wiring has electrical continuity between the front surface and the back surface of the substrate (claim 1).
【０００８】また、この出願の発明であるフィードスル
ー付き基板の製造方法であって、配線材料に配線パター
ンマスクを形成し、配線材料をエッチングすることによ
り溝を形成し、次いで、この溝に基板材料を充填し、さ
らに、研磨により成形することを特徴とするフィードス
ルー付き基板の製造方法を提供する（請求項２）。The method of manufacturing a substrate with a feed-through according to the invention of the present application includes forming a wiring pattern mask in a wiring material, etching the wiring material to form a groove, and then forming the substrate in the groove. A method for manufacturing a substrate with a feed-through, characterized in that a material is filled and further formed by polishing (claim 2).
【０００９】この出願の発明であるフィードスルー付き
基板は、基板の材料がパイレックスガラス、または、Ｓ
ｉ−Ｂ−Ｏガラスであること（請求項３）、配線の材料
が、金属またはＳｉであること（請求項４）を特徴とす
る。The substrate with a feed-through according to the invention of this application is made of Pyrex glass or S
It is characterized by being i-BO glass (Claim 3) and the material of the wiring is metal or Si (Claim 4).
【００１０】さらに、この出願の発明であるフィードス
ルー付き基板の製造方法であって、配線材料に配線パタ
ーンマスクを形成し、配線材料をエッチングすることに
より溝を形成し、次いで、この溝にパイレックスガラス
を溶融することにより充填し、さらに、研磨により成形
することを特徴とするフィードスルー付き基板の製造方
法（請求項５）、および、この出願の発明であるフィー
ドスルー付き基板の製造方法であって、フィードスルー
付き基板の製造方法であって、配線材料に配線パターン
マスクを形成し、配線材料をエッチングすることにより
溝を形成し、次いで、この溝にＳｉ−Ｂ−Ｏガラスのス
ートを堆積し、約１１００℃でアニールすることにより
充填し、さらに、研磨により成形することを特徴とする
フィードスルー付き基板の製造方法（請求項６）も提供
する。Further, in the method of manufacturing a substrate with a feed-through according to the invention of the present application, a wiring pattern mask is formed in a wiring material, a groove is formed by etching the wiring material, and then a Pyrex is formed in the groove. A method for producing a substrate with a feed-through, characterized in that glass is filled by melting and then formed by polishing, and a method for producing a substrate with a feed-through according to the invention of the present application. A method of manufacturing a substrate with a feed-through, wherein a wiring pattern mask is formed in a wiring material, a groove is formed by etching the wiring material, and then a soot of Si-BO glass is deposited in the groove. With a feed-through characterized by being filled by annealing at about 1100 ° C. and then molded by polishing Method of manufacturing a substrate (claim 6) are also provided.
【００１１】そして、この出願の発明は、フィードスル
ー付き基板の製造方法であって、基板材料をエッチング
することで溝を形成し、この溝に配線材料を充填し、さ
らに研磨により成形することを特徴とする基板の製造方
法（請求項７）を提供し、エッチングをＲＩＥ法（Ｒｅ
ａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）により行い、
配線材料の充填をメッキ法により行うことを特徴とする
基板の製造方法（請求項８）、対向する前記のフィード
スルー付き基板の間に、マイクロデバイスを挟みこみパ
ッケージすることにより製造されることを特徴とするマ
イクロマシンセンサーおよびアクチュエータ（請求項
７）も提供する。The invention of this application is a method of manufacturing a substrate with a feed-through, comprising forming a groove by etching a substrate material, filling the groove with a wiring material, and forming the groove by polishing. A method of manufacturing a substrate characterized by the above features (claim 7) is provided.
active Ion Etching)
A method of manufacturing a substrate, wherein the wiring material is filled by a plating method (Claim 8), wherein the microdevice is sandwiched and packaged between the opposing substrates with a feedthrough. Micromachine sensors and actuators (claim 7) are also provided.
【００１２】[0012]
【発明の実施の形態】この出願の発明は上記のとおりの
特徴をもつものであるが、以下にその実施の形態につい
て説明する。BEST MODE FOR CARRYING OUT THE INVENTION The invention of this application has the features as described above, and embodiments thereof will be described below.
【００１３】この出願の発明のフィードスルー付き基板
は、マイクロマシンセンサーやアクチュエータ等のマイ
クロデバイスをパッケージするのに用いられる。このフ
ィードスルー付き基板は、図１に示すように、基板表面
から基板裏面を貫通する形で配線（１）が基板（２）内
部に組み込まれており、この配線により、基板表面と基
板裏面の間には電気的導通を有する。The substrate with a feed-through according to the invention of this application is used for packaging a micro device such as a micro machine sensor or an actuator. As shown in FIG. 1, in the substrate with a feed-through, wiring (1) is incorporated in the substrate (2) so as to penetrate from the substrate surface to the substrate rear surface. There is electrical continuity between them.
【００１４】この出願の発明であるフィードスルー付き
基板の製造方法としては、まず、配線材料上に対して配
線パターンのマスキングが施され、この配線材料上のマ
スクに対してエッチングが行われる事により凹凸状の溝
が形成される。次いで、この溝に対して基板材料の充填
がなされ、さらに、基板の両面を研磨することにより成
形がなされる。In the method of manufacturing a substrate with a feed-through according to the invention of this application, first, a wiring pattern is masked on a wiring material, and a mask on the wiring material is etched. An uneven groove is formed. Next, the groove is filled with a substrate material, and further, the both surfaces of the substrate are polished to form the groove.
【００１５】前記の配線材料上に対する配線パターンの
マスキングは、感光樹脂膜や金属によるメッキによって
なされる。また、前記のエッチングとしては、リアクテ
ィブイオンエッチング等の異方性エッチングが実施され
る。The masking of the wiring pattern on the wiring material is performed by plating with a photosensitive resin film or metal. Further, as the etching, anisotropic etching such as reactive ion etching is performed.
【００１６】この出願の発明のフィードスルー付き基板
においては、基板部分の材料として、パイレックスガラ
ス、Ｓｉ−Ｂ−Ｏガラスなどのガラス材料が用いられ
る。また、この基板の材料として、エポキシ樹脂などの
各種の樹脂材料が用いられてもよい。In the substrate with feedthrough of the invention of this application, a glass material such as Pyrex glass or Si-BO glass is used as a material of the substrate portion. Also, various resin materials such as epoxy resin may be used as the material of the substrate.
【００１７】また、基板内部に表裏面を貫通する形で埋
設される配線の材料としては、たとえば、金属材料また
はＳｉなどが用いられる。基板部分の材料としてパイレ
ックスガラスが用いられる場合には、基板上の溝に対す
るパイレックスガラスの溶融により充填がなされる。ま
た、基板部分の材料としてＳｉ−Ｂ−Ｏガラスが用いら
れる場合には、基板上の溝にＳｉ−Ｂ−Ｏガラスのスー
トを堆積し、約１１００℃でアニールすることにより充
填がなされる。Further, as a material of the wiring buried inside the substrate so as to penetrate the front and back surfaces, for example, a metal material or Si is used. When Pyrex glass is used as the material of the substrate portion, filling is performed by melting the Pyrex glass into the grooves on the substrate. When Si-BO glass is used as the material of the substrate portion, the soot is deposited by depositing soot of Si-BO glass in grooves on the substrate and annealing at about 1100 ° C.
【００１８】[0018]
【実施例】基板部分の材料にパイレックスガラス、ま
た、配線部分の材料にＳｉを用いた場合におけるフィー
ドスルー付き基板の製造方法を、図２を用いて説明す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a substrate with a feed-through when Pyrex glass is used as a material of a substrate portion and Si is used as a material of a wiring portion will be described with reference to FIG.
【００１９】厚さ１ｍｍ程度のＳｉウェハー（２１）
（図２（Ａ））に対して、所望の配線パターンをマスク
するために、Ｓｉウェハー表面に対してＮｉメッキ（２
２）が施される（図２（Ｂ））。そして、リアクティブ
イオンエッチングによりＳｉウェハーに溝（２３）が形
成され、その後、Ｎｉの除去がなされる（図２
（Ｃ））。この溝に対して、融解したパイレックガラス
（２４）を充填し（図２（Ｄ））、生成物の両面を研磨
することにより、この出願の発明であるフィードスルー
付き基板は完成する（図２（Ｅ））。Si wafer of about 1 mm thickness (21)
(FIG. 2A), to mask a desired wiring pattern, Ni plating (2
2) is performed (FIG. 2B). Then, a groove (23) is formed in the Si wafer by reactive ion etching, and then Ni is removed (FIG. 2).
(C)). The groove is filled with molten Pyrek glass (24) (FIG. 2 (D)), and both surfaces of the product are polished to complete the substrate with a feedthrough according to the invention of the present application (FIG. 2). 2 (E)).
【００２０】この出願の発明のフィードスルー付き基板
は、基板表面に電極や配線を設置することも可能であ
る。この出願の発明のフィードスルー付き基板は、平坦
な表面を持つものであるから、基板に貫通孔を穿孔する
従来方法と比較し、基板表面に電極や配線を設置する際
のフォトリソグラフィーやエッチングなどの基板表面処
理が容易であるという特長を持つ。The substrate with a feed-through according to the invention of this application can be provided with electrodes and wiring on the surface of the substrate. Since the substrate with a feed-through of the invention of this application has a flat surface, compared with the conventional method of forming a through hole in the substrate, photolithography and etching when installing electrodes and wiring on the substrate surface are performed. Has the feature that the substrate surface treatment is easy.
【００２１】さらに、この出願の発明においては、図３
に例示するように、対向するフィードスルー付き基板
（３１）の間に機能性マイクロデバイス（３２）を挟み
こむことによりパッケージを施し、マイクロマシンセン
サーやアクチュエータなどの機能を有するマイクロパッ
ケージが製造される。この出願の発明のマイクロパッケ
ージは、材料である基板が穴を持たないことから、その
製造工程において封止もれといったの不良が発生しにく
く、また、機能性マイクロデバイス（３２）を構成する
Ｓｉ部と基板の配線部（３３）との接合の不良も生じに
くい。また、フィードスルー付き基板（３１）を部品と
してセンサやマイクロアクチュエータを構成する場合
に、フィードスルー付き基板（３１）と接合しないＳｉ
（３４）と基板とを同電位にするための電極（３５）に
配線部（３３）を接触させ、電極（３５）から基板外部
への電気的導通を得ることができるため、シールドを確
実かつ容易に施すことも可能となる。Furthermore, in the invention of this application, FIG.
As shown in FIG. 1, a package is formed by sandwiching a functional microdevice (32) between opposed substrates (31) with feedthroughs, and a micropackage having functions such as a micromachine sensor and an actuator is manufactured. In the micropackage of the invention of this application, since the substrate, which is a material, does not have holes, defects such as leakage of sealing hardly occur in the manufacturing process, and the Si constituting the functional microdevice (32) is formed. The bonding failure between the portion and the wiring portion (33) of the substrate hardly occurs. When a sensor or a microactuator is configured by using the substrate with a feed-through (31) as a component, Si that is not bonded to the substrate with a feed-through (31) is used.
The wiring portion (33) is brought into contact with the electrode (35) for making the potential of the (34) and the substrate the same, and electrical conduction from the electrode (35) to the outside of the substrate can be obtained. It can also be easily applied.
【００２２】この出願の発明のフィードスルー付き基板
は、前記の通り、配線を基板内部に具備するものである
から、パッケージされるマイクロデバイスとの電気的導
通に係る基板上の面積を、従来法と比較して少なくする
事が可能であり、その結果として、パッケージ製品の小
型化が実現される。狭ピッチで、高精度に位置決めされ
た、フィードスルーを実現できることになる。またこれ
により、センサやアクチュエータの、外部端子取り出し
に係る部分の面積を小型化できることから、センサやア
クチュエータのトータルの大きさを小型化できる。As described above, the substrate with a feed-through according to the invention of this application is provided with the wiring inside the substrate, so that the area on the substrate relating to the electrical continuity with the microdevice to be packaged can be reduced by the conventional method. It is possible to reduce the size of the package product as a result. It is possible to realize a feed-through that is positioned at a narrow pitch and with high precision. In addition, since the area of the portion related to the external terminal extraction of the sensor or the actuator can be reduced, the total size of the sensor or the actuator can be reduced.
【００２３】プロセスが簡易化されるとともに、歩留り
が大幅に向上する。The process is simplified and the yield is greatly improved.
【００２４】[0024]
【発明の効果】この出願の発明によって、マイクロデバ
イスのパッケージ製品の製造工程において、パッケージ
の単純化が実現され、製品の歩留まりが改善される。ま
た、この出願の発明は、製造されるマイクロデバイスの
パッケージ製品の信頼性向上や小型化にも貢献するもの
であり、その実用化が期待される。According to the invention of this application, simplification of the package is realized in the manufacturing process of the package product of the microdevice, and the yield of the product is improved. Further, the invention of this application contributes to improvement of the reliability and miniaturization of a package product of a manufactured micro device, and its commercialization is expected.
【図１】この出願の発明であるフィードスルー付き基板
を示す概略図である。FIG. 1 is a schematic view showing a substrate with a feed-through according to the invention of this application.
【図２】この出願の発明であるフィードスルー付き基板
の製造方法を示す概略図である。FIG. 2 is a schematic view illustrating a method of manufacturing a substrate with a feed-through according to the invention of the present application.
【図３】この出願の発明であるフィードスルー付き基板
を用いたマイクロデバイスのパッケージの例を示す概略
図である。FIG. 3 is a schematic diagram showing an example of a package of a micro device using a substrate with a feed-through according to the invention of this application.
１ 配線 ２ 基板 ２１ Ｓｉウェハー ２２ Ｎｉメッキ ２３ 溝 ２４ パイレックガラス ３１ フィードスルー付き基板 ３２ 機能性マイクロデバイス ３３ 配線部 ３４ 基板と接合しないＳｉ ３５ 電極 DESCRIPTION OF SYMBOLS 1 Wiring 2 Substrate 21 Si wafer 22 Ni plating 23 Groove 24 Pyrex glass 31 Substrate with feedthrough 32 Functional microdevice 33 Wiring part 34 Si 35 electrode not joined to substrate
Claims (9)
れる基板であって、基板内部に基板表面から基板裏面を
貫通する配線を具備し、この配線により基板表面と基板
裏面の間に電気的導通を有することを特徴とするフィー
ドスルー付き基板。1. A substrate used for a package of a micro device, comprising a wiring inside the substrate, the wiring penetrating from the surface of the substrate to the back surface of the substrate, and having electrical connection between the surface of the substrate and the back surface of the substrate by the wiring. A substrate with a feedthrough.
の製造方法であって、配線材料に配線パターンマスクを
形成し、配線材料をエッチングすることにより溝を形成
し、次いで、この溝に基板材料を充填し、さらに、研磨
により成形することを特徴とするフィードスルー付き基
板の製造方法。2. The method according to claim 1, wherein a wiring pattern mask is formed in the wiring material, a groove is formed by etching the wiring material, and then the substrate material is formed in the groove. A method for producing a substrate with a feed-through, characterized in that the substrate is filled and further molded by polishing.
は、Ｓｉ−Ｂ−Ｏガラスであることを特徴とする請求項
１記載のフィードスルー付き基板。3. The substrate with a feed-through according to claim 1, wherein the material of the substrate is Pyrex glass or Si—BO glass.
とを特徴とする請求項１記載のフィードスルー付き基
板。4. The substrate with a feed-through according to claim 1, wherein the material of the wiring is metal or Si.
の製造方法であって、配線材料に配線パターンマスクを
形成し、配線材料をエッチングすることにより溝を形成
し、次いで、この溝にパイレックスガラスを溶融するこ
とにより充填し、さらに、研磨により成形することを特
徴とするフィードスルー付き基板の製造方法。5. The method according to claim 1, wherein a wiring pattern mask is formed in the wiring material, a groove is formed by etching the wiring material, and then Pyrex glass is formed in the groove. A method for producing a substrate with a feed-through, characterized in that the substrate is filled by melting and then molded by polishing.
の製造方法であって、配線材料に配線パターンマスクを
形成し、配線材料をエッチングすることにより溝を形成
し、次いで、この溝にＳｉ−Ｂ−Ｏガラスのスートを堆
積し、約１１００℃でアニールすることにより充填し、
さらに、研磨により成形することを特徴とするフィード
スルー付き基板の製造方法。6. The method for manufacturing a substrate with a feed-through according to claim 1, wherein a wiring pattern mask is formed in the wiring material, a groove is formed by etching the wiring material, and then a Si-layer is formed in the groove. Depositing a soot of BO glass and filling by annealing at about 1100 ° C.
Furthermore, a method for manufacturing a substrate with a feed-through, characterized by forming by polishing.
の製造方法であって、基板材料をエッチングすることで
溝を形成し、この溝に配線材料を充填しさらに研磨によ
り成形することを特徴とするフィードスルー付き基板の
製造方法。7. The method for manufacturing a substrate with a feed-through according to claim 1, wherein a groove is formed by etching the substrate material, the groove is filled with a wiring material, and the groove is formed by polishing. To manufacture a substrate with feedthrough.
（ＲｅａｃｔｉｖｅＩｏｎ Ｅｔｃｈｉｎｇ）により行
い、配線材料の充填をメッキにより行うことを特徴とす
るフィードスルー付き基板の製造方法。8. The method according to claim 7, wherein the etching is performed by RIE.
(Reactive Ion Etching), and filling the wiring material by plating.
付き基板の間に、マイクロデバイスを挟みこみパッケー
ジすることにより製造されることを特徴とするマイクロ
マシンセンサーおよびアクチュエータ。9. A micromachine sensor and an actuator manufactured by sandwiching and packaging a microdevice between the substrates with the feedthrough according to claim 1.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31366699A JP2001129800A (en) | 1999-11-04 | 1999-11-04 | Substrate with field-through and manufacturing method therefor |
| PCT/JP2000/007556 WO2001032555A1 (en) | 1999-11-04 | 2000-10-27 | Substrate with feedthrough and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31366699A JP2001129800A (en) | 1999-11-04 | 1999-11-04 | Substrate with field-through and manufacturing method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001129800A true JP2001129800A (en) | 2001-05-15 |
Family
ID=18044061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31366699A Pending JP2001129800A (en) | 1999-11-04 | 1999-11-04 | Substrate with field-through and manufacturing method therefor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2001129800A (en) |
| WO (1) | WO2001032555A1 (en) |
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Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0428225A (en) * | 1990-05-23 | 1992-01-30 | Fujitsu Ltd | Pattern formation and manufacture of semiconductor device |
| JPH0794441A (en) * | 1993-09-21 | 1995-04-07 | Sony Corp | Semiconductor device and its manufacture |
| JP2725605B2 (en) * | 1994-07-29 | 1998-03-11 | 日本電気株式会社 | Manufacturing method of printed wiring board |
| JP3689529B2 (en) * | 1996-05-14 | 2005-08-31 | キヤノン株式会社 | Manufacturing method of liquid crystal element |
| JP4109737B2 (en) * | 1997-12-05 | 2008-07-02 | 株式会社東芝 | Circuit board manufacturing method and circuit board manufacturing apparatus |
-
1999
- 1999-11-04 JP JP31366699A patent/JP2001129800A/en active Pending
-
2000
- 2000-10-27 WO PCT/JP2000/007556 patent/WO2001032555A1/en not_active Application Discontinuation
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