JP2001127303A - Thin-film transistor array substrate and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expose a gate, drain, and auxiliary capacity terminal part provided on a thin-film transistor array substrate, with no degradation in productivity. SOLUTION: A process where a gate electrode 1, a gate bus line 2, a gate line terminal 3, an auxiliary capacity bus line 4, and an auxiliary capacity terminal 5 are formed on a glass substrate 18, and a process where a multi-layer gate insulating film (silicon oxide film 14, silicon nitride film 15) is formed, are provided before formation of a functional element. After that, a protective film 13 is formed over the entire surface of the substrate 18, and by etching twice, dry-etching and wet-etching with BHF, with the same resist pattern when opening a hole on the gate terminal 3, a drain line terminal 9, and the protective film on the auxiliary capacity terminal 5, a terminal part metal at a different layer is exposed. Then, a pixel electrode 11 and a terminal part transparent electrode 12 are formed to complete a thin-film transistor array substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (hereinafter, referred to as TET) array substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 23 shows the concept of a conventional active matrix liquid crystal display device having a channel-etch type thin film transistor. This active matrix liquid crystal display device has a thin film transistor (TF) as shown in FIG.
T) Substrate 130 and color filter substrate (hereinafter, referred to as
CF substrate) 131, and a structure in which a twisted nematic (TN) liquid crystal layer 132 is sandwiched therebetween. The TFT substrate 130 has a plurality of pixel electrodes 133 formed in a matrix, and the pixel electrodes 133 are thin film transistors (TFTs) 13 that are switching elements.
4 source electrodes 135.

A gate line 137 for supplying a scanning signal is connected to a gate electrode 136 of the TFT 134, and a data line 141 for inputting a display signal is connected to a drain electrode 138 to drive the TFT 134. CF substrate 131
Comprises a transparent electrode, an RGB color layer corresponding to each pixel, and a light shielding layer for light shielding.

Next, the structure of the TFT substrate will be described in detail.
The TFT 134 is formed on a TFT glass substrate 139 and has a gate electrode 136 connected to a gate line 137.
A gate insulating film 140 formed to cover the gate electrode 136; a drain electrode 138 connected to the data line 141 formed on the gate insulating film 140; a source electrode 135 connected to the pixel electrode 133; a-Si
Layer 142, drain electrode 138 and source electrode 13
N ⁺ a-Si provided between the gate electrode 5 and the a-Si layer 142
A layer 143, a drain electrode 138, a source electrode 135,
Pixel electrode 133, a-Si layer 142, n ⁺ a-Si layer 1
Passivation film 1 formed so as to cover 43
44. On the passivation film 144 and the pixel electrode 133, an alignment film for controlling the alignment and inclination (pretilt) of liquid crystal molecules is formed. As described above, a substrate formed from a TFT glass substrate to an alignment film is referred to as a TFT substrate. Also, 145
Is a contact hole, 146 is a back channel, 147
Is a color layer, 148 is a counter electrode, 149 is a black matrix, 150 is a light transmission area, and 151 is a light leakage area.

Next, a method of manufacturing a TFT substrate will be described with reference to FIG. FIG. 24 shows the TF shown in FIG.
It is sectional drawing which shows the manufacturing process of a T substrate. As shown in FIG. 24A, first, a first conductive film made of Cr or Al-Nd is deposited on a transparent insulating substrate 139 such as glass by sputtering to a thickness of 100 nm to 300 nm, and is patterned. Thereby, the first line forming the gate-side terminal portion 136a connected to the gate line, the gate electrode 136, and the external signal processing substrate for display is formed.
Is performed.

Next, as shown in FIG. 24B, a gate insulating film 140 made of a SiN film or the like and an a-Si layer 142
And an n ⁺ a-Si film 143 are successively laminated by plasma CVD to a thickness of about 300 nm, 350 nm, and 50 nm, respectively, to form an a-Si film 142 and an n ⁺ a-Si
A second patterning step for patterning the film 143 at once is performed.

Next, as shown in FIG. 24C, an unnecessary gate insulating film such as the gate insulating film 140 on the gate side terminal portion 136a is removed by using a fluorine-based gas to remove the opening 1.
A third patterning step for forming 52 is performed.

Next, as shown in FIG. 24D, Cr or Mo is deposited on the gate insulating film 140 and the n ⁺ a-Si film 143 to a thickness of about 100 nm by sputtering, and is patterned. As a result, a fourth patterning step for forming the source electrode 135, the drain electrode 138, the data line, and the data-side terminal portion 153 connected to the external signal processing substrate for display is performed.

Next, as shown in FIG. 24E, a fifth electrode patterning step of forming a pixel electrode 133 by depositing a transparent electrode of ITO or the like with a thickness of about 50 nm by sputtering and patterning the transparent electrode. And by engraving the back channel of the TFT,
Unnecessary portions of the n ⁺ a-Si film are removed.

Next, as shown in FIG. 1F, an SiN film as an insulator is formed to a thickness of 300 nm by plasma CVD so as to cover the back channel, source electrode, drain electrode, data line, and terminal of the TFT. After forming a passivation film for protecting the thin film transistor, unnecessary passivation films on the pixel portion and the gate side and the data side terminal portion are removed to form openings O1,
A sixth patterning step for forming O2 and O3 is performed. Finally, the TFT substrate is annealed at 250 ° C. for about 30 minutes.
Through the six patterning steps described above, a TFT substrate of a liquid crystal display device is manufactured.

The structure of the external connection terminal based on the above-mentioned conventional manufacturing method is described in Japanese Patent Application Laid-Open No. 5-243333, and will be described with reference to FIGS. 25, 26, 27 and 28. 26 and 27 are plan views of the gate-side terminal and the data-side terminal, and FIGS. 25 and 28 are cross-sectional views of each. Both the gate side terminal and the data side terminal have a structure in which a lower layer metal forming a gate electrode and the like is provided, a contact hole is formed only in a part of the lower layer metal, and an upper layer metal forming a drain electrode and the like is formed. The structure is such that a transparent electrode forming a pixel electrode or the like is formed as an uppermost layer so as to completely cover a contact hole and cover an upper metal layer.

As shown in FIGS. 25 to 28, a gate electrode 31 and a gate bus line 32 are formed on a transparent insulating substrate 30 using a metal such as chromium, and then a silicon oxide, silicon nitride or the like is used. An operating semiconductor film 35 composed of the gate insulating film 33 and the amorphous silicon 34 having the multilayer structure is continuously formed, and an island of the operating semiconductor is formed on the gate electrode 31.

Then, a contact hole 28 is formed in the insulating film of the terminal portion in order to obtain an electrical connection between the terminal portion lower layer metal 36 and the terminal portion upper layer metal 37. Further, the terminal portion upper layer metal 37, the signal line 39, the source electrode 40, and the drain electrode 41 are formed by using a metal such as chromium.

Next, oxides of indium and tin (ITO:
The transparent electrode 42 and the pixel electrode 43 of the terminal portion made of Indium Tin Oxide are formed. Subsequent to this step, the TFT is completed by removing the phosphorus-doped amorphous silicon between the source electrode 40 and the drain electrode 41, and furthermore, silicon nitride or the like is formed on the entire surface of the substrate, and the gate terminal, The TFT array substrate is completed by removing the drain terminal and the film on the pixel electrode.

Known examples for the purpose of shortening the photolithography process, particularly for removing the insulating film at the terminal portion, are disclosed in JP-A-62-298117 and JP-A-62-278117.
298118, JP-A-6-102528 and the like.

Japanese Patent Application Laid-Open No. Sho 62-298117 discloses that a thin film transistor protective film is formed while leaving a photoresist formed when an upper metal layer is formed, and a photolithography step of removing the protective film using a lift-off method. The content that it is omitted is described.

Japanese Patent Application Laid-Open No. Sho 62-298118 discloses a method in which a metal film is left at an end of a gate bus line, an end of a drain bus line, and an end of an auxiliary capacitance bus line and exposed from the back using a negative resist. And that the number of photomasks is reduced by one.

JP-A-6-102528 describes two methods. One of the methods is that a protective film is formed on the entire surface after the upper metal layer is formed, and a transparent electrode is formed while leaving a photoresist used for opening the gate bus line end, the auxiliary capacitance bus line end, and the drain bus line. It is intended to shorten the photolithography process by forming a pixel electrode and a terminal portion cover electrode using a film lift-off method.

Another method described in JP-A-6-102528 discloses a method in which a polyimide film is formed at an end of a gate bus line and an end of an auxiliary capacitance bus line, and a gate insulating film, an operating semiconductor film and the like are provided. After that, after a drain electrode pixel electrode is formed and a protective film is formed, a photoresist having a pattern opened at an end of the drain bus line, an end of the gate bus line, and an end of the auxiliary capacitance bus line is provided. The end of the bus line is etched using the transparent electrode on the terminal and the end of the gate bus line as an etching stopper, and the end of the auxiliary capacitance bus line is etched using the polyimide film as an etching stopper, and the polyimide film is removed by dry etching. The photolithography process of the contact hole that establishes electrical conduction between the upper and lower metal layers It is those of the content to remove.

[0020]

However, FIG.
The conventional method of manufacturing a thin film transistor substrate shown in FIGS. 3 and 24 requires six patterning steps. In particular, as shown in Japanese Patent Application Laid-Open No. 5-243333, a contact hole for establishing conduction between upper and lower metal layers is formed. In this case, two patterning steps are required for the insulating film removing step, i.e., the patterning step for removing the protective film on the end of the bus line and the patterning step for removing the protective film on the end of the bus line.

Further, Japanese Patent Application Laid-Open No. Sho 62-298117,
In the prior art disclosed in JP-A-6-102528, a method in which a source insulating film is not formed at the end of each bus line is used. However, this method is effective when one kind of product is produced. In the case of producing a large variety of products, there is a problem that it is necessary to limit and change the film formation region of the gate insulating film for each product.

Further, Japanese Patent Application Laid-Open No. 62-298117,
In the prior art disclosed in JP-A-6-102528, a lift-off method is used in which a film is formed on a photoresist and the film is simultaneously peeled off when the resist is peeled off. There is a problem that it occurs and lowers the yield.

In the prior art disclosed in Japanese Patent Application Laid-Open No. 6-102528, a step of forming a polyimide film at the end of a lower metal bus line is added, so that the number of photolithography steps increases. There was a point.

In the prior art disclosed in Japanese Patent Application Laid-Open No. Sho 62-298117, the number of photomasks can be reduced, but the production process is no different from the conventional one and does not contribute to cost reduction. There was a point.

An object of the present invention is to provide a thin film transistor array substrate which can be manufactured by a smaller number of patterning steps in the channel etch type thin film transistor substrate forming process than before, and a method of manufacturing the same.

[0026]

In order to achieve the above object, a method of manufacturing a thin film transistor array substrate according to the present invention includes a step of selectively forming a lower metal layer on a transparent substrate; Covering the metal layer with a gate insulating film, selectively forming an active semiconductor film and an upper metal layer on the gate insulating film, and protecting the gate insulating film, the active semiconductor film and the upper metal layer with a protective film The protective film and the gate insulating film are selectively removed by wet etching and the subsequent dry etching using the same mask, and a part of each of the lower metal layer and the upper metal layer. Exposing.

The dry etching is performed by SF ₆ , CF ₄ , C
It is performed using a gas containing at least one of HF ₃ , and the pressure is 20 Pa or more and 40 Pa or less.

Further, in the method of manufacturing a thin film transistor array according to the present invention, a step of selectively forming a lower metal layer on a transparent substrate; a step of covering the transparent substrate and the lower metal layer with a gate insulating film; A step of selectively forming an active semiconductor film and an upper metal layer on the gate insulating film; a step of covering the gate insulating film, the active semiconductor film and the upper metal layer with a protective film; and performing two-stage dry etching. Selectively removing the protective film and the gate insulating film to expose a part of each of the lower metal layer and the upper metal layer.

In the first stage of the dry etching, SF
₆ , a gas containing at least one of CF ₄ and CHF ₃ is used, and the pressure is 20 Pa or more and 40 Pa or less.

Further, in the method of manufacturing a thin film transistor array according to the present invention, a step of selectively forming a lower metal layer on a transparent substrate; a step of covering the transparent substrate and the lower metal layer with a gate insulating film; Selectively forming a working semiconductor film and an upper metal layer on the gate insulating film; covering the gate insulating film, the working semiconductor film and the upper metal layer with a protective film; SF ₆ , CF ₄ , and CHF ₃ of using a gas containing at least one, or more 20 Pa 40 Pa
By performing dry etching under the following pressure, the protective film and the gate insulating film are selectively removed,
Exposing a part of each of the lower metal layer and the upper metal layer.

The method further comprises a step of covering a part of each of the exposed lower metal layer and upper metal layer with a transparent electrode.

The gate insulating film has a multilayer structure.

The method further comprises the step of removing the altered layer formed on the exposed upper metal layer.

The step of removing the altered layer formed on the exposed upper metal layer is performed by dry etching using a gas containing at least one of Ar, He, N ₂ , O ₂ and HCl.

Further, the thin film transistor array substrate according to the present invention is a thin film transistor array substrate of a type in which liquid crystal is operated by an electric field in a lateral direction with respect to a transparent insulating substrate, wherein a gate bus line selectively formed on the substrate is provided. A gate insulating film covering the gate bus line, a drain bus line selectively formed on the gate insulating film, a protective film covering the drain bus line and the gate insulating film, the protective film and the gate insulating film. A first contact hole formed through both of the films to expose a part of the gate bus line, and a second contact hole formed through the protective film to expose a part of the drain bus line And a transparent electrode covering a part of each of the exposed gate bus line and drain bus line. To.

The transparent electrode covering a part of the exposed gate bus line has a protrusion interposed between the gate insulating film and the gate bus line, and the transparent electrode covers a part of the exposed drain bus line. The covering transparent electrode has a protruding portion interposed between the protective film and the drain bus line.

Another part of the gate bus line functions as a gate electrode of the thin film transistor, and a layer of the same material as the transparent electrode is formed on the gate electrode.

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view showing a TN type thin film transistor array according to Embodiment 1 of the present invention. FIG. 2 is a sectional view taken along line AA ′ of FIG. 1 showing a gate bus line terminal portion and a thin film transistor portion.
FIG. 2 is a sectional view taken along line BB ′ of FIG. 1 showing a drain bus line terminal portion. 4 to 17 are sectional views showing a method of manufacturing the thin film transistor array according to the first embodiment of the present invention in the order of steps.

Referring to the figure, a thin film transistor array substrate according to the first embodiment of the present invention includes thin film transistors arranged in a matrix on a transparent insulating substrate 18;
Gate electrode 1 and drain electrode 8a of the thin film transistor
Bus line 2 and drain bus line 8 connected to the pixel electrode 1 and the pixel electrode 1 driven by the thin film transistor
And the thin film transistor includes a gate electrode 1, a gate insulating film 14, a working semiconductor film 6, and a source / drain electrode 7, 8a on a transparent insulating substrate 18.
Are sequentially laminated. Further, the thin film transistor array has the auxiliary capacitance bus line 4 which faces the pixel electrode 11 via the gate insulating film 14. Also, 3
Is a gate line terminal, 5 is an auxiliary capacitance terminal, 9 is a drain line terminal, 10 is a through hole, 12 is a terminal part transparent electrode, and 13 is a protective film.

Further, in the peripheral circuit of the thin film transistor, it is necessary to connect the gate layer and the drain layer, which is performed via the uppermost pixel electrode layer.

The above-described method for manufacturing the thin film transistor array substrate according to the first embodiment of the present invention basically includes a gate / bus forming step, a working semiconductor forming step, a functional element / bus forming step, an opening Part forming step,
The method includes at least a pixel electrode forming step, and after forming a multi-layered gate insulating film and a working semiconductor film in the working semiconductor forming step, operates as a thin film transistor and a portion where a gate bus line and a drain bus line overlap. An operating semiconductor is formed in the part,
A source electrode and a drain electrode of a thin film transistor are formed on the gate insulating film and the operating semiconductor in the bus forming step, and a drain bus line connected to the drain electrode is formed. After forming the protective film, a gate insulating film and a protective film on the gate electrode,
The protective film on the drain bus line terminal portion and the auxiliary capacitance terminal portion is removed, and the pixel electrode is formed of a transparent electrode in the pixel electrode forming step.

Next, a specific example of the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention will be described with reference to FIGS.
It will be described based on FIG. First, as shown in FIG. 4, a lower metal film 19 is formed on a glass substrate (transparent insulating substrate) 18 that has been subjected to a surface treatment such as cleaning using a sputtering method. As the metal film 19, Cr, Mo, Al, Ta, Ti, or the like is used.

Next, as shown in FIG. 5, a photoresist 20 serving as an etching mask is formed on the lower metal film 19 through a photolithography process of applying, exposing, and developing a photoresist. Further, the lower layer metal 19 is subjected to wet etching using the patterned photoresist 20 as a mask, and thereafter, the resist is peeled off, the substrate 18 is washed, and as shown in FIG. 1, a gate line terminal 3, and a gate bus line 2, an auxiliary capacitance bus line 4, and an auxiliary capacitance terminal 5 shown in FIG.

Next, as shown in FIG. 7, a silicon oxide film 14 using a sputtering method, a silicon nitride film 15 and an amorphous silicon film 21 (a-S
i + n ⁺ -a-Si) is continuously deposited on the entire surface of the substrate 18.

Next, as shown in FIG. 8, on the amorphous silicon film 21 of the substrate 18 on which the film was formed, the film was patterned through a photolithography process as a mask for forming a region to be a functional element (operation) of the thin film transistor. A photoresist 20 is formed.

Next, as shown in FIG.
0 as a mask, the amorphous silicon film 2 on the substrate 18
1 is etched by a dry etching method, the photoresist 20 is peeled off, the substrate 18 is washed, and an amorphous silicon film (amorphous silicon pattern 6 in FIG. 1) 21 forming a thin film transistor is formed.
Get.

Next, as shown in FIG. 10, an upper metal film 22 is formed on the entire surface of the glass substrate 18 by using a sputtering method.

Next, as shown in FIG. 11, a photoresist 2 patterned by a photolithography process
0 is formed on the upper metal film 22.

Next, as shown in FIG. 12, dry etching using a chlorine-based gas is performed on the upper metal film 22 of the substrate 18 using the photoresist 20 as a mask. Thereafter, the resist 20 is peeled off, and the substrate 18 is washed. Then, the source electrode 7 and the drain bus line 8 of the thin film transistor shown in FIG. 12 and the drain line terminal 9 shown in FIG. 1 are formed. Further, the n ⁺ -a-Si 21 is etched using the drain bus line 8 and the source electrode 7 as a mask to form a thin film transistor.

Next, as shown in FIG. 13, a protective film 13 made of silicon nitride is formed on the entire surface of the substrate 18 by a plasma CVD method.

Next, FIG.
Then, a photoresist 20 serving as a mask for opening the through hole 10 is formed on the source electrode 7, the gate line terminal 3, and the drain line terminal 9 as shown in FIG.

Next, as shown in FIG. 15, using the photoresist 20 as a mask, the substrate 18 is wet-etched with an etching solution of BHF (buffered hydrofluoric acid) to remove the protective film 13 and the silicon nitride film 15. Source electrode 7,
A through hole 10 is opened on the gate line terminal 3 and the drain line terminal 9. At this time, in the part of the source electrode 7 and the drain line electrode 9 shown in FIG. 1, the upper metal film 22 serves as an etching stopper, only the protective film 13 is etched, and the silicon nitride film 15 is not etched. In addition, in the portion of the gate line terminal 3 and the auxiliary capacitance terminal 5, the silicon nitride 15 is etched because there is no stopper function by the upper layer metal 22. However, the silicon nitride film 15 serves as an etching stopper because the etching rate is lower than that of the protective film 13 and is not completely removed.

Therefore, the silicon nitride film 15 and the silicon oxide film 14 are removed by dry etching while leaving the photoresist 20 on the substrate 18 as it is. Also in this process, the upper metal film 22 functions as an etching stopper in the portion of the source electrode 7 and the drain line terminal 9.
Thereafter, the photoresist 20 is peeled off, and the substrate 18 is washed to obtain the structure shown in FIG.

Next, as shown in FIG. 16, an oxide of indium and tin (ITO: Indium T) is formed on the entire surface of the substrate 18.
in Oxide) 23 by using a sputtering method,
Photoresist 20 is removed by photolithography process.
Formed on TO23. Thereafter, wet etching is performed on the ITO 23 using the photoresist 20 as a mask. Thereafter, the photoresist 20 is peeled off, and the substrate 18 is washed to form the pixel electrode 11 and the terminal portion transparent electrode 12 shown in FIGS. I do. Thus, the thin film transistor array substrate is completed.

As described above, in the first embodiment of the present invention,
The step of removing an unnecessary gate insulating film and the step of removing an unnecessary protective film are performed in the same patterning step, thereby forming a channel-etch type thin film transistor substrate by five patterning steps in which the number of patterning steps is one less than in the past. Is possible.

As described above, the step of removing the gate insulating film and the protective film is performed in the same patterning step, and the upper metal film 22 serves as an etching stopper in the openings such as on the source electrode and the drain electrode. However, since the upper metal film 22 is exposed to plasma of a fluorine-based gas such as SF ₆ , CF ₄ , CHF ₃ for a long time, depending on the plasma conditions, the metal of about 200 to 400 ° F. An altered layer is formed. If a deteriorated layer occurs on the surface of the upper metal layer and the contact resistance of the drain electrode increases or the contact resistance of the contact in the pixel increases,
Display failure occurs.

As a result of the experiment, it was found that when the drain terminal contact resistance was 5 kΩ or more, unnecessary dulling occurred in the data signal, and a dim D line defect occurred. FIG.
FIG. 3 is a diagram illustrating a relationship between a contact resistance of a contact in a pixel and display unevenness. As is clear from FIG. 21, the contact resistance must be within 1 MΩ, and the variation must be 100 kΩ / cm or less.

FIG. 22 shows that the opening of the drain electrode formed under various dry etching conditions is 400 ° / mi.
FIG. 7 is a diagram showing a result obtained by performing Ar sputtering with n and performing Auger analysis on a depth profile thereof. As is clear from FIG. 22, under a dry etching condition of a low pressure of about 1 to 15 Pa, a deteriorated layer of about 200 to 400 ° is formed on the upper metal surface, whereas under a dry etching condition of a high pressure of about 20 to 40 Pa, It can be seen that the variable mass is suppressed.

However, by changing the dry etching to a high pressure, the deteriorated layer on the upper metal surface can be suppressed. However, when the pressure is increased, the etching ability is reduced, and a part of the gate insulating film such as silicon oxide is formed. In the case where is used, it may not be possible to completely remove the silicon oxide depending on the film quality of the silicon oxide. To avoid this, dry etching is divided into two stages. In the first stage, part of the protective film and the gate insulating film is removed using high-pressure plasma, and in the second stage, low-pressure plasma is removed. Alternatively, the remaining gate insulating film may be removed.

After opening the drain electrode by dry etching, Ar, H
A good contact can also be obtained by performing reverse sputtering using plasma of a gas such as e, O ₂ , HCl or the like to remove the variable mass on the metal surface. By performing the above processing, the contact resistance of the drain electrode and the contact hole in the pixel can be reduced.

(Embodiment 2) Next, Embodiment 2 of the present invention will be described. FIG. 18 is a plan view showing a thin film transistor array substrate according to Embodiment 2 of the present invention, in which a liquid crystal is operated by applying a horizontal electric field (horizontal electric field) to a transparent insulating substrate. FIG. FIG. 19 is a cross-sectional view taken along the line CC ′ of FIG. 18 showing the gate line terminal 3 and the thin film transistor unit. FIG.
0 is a sectional view taken along the line DD ′ of FIG. 18 showing the drain line terminal 9 and the auxiliary capacitance terminal 5.

In the figure, the thin-film transistor array substrate according to the second embodiment of the present invention has a counter electrode provided in a TFT substrate without using the counter electrode of the counter substrate, and a horizontal electric field (horizontal electric field) is applied to the substrate. This is a method using a horizontal electric field called a method for controlling liquid crystal by using a pixel electrode 1.
Reference numeral 1 denotes a comb-shaped electrode, which utilizes a horizontal electric field generated between the auxiliary capacitance bus line 4 and the pixel electrode 11 in FIG. 18, and therefore does not require a transparent electrode as in the TN method.

In the method for manufacturing a thin film transistor array substrate according to the second embodiment of the present invention, the functional element
What is claimed is: 1. A method for manufacturing a thin film transistor array substrate comprising a pixel electrode forming step and an opening forming step, the thin film transistor array substrate comprising: a thin film transistor arranged in a matrix on a transparent insulating substrate; and a gate electrode of the thin film transistor. 1 and a gate bus line 2 and a drain bus line 8 connected to the drain electrode 9, an auxiliary capacitance bus line 4, and a pixel electrode 11 driven by the thin film transistor. The liquid crystal is controlled by utilizing a horizontal electric field generated between the capacitor bus line 4 and the capacitor bus line 4.
In the lower layer electrode / bus forming step, a gate electrode 1, a gate bus line 2 connected to the gate electrode 1, and an auxiliary capacitance bus line 4 are formed on the transparent insulating substrate 18. Line 4 auxiliary capacitance terminal 5
A process of laminating and forming a transparent metal (electrode) 16 on a lower electrode is performed thereon, and a process of forming an operation semiconductor 21 in a portion of the multi-layered gate insulating films 14 and 15 that operates as a transistor is performed in an operation semiconductor formation process. Forming a drain electrode of a thin film transistor and a drain bus line 8 connected to the drain electrode on the gate insulating films 14 and 15 and the operating semiconductor 21 in a functional element / bus / pixel electrode forming step; The pixel electrode 11 is formed from the metal forming the bus line 8, and the transparent electrode 17 on the upper electrode is formed on the drain electrode, the drain terminal 9 of the drain bus line 8, and the pixel electrode 11. In the forming step, after forming the protective film 13 on the entire surface of the substrate 18, the unnecessary protective film 13 is removed, and the gate electrode 1 is removed. And a transparent metal (electrode) 16 on the lower electrode on the auxiliary capacitance terminal 5 of the auxiliary capacitance bus line 4 and a transparent metal (electrode) 17 on the upper electrode on the drain terminal 9 of the drain bus line 8 are exposed. .

Therefore, according to the second embodiment of the present invention, there is an advantage that the step of forming a transparent electrode and the photolithography step in the step of FIG. 16 of the first embodiment can be omitted. However, from the viewpoint of the connection reliability between the gate bus line 1, the drain bus line 8, the auxiliary capacitance terminal 5 and the drive circuit, it is better to use IT than the wiring metal material.
It is desirable to use O. This is because the prior art utilizes an anisotropic conductive film developed for a simple matrix, and is therefore designed with the highest priority on connectivity with a transparent electrode (ITO).

In the second embodiment of the present invention, as shown in FIGS. 19 and 20, when the lower electrode upper transparent metal 16 and the upper electrode upper transparent metal 17 are formed, the wiring metal (gate electrode, gate electrode) is formed. , A drain terminal, an auxiliary capacitance terminal, etc.), a transparent metal (ITO) film formation, and a photolithography process.

As described above, according to the second embodiment of the present invention, there is an advantage that the photolithography process can be further reduced by one process as compared with the first embodiment.

[0068]

According to the present invention as described above,
The process of exposing the gate line, the drain line, and the auxiliary capacitance terminal can be reliably performed by one photolithography process.

More specifically, in the prior art, six photolithography steps (PR steps) were required, but in the invention described in the first embodiment, a thin film transistor array substrate was manufactured in five PRT steps. can do.

Since the lift-off method is not used unlike the prior art, no dust is generated by performing the lift-off method. Further, in the prior art, the productivity is reduced by restricting the film formation by a metal mask method or the like of the terminal portion and by applying polyimide to the lower layer terminal portion and using it as an etching stopper, but according to the present invention, There is no factor that reduces productivity, and the process can be shortened.

[Brief description of the drawings]

FIG. 1 is a plan view showing a thin film transistor array substrate according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line A-A 'of FIG.

FIG. 3 is a sectional view taken along line B-B 'of FIG.

FIG. 4 is a sectional view illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 7 is a sectional view illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 8 is a sectional view illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 9 is a sectional view illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 10 is a sectional view illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 11 is a sectional view illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 12 is a sectional view illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 13 is a sectional view illustrating the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 14 is a sectional view illustrating the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 15 is a sectional view illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 16 is a sectional view illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 17 is a sectional view illustrating the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention in the order of steps.

FIG. 18 is a plan view showing a thin film transistor array substrate according to a second embodiment of the present invention.

FIG. 19 is a sectional view taken along line C-C ′ of FIG. 18;

20 is a sectional view taken along line D-D 'of FIG.

FIG. 21 is a diagram showing the relationship between the contact resistance of the intra-pixel contact and the display unevenness.

FIG. 22 shows an opening of a drain terminal (electrode) formed under various dry etching conditions at 400 ° / min.
FIG. 5 is a diagram showing a depth profile obtained by performing an Auger analysis on Ar sputtering performed in FIG.

23A and 23B show a conventional active matrix liquid crystal display device having a channel-etch type thin film transistor, wherein FIG. 23A is a plan view, FIG. 23B is a cross-sectional view taken along the line AA of FIG. It is BB sectional drawing of a).

24 is a cross-sectional view illustrating a method of manufacturing the active matrix liquid crystal display device having the channel-etched thin film transistor illustrated in FIG. 23 in the order of steps.

FIG. 25 is a sectional view showing a conventional thin film transistor array substrate.

FIG. 26 is a plan view showing a conventional thin film transistor array substrate.

FIG. 27 is a plan view showing a conventional thin film transistor array substrate.

28 (a) is a view taken along line EE ′ of FIG. 26, FIG.
26 is a sectional view taken along line HH ′, and FIG.
It is a sectional view taken along line JJ ′.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate electrode 2 Gate bus line 3 Gate line terminal 4 Auxiliary capacitance bus line 5 Auxiliary capacitance terminal 6 Amorphous silicon 7 Source electrode 8 Drain bus line 9 Drain line terminal 10 Through hole 11 Pixel electrode 12 Terminal transparent electrode 13 Protective film 14 Oxidation Silicon film 15 Silicon nitride film 16 Transparent metal on lower electrode 17 Transparent metal on upper electrode 18 Glass substrate 19 Lower metal film 20 Photoresist 21 Amorphous silicon film 22 Upper metal film 23 ITO

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/3065 H01L 21/306 D 21/306 S 29/78 612D 617U

Claims (12)

[Claims] A step of selectively forming a lower metal layer on a transparent substrate; a step of covering the transparent substrate and the lower metal layer with a gate insulating film; and a step of forming an operating semiconductor film and an upper metal layer on the gate insulating film. A step of selectively forming a layer, a step of covering the gate insulating film, the operating semiconductor film and the upper metal layer with a protective film, and a wet etching using the same mask and a subsequent dry etching to form the protective film. And selectively removing the gate insulating film to expose a part of each of the lower metal layer and the upper metal layer. 2. The dry etching includes SF ₆ , CF ₄ ,
It performed using a gas containing at least one of CHF _3, the method of manufacturing the thin film transistor array substrate according to claim 1, wherein the the pressure is less 40Pa or 20 Pa. 3. A step of selectively forming a lower metal layer on a transparent substrate, a step of covering the transparent substrate and the lower metal layer with a gate insulating film, and a step of forming an active semiconductor film and an upper metal layer on the gate insulating film. A step of selectively forming a layer, a step of covering the gate insulating film, the operating semiconductor film and the upper metal layer with a protective film, and a two-stage dry etching, whereby the protective film and the gate insulating film are formed. Selectively exposing the lower metal layer and the upper metal layer to partially expose the lower metal layer and the upper metal layer. 4. The first stage of the dry etching is S
_{4. The} method for manufacturing a thin film transistor array substrate according to claim 3, wherein the method is performed using a gas containing at least one of F ₆ , CF ₄ , and CHF ₃ , and the pressure is 20 Pa or more and 40 Pa or less. 5. A step of selectively forming a lower metal layer on a transparent substrate, a step of covering the transparent substrate and the lower metal layer with a gate insulating film, and a step of forming an active semiconductor film and an upper metal layer on the gate insulating film. Selectively forming a layer, covering the gate insulating film, the operating semiconductor film and the upper metal layer with a protective film, and using a gas containing at least one of SF ₆ , CF ₄ , and CHF ₃ , Performing dry etching under a pressure of 20 Pa or more and 40 Pa or less to selectively remove the protective film and the gate insulating film, thereby exposing a part of each of the lower metal layer and the upper metal layer; A method for manufacturing a thin film transistor array substrate, comprising: 6. The method according to claim 1, further comprising a step of covering each of the exposed lower metal layer and upper metal layer with a transparent electrode. 7. The method according to claim 1, wherein the gate insulating film has a multilayer structure. 8. The method according to claim 1, further comprising removing a deteriorated layer formed on the exposed upper metal layer. 9. The step of removing the altered layer formed on the exposed upper metal layer includes the steps of Ar, He, N ₂ , O ₂ , and HCl.
9. The method according to claim 8, wherein the etching is performed by dry etching using a gas containing at least one of the following. 10. A thin film transistor array substrate of a type in which liquid crystal is operated by an electric field in a lateral direction with respect to a transparent insulating substrate, wherein a gate bus line selectively formed on the substrate and a gate insulating covering the gate bus line. Film, a drain bus line selectively formed on the gate insulating film, a protective film covering the drain bus line and the gate insulating film, and formed through both the protective film and the gate insulating film. A first contact hole exposing a part of the gate bus line, a second contact hole formed through the passivation film and exposing a part of the drain bus line, And a transparent electrode covering a part of each of the drain bus lines. Board. 11. A transparent electrode covering a part of the exposed gate bus line has a protruding portion interposed between the gate insulating film and the gate bus line. The thin film transistor array substrate according to claim 10, wherein the transparent electrode covering the portion has a protruding portion interposed between the protective film and the drain bus line. 12. The gate bus line according to claim 11, wherein another part of the gate bus line functions as a gate electrode of the thin film transistor, and a layer of the same material as that of the transparent electrode is formed on the gate electrode. The thin film transistor array substrate according to any one of the preceding claims.