JP2001127103A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001127103A JP2001127103A JP30295199A JP30295199A JP2001127103A JP 2001127103 A JP2001127103 A JP 2001127103A JP 30295199 A JP30295199 A JP 30295199A JP 30295199 A JP30295199 A JP 30295199A JP 2001127103 A JP2001127103 A JP 2001127103A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- anisotropic conductive
- conductive film
- conductive particles
- connection pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はコンピューター等の
情報処理装置に実装される半導体装置に関し、より詳細
には半導体素子の電極を配線基板の接続パッドに異方性
導電膜を介して接続して成る半導体装置に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted on an information processing apparatus such as a computer, and more particularly to a semiconductor device in which electrodes of a semiconductor element are connected to connection pads of a wiring board via an anisotropic conductive film. The present invention relates to a semiconductor device comprising:
【０００２】[0002]
【従来の技術】半導体装置は、従来、半導体素子と、半
導体素子を実装する配線基板と、半導体素子と配線基板
とを電気的、機械的に接続して実装する異方性導電膜
（ＡＣＦ）等の接続材とから形成されている。2. Description of the Related Art Conventionally, a semiconductor device includes a semiconductor element, a wiring board on which the semiconductor element is mounted, and an anisotropic conductive film (ACF) in which the semiconductor element and the wiring board are electrically and mechanically connected and mounted. And the like.
【０００３】前記配線基板は、酸化アルミニウム質焼結
体等のセラミックスから成り、上面に半導体素子搭載部
を有する絶縁基体と、タングステン、モリブデン、銅、
銀等のメタライズ金属層から成り前記搭載部の表面に形
成された接続パッドとにより形成されている。The wiring substrate is made of ceramics such as an aluminum oxide sintered body, and has an insulating base having a semiconductor element mounting portion on an upper surface, tungsten, molybdenum, copper, and the like.
And a connection pad formed of a metallized metal layer such as silver and formed on the surface of the mounting portion.
【０００４】また、前記異方性導電膜は、金、銀、銅等
の金属や、これらの金属を表面に被着させた有機樹脂か
ら成る導電粒子（平均径が１〜１０μｍ程度）を、厚さ
１５〜３０μｍの熱硬化性樹脂、熱可塑性樹脂、光硬化
性樹脂等の有機樹脂から成る樹脂フィルム中に分散させ
た構造を有している。Further, the anisotropic conductive film includes conductive particles (average diameter of about 1 to 10 μm) made of a metal such as gold, silver, and copper, and an organic resin having these metals adhered to the surface thereof. It has a structure in which it is dispersed in a resin film having a thickness of 15 to 30 μm and made of an organic resin such as a thermosetting resin, a thermoplastic resin, or a photocurable resin.
【０００５】かかる半導体装置は、例えば、前記搭載部
に形成された接続パッドと半導体素子下面の接続パッド
とを対向させるようにして、絶縁基体の搭載部上に半導
体素子を、間に異方性導電膜を挟んで載置させ、しかる
後、これらの半導体素子、異方性導電膜および配線基板
を上下方向に加圧し、同時に異方性導電膜の樹脂フィル
ムを硬化させることにより製作されており、前記加圧に
よって絶縁基体の接続パッドと半導体素子の電極とが異
方性導電膜の導電粒子を挟みつけて適度に扁平化させ、
この導電粒子を介して電気的に接続され、同時に絶縁基
体と半導体素子とが樹脂フィルムを介して接合されるこ
ととなる。In such a semiconductor device, for example, a semiconductor element is mounted on a mounting portion of an insulating base such that a connection pad formed on the mounting portion and a connection pad on a lower surface of the semiconductor element are opposed to each other. The semiconductor device, the anisotropic conductive film, and the wiring board are pressed vertically, and the resin film of the anisotropic conductive film is cured at the same time. The connection pad of the insulating base and the electrode of the semiconductor element are appropriately flattened by sandwiching the conductive particles of the anisotropic conductive film by the pressing,
Electrical connection is made via the conductive particles, and at the same time, the insulating base and the semiconductor element are joined via the resin film.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体装置は、酸化アルミニウム質焼結体等から成
る絶縁基体を形成するための焼成時、絶縁基体にソリ等
の変形が発生し易く、このソリ等に起因して絶縁基体の
搭載部表面に形成された全接続パッドの上面の平坦度が
通常３０μｍ以上と高く、上下方向の位置のばらつきが
大きいという欠点があり、このため接続パッドに半導体
素子の電極を異方性導電膜を介して接続する際、異方性
導電膜中の導電粒子を挟みつける力が複数の接続部間で
大きくばらついてしまい、各接続パッドと半導体素子の
電極との間に導電粒子を均一の圧力で挟みつけることが
できず、接続パッドおよび電極と導電粒子との接触面積
がばらついて接続部の電気抵抗が所定の抵抗値からばら
つき、半導体素子を正確に作動させることができなくな
るおそれがあるという問題があった。However, in the above-described conventional semiconductor device, when the insulating substrate made of an aluminum oxide-based sintered body or the like is fired, the insulating substrate is liable to be deformed such as warp. The flatness of the upper surface of all the connection pads formed on the mounting portion surface of the insulating base due to warpage or the like is high, typically as high as 30 μm or more, and there is a large variation in the position in the vertical direction. When the electrodes of the device are connected via the anisotropic conductive film, the force for sandwiching the conductive particles in the anisotropic conductive film varies greatly between the plurality of connection portions, and each connection pad and the electrode of the semiconductor device are connected to each other. The conductive particles cannot be sandwiched between the conductive particles at a uniform pressure, and the contact areas between the connection pads and the electrodes and the conductive particles vary, so that the electrical resistance of the connection portion varies from a predetermined resistance value. There is a problem that it may become impossible to accurately operate.
【０００７】また、前記メタライズ金属層により形成さ
れる接続パッドは、その表面粗さの最大高さＲｙ（ＪＩ
Ｓ規格）が０．５μｍ未満と、導電粒子の平均径（１〜
１０μｍ）に比べて小さいことから、導電粒子を捕捉、
保持する作用が弱く、この接続パッドと半導体素子の電
極との間に異方性導電膜を挟んで加圧したとき、十分な
数の導電粒子を接続面に捕捉、保持することが難しいた
め接続パッドと半導体素子の電極との間の接触面積が小
さくなって接触抵抗が高くなり、半導体装置の電気特性
を劣化させるおそれがあるという問題もあった。The connection pad formed by the metallized metal layer has a maximum surface roughness Ry (JI).
S standard) is less than 0.5 μm, and the average diameter of the conductive particles (1 to 1)
10 μm), which captures conductive particles,
Since the holding function is weak, it is difficult to capture and hold a sufficient number of conductive particles on the connection surface when the anisotropic conductive film is sandwiched between the connection pad and the electrode of the semiconductor element and pressed. There is also a problem that the contact area between the pad and the electrode of the semiconductor element is reduced, the contact resistance is increased, and the electrical characteristics of the semiconductor device may be degraded.
【０００８】本発明は、上記問題に鑑みて案出されたも
のであり、その目的は、半導体素子を配線基板に異方性
導電膜を介して実装して成る半導体装置において、配線
基板の各接続パッドに半導体素子の電極が、低接触抵抗
で、かつ各接続部間で電気的に均一に接続された半導体
装置を提供することにある。The present invention has been devised in view of the above problems, and has as its object to provide a semiconductor device in which a semiconductor element is mounted on a wiring board via an anisotropic conductive film. An object of the present invention is to provide a semiconductor device in which an electrode of a semiconductor element is connected to a connection pad with low contact resistance and electrically uniformly between each connection portion.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体装置は、
上面に複数個の接続パッドを有する絶縁基体と、下面に
複数個の電極を有する半導体素子とから成り、絶縁基体
上に半導体素子を搭載するとともに各接続パッドと各電
極とを樹脂フィルム中に導電粒子を分散させて成る異方
性導電膜を介して接続した半導体装置であって、前記全
接続パッド上面の平坦度を１５μｍ以下とするとともに
各接続パッドの表面粗さの最大高さ（Ｒｙ）を異方性導
電膜の導電粒子の平均径に対し１／２以上乃至１０μｍ
以下としたことを特徴とするものである。According to the present invention, there is provided a semiconductor device comprising:
An insulating substrate having a plurality of connection pads on an upper surface and a semiconductor element having a plurality of electrodes on a lower surface. The semiconductor element is mounted on the insulating substrate, and each connection pad and each electrode are electrically conductive in a resin film. A semiconductor device connected via an anisotropic conductive film in which particles are dispersed, wherein the flatness of the upper surface of all of the connection pads is set to 15 μm or less and the maximum height (Ry) of the surface roughness of each connection pad. Is 以上 or more to 10 μm with respect to the average diameter of the conductive particles of the anisotropic conductive film.
It is characterized by the following.
【００１０】本発明の半導体装置によれば、全接続パッ
ド上面の平坦度を１５μｍ以下としたことから、この接
続パッドと半導体素子の電極とを、樹脂フィルム中に金
属粒子を分散させて成る異方性導電膜を介して接続する
際、全接続パッドにほぼ均等に圧力を加えることがで
き、接続パッドと半導体素子の電極との間に導電粒子を
挟みつける力が各接続パッドの間で均等となり、各接続
部の電気抵抗がばらつくことを有効に防ぐことができ
る。According to the semiconductor device of the present invention, since the flatness of the upper surface of all the connection pads is set to 15 μm or less, the connection pads and the electrodes of the semiconductor element are formed by dispersing metal particles in a resin film. When connecting via an anisotropic conductive film, pressure can be applied almost uniformly to all connection pads, and the force for sandwiching conductive particles between the connection pads and the electrodes of the semiconductor element is equal between each connection pad Thus, it is possible to effectively prevent the electric resistance of each connection portion from varying.
【００１１】また、本発明の半導体装置によれば、各接
続パッドの表面粗さの最大高さＲｙを異方性導電膜の導
電粒子の平均径に対し１／２以上乃至１０μｍ以下と、
適度に粗面としたことから、接続パッドと半導体素子の
電極との間に異方性導電膜を挟んで加圧するとき、導電
粒子を前記適度に粗面とした接続パッド上面の谷部内に
容易に捕捉するとともにこれを確実に保持させることが
でき、その結果、十分な数の導電粒子が接続面に捕捉、
保持されることとなり接続パッドと半導体素子の電極と
の接触抵抗を十分低いものとし、電気特性に優れた半導
体装置を得ることができる。Further, according to the semiconductor device of the present invention, the maximum height Ry of the surface roughness of each connection pad is 以上 to 10 μm with respect to the average diameter of the conductive particles of the anisotropic conductive film.
Since the surface is moderately rough, when the anisotropic conductive film is interposed between the connection pad and the electrode of the semiconductor element and pressurized, the conductive particles are easily placed in the valley of the upper surface of the connection pad having the moderately rough surface. And ensure that it is retained, so that a sufficient number of conductive particles are captured on the connection surface,
As a result, the contact resistance between the connection pad and the electrode of the semiconductor element is made sufficiently low, so that a semiconductor device having excellent electrical characteristics can be obtained.
【００１２】[0012]
【発明の実施の形態】次に、本発明を添付図面に基づき
説明する。図１は本発明の半導体装置の一実施例を示す
断面図であり、１は絶縁基体、２は半導体素子、３は接
続パッド、４は異方性導電膜である。Next, the present invention will be described with reference to the accompanying drawings. FIG. 1 is a sectional view showing one embodiment of the semiconductor device of the present invention, wherein 1 is an insulating base, 2 is a semiconductor element, 3 is a connection pad, and 4 is an anisotropic conductive film.
【００１３】前記絶縁基体１は、酸化アルミニウム質焼
結体、窒化アルミニウム質焼結体、ムライト質焼結体、
炭化珪素質焼結体、ガラスセラミックス焼結体等の電気
絶縁材料から成る略四角形状の板体であり、その上面中
央部には半導体素子を搭載するための半導体素子搭載部
１ａを有しており、該半導体素子搭載部１ａに半導体素
子２が異方性導電膜４を用いて実装される。The insulating substrate 1 is made of an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body,
It is a substantially rectangular plate made of an electrically insulating material such as a silicon carbide sintered body or a glass ceramic sintered body, and has a semiconductor element mounting portion 1a for mounting a semiconductor element in the center of the upper surface thereof. The semiconductor element 2 is mounted on the semiconductor element mounting portion 1a using the anisotropic conductive film 4.
【００１４】前記絶縁基体１は、例えば酸化アルミニウ
ム質焼結体から成る場合であれば、酸化アルミニウム、
酸化珪素、酸化マグネシウム、酸化カルシウム等の原料
粉末に適当な有機バインダ、溶剤、可塑剤、分散材等を
添加混合して泥漿状となすとともにこれを従来周知のド
クターブレード法を採用してシート状となすことにより
複数枚のセラミックグリーンシートを得、しかる後、こ
のセラミックグリーンシートに適当な打ち抜き加工を施
すとともに必要に応じて上下に積層し、これを約１６０
０℃の温度で焼成することによって製作される。If the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, the insulating substrate 1 is made of aluminum oxide,
An appropriate organic binder, a solvent, a plasticizer, a dispersing agent, etc. are added to raw material powders such as silicon oxide, magnesium oxide, calcium oxide and the like to form a slurry, which is then formed into a sheet by employing a conventionally known doctor blade method. Then, a plurality of ceramic green sheets are obtained. Thereafter, the ceramic green sheets are subjected to an appropriate punching process, and if necessary, are laminated vertically to form a ceramic green sheet.
It is manufactured by firing at a temperature of 0 ° C.
【００１５】また、前記絶縁基体１はその搭載部１ａ表
面に、半導体素子２の電極２ａを接続させるための複数
の接続パッド３が半導体素子の電極２ａに対応して形成
され、この接続パッド３から絶縁基体１の下面にかけて
複数の配線導体５が導出形成されており、搭載部１ａ上
に半導体素子２を接合するとともに、この半導体素子の
電極２ａを接続パッド３に電気的に接続させることによ
って半導体装置として完成し、配線導体５の導出部を外
部電気回路に接続することにより、半導体素子２と外部
電気回路とが電気的に接続される。On the surface of the mounting portion 1a of the insulating base 1, a plurality of connection pads 3 for connecting the electrodes 2a of the semiconductor element 2 are formed corresponding to the electrodes 2a of the semiconductor element. A plurality of wiring conductors 5 are formed in a lead-out manner from the lower surface of the insulating base 1 to join the semiconductor element 2 on the mounting portion 1a and electrically connect the electrode 2a of this semiconductor element to the connection pad 3. By completing the semiconductor device and connecting the lead portion of the wiring conductor 5 to an external electric circuit, the semiconductor element 2 and the external electric circuit are electrically connected.
【００１６】前記接続パッド３及び配線導体５は、タン
グステン、モリブデン、銅、銀等の金属材料から成り、
例えば、タングステン、モリブデン、マンガン等の高融
点金属粉末から成る場合であれば、高融点金属粉末に適
当な有機溶剤、溶媒を添加混合して得た金属ペーストを
従来周知のスクリーン印刷法等の厚膜手法を採用し、絶
縁基体１となるセラミックグリーンシートの表面に予め
印刷塗布しておくことによって絶縁基体１の搭載部１ａ
から下面にかけて形成される。The connection pad 3 and the wiring conductor 5 are made of a metal material such as tungsten, molybdenum, copper, silver, etc.
For example, in the case of a metal powder having a high melting point such as tungsten, molybdenum, or manganese, a suitable organic solvent is added to the metal powder having a high melting point, and a metal paste obtained by adding and mixing a solvent is thickened by a conventionally known screen printing method. The mounting portion 1a of the insulating base 1 is formed by applying a film method and printing and coating the surface of the ceramic green sheet serving as the insulating base 1 in advance.
To the lower surface.
【００１７】また、前記半導体素子２は、その下面に金
バンプ等の電極２ａが導出形成されており、異方性導電
膜４により、下面が搭載部１ａ上に接合されるとともに
電極２ａが前記接続パッド３に電気的に接続されてい
る。The semiconductor element 2 has an electrode 2a such as a gold bump formed on the lower surface thereof. The lower surface of the semiconductor element 2 is joined to the mounting portion 1a by the anisotropic conductive film 4, and the electrode 2a is connected to the electrode 2a. It is electrically connected to the connection pad 3.
【００１８】前記異方性導電膜４は、半導体素子２を絶
縁基体１の搭載部１ａ上に接合させる接着剤として作用
するとともに、半導体素子２の電極２ａを接続パッド３
に電気的に接続させる導電性接続部材として作用する。The anisotropic conductive film 4 functions as an adhesive for bonding the semiconductor element 2 to the mounting portion 1a of the insulating base 1, and also connects the electrode 2a of the semiconductor element 2 to the connection pad 3.
And acts as a conductive connection member for electrically connecting the first and second members.
【００１９】前記異方性導電膜４は、図２に示す如く、
銀、銅、金、ニッケル、錫、鉛またはこれらの合金等の
金属や、これらの金属を表面に被着させたポリスチレン
等の有機樹脂から成る導電粒子（平均径が１〜１０μｍ
程度）４ａを、厚さ１５〜３０μｍのエポキシ樹脂等の
熱硬化性樹脂、ポリエチレン樹脂等の熱可塑性樹脂、ア
クリル系樹脂等の光硬化性樹脂等から成る樹脂フィルム
４ｂ中に分散させた構造を有し、前記樹脂フィルム４ｂ
が半導体素子２を搭載部１ａに接合させる接着剤として
作用するとともに、前記導電粒子４ａが半導体素子の電
極２ａを接続パッド３に接続させる導電性部材として作
用する。The anisotropic conductive film 4 is, as shown in FIG.
Conductive particles made of a metal such as silver, copper, gold, nickel, tin, lead or an alloy thereof, or an organic resin such as polystyrene having these metals adhered to the surface (the average diameter is 1 to 10 μm
A) A structure in which 4a is dispersed in a resin film 4b made of a thermosetting resin such as an epoxy resin having a thickness of 15 to 30 μm, a thermoplastic resin such as a polyethylene resin, a photocurable resin such as an acrylic resin, or the like. Having the resin film 4b
Functions as an adhesive for bonding the semiconductor element 2 to the mounting portion 1a, and the conductive particles 4a function as a conductive member for connecting the electrode 2a of the semiconductor element to the connection pad 3.
【００２０】前記異方性導電膜４による搭載部１ａへの
半導体素子２の実装は、例えば、絶縁基体１の搭載部１
ａ上に半導体素子２を、間に異方性導電膜４を挟み、搭
載部１ａ表面の複数の接続パッド３と半導体素子５の電
極とを上下に位置合わせして載せ、次に、これらの半導
体素子２、異方性導電膜４および絶縁基体１に上下に約
５０〜１５０ｇ／ｍｍ２の荷重で加圧するとともに加熱
することにより行われ、接続パッド３と電極２ａとの間
に多数の導電粒子を捕捉、保持させるとともにこれを加
圧して適度に扁平化させて広接触面積で挟ませることに
より両者が低電気抵抗で電気的に接続されることとな
り、同時に樹脂フィルム４ｂを熱硬化させることにより
導電粒子４ａの位置が固定されるとともに絶縁基体１と
半導体素子２とが接合されることとなる。The mounting of the semiconductor element 2 on the mounting portion 1 a by the anisotropic conductive film 4 is performed, for example, by mounting the insulating portion 1 on the mounting portion 1 a.
a, the plurality of connection pads 3 on the surface of the mounting portion 1a and the electrodes of the semiconductor element 5 are placed on top of each other with the anisotropic conductive film 4 interposed therebetween. This is performed by pressing and heating the semiconductor element 2, the anisotropic conductive film 4, and the insulating substrate 1 up and down with a load of about 50 to 150 g / mm 2, and a large number of conductive particles between the connection pad 3 and the electrode 2a. By capturing and holding the resin and pressurizing it to make it appropriately flat and sandwiching it with a wide contact area, the two are electrically connected with low electric resistance, and at the same time, the resin film 4b is thermally cured. The position of the conductive particles 4a is fixed, and the insulating base 1 and the semiconductor element 2 are joined.
【００２１】この場合、前記複数の全接続パッド３上面
の平坦度が１５μｍを超えると、異方性導電膜６を圧縮
させる圧力が複数の接続部間でばらついてしまい、導電
粒子を挟む圧力がばらつき、導電粒子４ａと接続パッド
３または半導体素子の電極２ａとの接触面積がばらつい
て両者間の接触抵抗が複数の接続部間で大きくばらつく
こととなり、接続部の電気抵抗が所定の抵抗値からばら
ついて半導体素子を正確に作動させることができなくな
る。従って、前記全接続パッド３上面の平坦度は１５μ
ｍ以下に特定される。In this case, when the flatness of the upper surface of the plurality of connection pads 3 exceeds 15 μm, the pressure for compressing the anisotropic conductive film 6 varies between the plurality of connection portions, and the pressure for sandwiching the conductive particles is reduced. As a result, the contact area between the conductive particles 4a and the connection pads 3 or the electrodes 2a of the semiconductor element varies, and the contact resistance between the two greatly varies among a plurality of connection portions, and the electrical resistance of the connection portions increases from a predetermined resistance value. Variations make it impossible to operate the semiconductor element accurately. Therefore, the flatness of the upper surface of all the connection pads 3 is 15 μm.
m or less.
【００２２】また、前記接続パッド３は、その表面粗さ
の最大高さＲｙが異方性導電膜４中の導電粒子４ａの平
均径の１／２未満となると、導電粒子４ａの平均径（一
般に１〜１０μｍ）に比べ、これを捕捉、保持する接続
パッド３表面の谷部３ａの深さが浅くなりすぎ、導電粒
子４ａを捕捉、保持する作用が極めて低いものとなり、
半導体素子２を異方性導電膜４を用いて搭載部１ａ上に
実装する際、圧力による樹脂フィルム４ｂの変形にとも
なって多数の導電粒子４ａが接続パッド３と半導体素子
の電極２ａとの間から外れ、接続パッド３と電極２ａと
の間に介在する導電粒子が不足して両者の接触抵抗を高
くしてしまう。また、Ｒｙが１０μｍを超えて粗面とな
ると、異方性導電膜６中の導電粒子４ａの平均径に比べ
て接続パッド３表面の谷部３ａの深さが深くなりすぎ、
保持された導電粒子４ａの多数が谷部３ａ内に隠れてし
まい、導電粒子４ａを効果的に扁平化させて接続パッド
３と電極２ａとの接触面積を広いものとすることができ
ず、両者の接触抵抗を高くしてしまう。従って、前記接
続パッド３は、その表面粗さの最大高さＲｙを、異方性
導電膜４の導電粒子４ａの平均径に対し１／２以上乃至
１０μｍ以下の範囲としておく必要がある。When the maximum height Ry of the surface roughness of the connection pad 3 is less than half the average diameter of the conductive particles 4a in the anisotropic conductive film 4, the average diameter of the conductive particles 4a ( (Generally 1 to 10 μm), the depth of the valleys 3a on the surface of the connection pad 3 for capturing and holding this is too shallow, and the action of capturing and holding the conductive particles 4a is extremely low.
When the semiconductor element 2 is mounted on the mounting portion 1a using the anisotropic conductive film 4, a large number of conductive particles 4a are formed between the connection pad 3 and the electrode 2a of the semiconductor element due to deformation of the resin film 4b due to pressure. And the conductive particles interposed between the connection pad 3 and the electrode 2a are insufficient, and the contact resistance between them is increased. When Ry exceeds 10 μm and becomes rough, the depth of the valley 3 a on the surface of the connection pad 3 becomes too deep compared to the average diameter of the conductive particles 4 a in the anisotropic conductive film 6,
Many of the held conductive particles 4a are hidden in the valleys 3a, and the conductive particles 4a cannot be effectively flattened to increase the contact area between the connection pad 3 and the electrode 2a. Increase the contact resistance. Therefore, the connection pad 3 needs to have the maximum height Ry of the surface roughness in the range of not less than 乃至 to not more than 10 μm with respect to the average diameter of the conductive particles 4 a of the anisotropic conductive film 4.
【００２３】また前記接続パッド３は、例えば、焼成し
て絶縁基体１上に形成された後、この接続パッド３全部
の上面に平面研磨を施し、全接続パッド３上面の平坦度
を高くするとともにその表面を適度に粗くすることによ
り、全接続パッド３上面の平坦度を１５μｍ以下とする
とともに、各接続パッド３の表面粗さの最大高さＲｙを
異方性導電膜４の導電粒子４ａの平均径に対し１／２以
上乃至１０μｍ以下の範囲とすることができる。The connection pads 3 are, for example, formed on the insulating substrate 1 by firing, and thereafter, the upper surfaces of all the connection pads 3 are subjected to planar polishing to increase the flatness of the upper surfaces of all the connection pads 3. By appropriately roughening the surface, the flatness of the upper surface of all the connection pads 3 is reduced to 15 μm or less, and the maximum height Ry of the surface roughness of each connection pad 3 is reduced by the conductive particles 4 a of the anisotropic conductive film 4. It can be in the range of not less than 1/2 to not more than 10 μm with respect to the average diameter.
【００２４】なお、前記接続パッド３および配線導体５
は、その露出する表面にニッケル、金等の耐食性に優
れ、かつボンディング性、半田との濡れ性に優れる金属
をめっき法により１〜２０μｍの厚みに被着させておく
と、接続パッド３および配線導体５の酸化腐食を有効に
防止することができるとともに、配線導体５の外部電気
回路基板への接続を容易かつ確実なものとすることがで
きる。従って、前記配線導体５、及び接続パッド３は、
その露出する表面にニッケル、金等の耐食性に優れ、か
つボンディング性、半田との濡れ性に優れる金属をめっ
き法により１〜２０μｍの厚みに被着させておくことが
好ましい。The connection pad 3 and the wiring conductor 5
When a metal having excellent corrosion resistance such as nickel and gold, and excellent in bonding property and wettability with solder is applied to the exposed surface to a thickness of 1 to 20 μm by plating, the connection pad 3 and the wiring Oxidation and corrosion of the conductor 5 can be effectively prevented, and the connection of the wiring conductor 5 to the external electric circuit board can be made easy and reliable. Therefore, the wiring conductor 5 and the connection pad 3
It is preferable that a metal having excellent corrosion resistance, such as nickel and gold, and having excellent bonding properties and wettability with solder is applied to the exposed surface to a thickness of 1 to 20 μm by plating.
【００２５】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能である。It should be noted that the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention.
【００２６】[0026]
【発明の効果】本発明の半導体装置によれば、半導体素
子の電極が異方性導電膜を介して接続される複数の全接
続パッド上面の平坦度を１５μｍ以下としたことから、
実装時に各接続部間での異方性導電膜の加圧を均等に行
わせることができ、導電粒子を均一に加圧し、各接続パ
ッドと半導体素子の電極との電気的な接続を各接続部間
でほぼ均等に行わせて抵抗値をばらつかせることを有効
に防ぐことができ、半導体素子を常に正確に作動させる
ことができる。According to the semiconductor device of the present invention, the flatness of the upper surface of the plurality of connection pads to which the electrodes of the semiconductor element are connected via the anisotropic conductive film is set to 15 μm or less.
During mounting, the anisotropic conductive film can be evenly pressed between the connection parts, the conductive particles can be pressed uniformly, and the electrical connection between each connection pad and the electrode of the semiconductor element can be made by each connection It is possible to effectively prevent the resistance value from being varied by performing the operations almost equally between the sections, and the semiconductor element can always be operated accurately.
【００２７】また、本発明の半導体装置によれば、各接
続パッドの表面粗さの最大高さＲｙを異方性導電膜の導
電粒子の平均径の１／２乃至１０μｍの範囲としたこと
から、導電粒子を接続パッド表面の谷部によって効果的
に捕捉、保持させることができるとともに、この導電粒
子を谷部から効果的に突出させることができ、接続パッ
ドと半導体素子の電極との間に多数の導電粒子を両者に
接触させて介在させることができ、両者の接触抵抗を低
いものとして電気特性に優れた半導体装置を得ることが
できる。Further, according to the semiconductor device of the present invention, the maximum height Ry of the surface roughness of each connection pad is set to a range of １ ／ to 10 μm of the average diameter of the conductive particles of the anisotropic conductive film. The conductive particles can be effectively captured and held by the valleys of the connection pad surface, and the conductive particles can be effectively projected from the valleys. A large number of conductive particles can be brought into contact with and interposed therebetween, and a semiconductor device having excellent electrical characteristics can be obtained with a low contact resistance between the two.
【図１】本発明の半導体装置の一実施例を示す断面図で
ある。FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.
【図２】図１に示す半導体装置の要部断面図である。FIG. 2 is a sectional view of a principal part of the semiconductor device shown in FIG. 1;
１・・・・絶縁基体 ２・・・・半導体素子 ２ａ・・・電極 ３・・・・接続パッド ４・・・・異方性導電膜 ４ａ・・・導電粒子 ４ｂ・・・樹脂フィルム ５・・・・配線導体 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Semiconductor element 2a ... Electrode 3 ... Connection pad 4 ... Anisotropic conductive film 4a ... Conductive particles 4b ... Resin film 5 ... ... Wiring conductors
Claims (1)
体と、下面に複数個の電極を有する半導体素子とから成
り、絶縁基体上に半導体素子を搭載するとともに各接続
パッドと各電極とを樹脂フィルム中に導電粒子を分散さ
せて成る異方性導電膜を介して接続した半導体装置であ
って、前記全接続パッド上面の平坦度を１５μｍ以下と
するとともに各接続パッドの表面粗さの最大高さ（Ｒ
ｙ）を異方性導電膜の導電粒子の平均径に対し１／２以
上乃至１０μｍ以下としたことを特徴とする半導体装
置。An insulating substrate having a plurality of connection pads on an upper surface; and a semiconductor element having a plurality of electrodes on a lower surface. The semiconductor element is mounted on the insulating substrate, and each connection pad and each electrode are connected to each other. A semiconductor device connected via an anisotropic conductive film formed by dispersing conductive particles in a resin film, wherein the flatness of the upper surface of all the connection pads is 15 μm or less, and the maximum surface roughness of each connection pad is Height (R
A semiconductor device, wherein y) is set to 以上 or more and 10 μm or less with respect to the average diameter of the conductive particles of the anisotropic conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30295199A JP2001127103A (en) | 1999-10-25 | 1999-10-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30295199A JP2001127103A (en) | 1999-10-25 | 1999-10-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001127103A true JP2001127103A (en) | 2001-05-11 |
Family
ID=17915123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30295199A Pending JP2001127103A (en) | 1999-10-25 | 1999-10-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001127103A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006245140A (en) * | 2005-03-01 | 2006-09-14 | Nissha Printing Co Ltd | Connection structure and method of connection of circuit terminal |
| US20090288697A1 (en) * | 2006-08-29 | 2009-11-26 | Hitachi Chemical Co., Ltd. | Conductive adhesive film and solar cell module |
| US20100147355A1 (en) * | 2006-10-10 | 2010-06-17 | Hitachi Chemical Company, Ltd. | Connected structure and method for manufacture thereof |
| JP2011055033A (en) * | 2009-08-31 | 2011-03-17 | Kyocera Kinseki Corp | Piezoelectric oscillator |
| JP2011055008A (en) * | 2005-11-10 | 2011-03-17 | Hitachi Chem Co Ltd | Connection structure and method of manufacturing the same |
-
1999
- 1999-10-25 JP JP30295199A patent/JP2001127103A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006245140A (en) * | 2005-03-01 | 2006-09-14 | Nissha Printing Co Ltd | Connection structure and method of connection of circuit terminal |
| JP2011055008A (en) * | 2005-11-10 | 2011-03-17 | Hitachi Chem Co Ltd | Connection structure and method of manufacturing the same |
| US20090288697A1 (en) * | 2006-08-29 | 2009-11-26 | Hitachi Chemical Co., Ltd. | Conductive adhesive film and solar cell module |
| US9173302B2 (en) * | 2006-08-29 | 2015-10-27 | Hitachi Chemical Company, Ltd. | Conductive adhesive film and solar cell module |
| US20100147355A1 (en) * | 2006-10-10 | 2010-06-17 | Hitachi Chemical Company, Ltd. | Connected structure and method for manufacture thereof |
| US9123835B2 (en) | 2006-10-10 | 2015-09-01 | Hitachi Chemical Company, Ltd. | Connected structure and method for manufacture thereof |
| US20160035925A1 (en) * | 2006-10-10 | 2016-02-04 | Hitachi Chemical Company, Ltd. | Connected structure and method for manufacture thereof |
| JP2011055033A (en) * | 2009-08-31 | 2011-03-17 | Kyocera Kinseki Corp | Piezoelectric oscillator |
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