JP2001126411A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit for easily performing locking and making unlocking hard once locking is performed. SOLUTION: A data clock extraction circuit 12 extracts clock signals from an input data stream DF and outputs them through a selector 13 to a phase comparator 17a. The phase comparator 17a compares the phases of the clock signals and feedback signals and outputs the result through an LPF 20a to a VCO 21. The output of the VCO 21 is inputted through a frequency divider circuit to the phase comparator 17a. A filter control circuit 26 is a circuit for automatically setting the filter constant of the LPF 20a, sets the filter constant for accelerating the response speed of the LPF 17a in the case that the input data stream DF and the fed-back clock signals are not synchronized and sets the filter constant for lowering the response speed of the LPF 20a in the case that they are synchronized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CD player,
The present invention relates to a PLL circuit suitable for use in a reproducing circuit for reproducing a digital output signal output from an LD player or the like into an analog signal.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a schematic configuration of a reproducing circuit of this kind. In FIG. 1, reference numeral 1 denotes a CD player, which converts digital tone data into serial data and outputs it. Reference numeral 2 denotes a buffer amplifier, which amplifies the output of the CD player 1 and outputs it as a serial tone data string DF. FIG. 5B shows a waveform of the data string DF. Assuming that the sampling frequency of the musical sound data is fs, the data string DF has a frequency of 128 f shown in FIG.
It is output from the CD player 1 at the timing of the s clock signal. One bit in the data string DF corresponds to two periods of the clock signal.

[0003] Reference numeral 3 denotes a digital audio interface receiver (hereinafter, referred to as DIR) which extracts a clock signal and data from an output data string DF of the buffer amplifier 2 and outputs the clock signal and data to a DAC (digital-analog converter) 4. Here, DIR3 has a frequency of 25
A PLL circuit generates and outputs three types of clock signals of a master clock MCK of 6 fs, a bit clock BCK having a frequency of 64 fs, and a word clock WCK having a frequency of fs, and outputs tone data at the timing of the bit clock BCK. I do. FIG. 6 shows the timing of each clock and data. The DAC 4 converts the data output from the DIR 3 into an analog signal and outputs the analog signal.

FIG. 7 shows a PL built in the DIR 3 described above.
FIG. 3 is a block diagram illustrating a configuration of an L circuit. In this figure, reference numeral 11 denotes an output data string D of the buffer amplifier 2 (FIG. 4).
F is an input terminal to which the data clock DF is applied.
Is input to The data / clock extracting circuit 12 extracts a clock signal having a frequency of 64 fs from the data string DF and outputs the clock signal to the selector 13, and also extracts musical tone data from the data string DF based on a 128 fs clock signal obtained at the output terminal 31. .

XI is a clock signal of 12.288 MHz, and is formed in an oscillation circuit (not shown) using a crystal oscillator. Reference numeral 14 denotes a frequency dividing circuit, which is a clock signal XI.
Is converted into a clock signal having a frequency of 1/4 (3.072 MHz), and is output to the selector 13.

Reference numeral 16 denotes an input detection circuit,
Whether the data string DF is applied to the input terminal 11
, And outputs a “1” signal to the selector 13 when it is applied, and outputs a “0” signal when it is not applied. The selector 13 is an input detection circuit 16
Is "1", the data clock extraction circuit 12
Is selected and output. When the output is "0", the frequency divider 14
Select the output and output.

Phase comparator (phase comparator) 17
Performs a phase comparison between the output of the selector 13 and a clock signal (frequency: 64 fs) obtained by dividing the clock signal having a frequency of 128 fs obtained at the output terminal 31 by 1/2 by the frequency dividing circuit 18 and comparing the result with the LPF (Low-pass filter) 20. The LPF 20 outputs only a low frequency component of the output of the phase comparator 17 to a VCO (voltage controlled oscillator) 21. The VCO 21 is an oscillator that oscillates at a frequency corresponding to the output voltage of the LPF 20, and its output clock signal (frequency: 512 fs) is
2.

The frequency dividing circuit 22 divides the frequency of the clock signal output from the VCO 21 by 、 and outputs it to the output terminal 30 and the frequency dividing circuit 23 as a clock signal having a frequency of 256 fs. The frequency dividing circuit 23 divides the output of the frequency dividing circuit 22 by １ ／ and outputs it to the output terminal 31 as a clock signal having a frequency of 128 fs, and also outputs the data clock extracting circuit 12 and the frequency dividing circuit 18 described above. . The frequency dividing circuit 18 divides the output of the frequency dividing circuit 23 by １ ／, and outputs the result to the phase comparator 17 and the output terminal 32.

In the PLL circuit having such a configuration, when the data string DF is applied to the input terminal 11, a "1" signal is output from the input detection circuit 16, whereby the data / clock extraction circuit 12 outputs The output clock signal (frequency: 64 fs) is supplied to the phase comparator 17 via the selector 13. As a result, the PLL circuit locks to the clock signal having the frequency of 64 fs, and all the clock signals output from the output terminals 30 to 32 are signals synchronized with the clock signal output from the data clock extraction circuit 12.

On the other hand, when the data string DF is not applied to the input terminal 11, a "0" signal is output from the input detection circuit 16, whereby the output (frequency:
64fs) is supplied to the phase comparator 17 via the selector 13. As a result, the PLL circuit operates at frequency 6
Lock to the 4 fs clock signal and output terminals 30 to
Each of the clock signals output from the clock 32 is a signal synchronized with the clock signal output from the frequency divider 14.

As described above, the PLL circuit shown in FIG.
When the data stream is output from the D player 1 (FIG. 4), the clock is locked (synchronized) with the clock signal extracted from the data stream, and when the data stream is not output, the clock is output from the internal crystal oscillation circuit. The clock signal XI oscillates while being locked.

[0012]

The ease of locking / unlocking of the PLL circuit depends on the feedback time constant of the circuit. Then, it is desirable that the PLL circuit used for the above-mentioned DIR3 or the like locks the input data string DF in a short time, and that once locked, the lock is not easily released. However, in the conventional PLL circuit, when the feedback time constant is reduced, the lock is easily performed, but the lock is easily released. When the feedback time constant is increased, the lock is not easily released, but there is a problem that the lock is hard to lock.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a PLL circuit which is easy to lock and which is hardly released once locked.

[0014]

In order to achieve the above object, according to the present invention, there is provided a phase comparator in which an input signal is applied to a first input terminal, and an output of the phase comparator. And a voltage-controlled oscillator oscillating at a frequency corresponding to the output voltage of the low-pass filter, and a signal synchronized with the output of the voltage-controlled oscillator is supplied to a second input terminal of the phase comparator. In the PLL circuit applied to the control circuit, a signal synchronized with the output of the voltage controlled oscillator and a detection means for detecting whether or not the input signal is synchronized, and a detection result of the detection means is synchronized. If it is not, the response speed of the low-pass filter is set to be faster, and if the detection result of the detection means is synchronized, the response speed of the low-pass filter is increased. In which by comprising and a filter control means for setting the Kunar filter constant.

The invention described in claim 2 is the first invention.
Wherein the low-pass filter is an integration circuit including a resistor and a capacitor, and the filter control means sets a charge / discharge current of the capacitor. According to a third aspect of the present invention, in the PLL circuit according to the first aspect, the low-pass filter is an integrating circuit including a resistor and a capacitor, and the filter control means sets a time constant of the integrating circuit. It is characterized by the following. According to a fourth aspect of the present invention, in the PLL circuit according to the first aspect, the low-pass filter is an integrating circuit including a resistor and a capacitor, and the filter control means controls a charge / discharge current of the capacitor and the integration. It is characterized in that each time constant of the circuit is set.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention. In this figure, 11 is a terminal to which a data train DF output from a CD player or the like is applied, and 12 is a data / clock extracting circuit. The data clock extraction circuit 12 extracts a clock signal and data having a frequency of 64 fs from the data string DF, and extracts a preamble detection signal LOCK.
Is output. This preamble detection signal LOCK is
When each data of the data string DF is synchronized with the clock signal (128 fs) for data extraction, in other words, P
This signal is detected when the LL circuit is locked, and is not detected when the LL circuit is not locked. That is, the preamble signal existing in the data string DF can be detected only when synchronization is achieved, and the preamble detection signal LOCK is output when the preamble signal is detected.

Reference numeral 18 denotes a 1/2 frequency dividing circuit. 27-29
Are frequency-dividing circuits for dividing the frequency of the clock signal XI having a frequency of 24.576 MHz by 1 / 1.5, 1/3 and 1/6. Reference numeral 15 denotes a selector for selecting and outputting one of the outputs of the above-described frequency dividing circuits 27 to 29 based on signals SA to SC described later. Reference numeral 16 denotes an input detection circuit for detecting whether or not a data string is applied to the input terminal 11, and its output is supplied to an AND gate 96 via a delay circuit 95.
Supplied to Reference numeral 94 denotes an input change detection circuit, which is the preamble detection signal LOCK or the signals SA to SC described above.
A pulse signal is output when any of these changes.

Next, the phase comparator 17a, LP
The details of the F20a and the VCO 21 are shown in FIG. In the phase comparator 17a shown in this figure, reference numeral 40 denotes a phase comparator, and a PULLUP output signal 40a of the phase comparator 40 is applied to one input terminal of NAND gates 43 to 45 via an inverter 41 and a NAND gate 42. , PULLDOWN output signal 40b is supplied to NOR gate 46.
Is applied to one of the input terminals of the NOR gates 47 to 49.

The NAND gates 43 to 45 and NOR gates 47 to 49 are gates that are opened / closed by signals at terminals 51 to 53, respectively.
When a signal of "0" is applied, the PULLUP signal 40a
And PULLDOWN signal 40b are respectively gate 43,
47 is output to the LPF 20a and to the terminals 51 to 53 "
When the signal "0,1,0" is applied, the pullup signal 40a and the pulldown signal 40b are output from the gates 44,48 to the LPF 20a, respectively, and the signal "0,0,1" is sent to the terminals 51-53. When applied,
PULLUP signal 40a and PULLDOWN signal 4
0b is output from the gates 45 and 49 to the LPF 20a. A control signal is supplied to the terminals 51 to 53 from the filter control circuit 26 (FIG. 1) via the terminal 26.

The LPF 20a comprises a current controller 51 and a CR circuit 52. In the current control unit 51, 5
3 is a constant current source and 54 is a buffer FET. FET5
5, 56 and FETs 58, 59 (or FETs 60, 61).
Alternatively, the FETs 62 and 63) constitute a current mirror circuit. The FETs 64 to 66 are analog switches, and are ON / OFF controlled by the outputs of the NAND gates 43 to 45 described above. Also, the FETs 67 to 69 are analog switches, and the NOR gates 47 to 49 described above.
Is turned on / off by the output of.

Next, in the CR circuit 52, 70 to 76
Is a switch, 80 to 85 are serially connected resistors, 8
6 is an external capacitor. And the switch 70
Are controlled on / off by a control signal supplied from the filter control circuit 26 via the terminal 26b.

In such a configuration, the time constant of the CR circuit 52 is controlled by the on / off state of the switches 70 to 76, in other words, by the control signal applied to the terminal 26. The charge / discharge current of the CR circuit 52 is controlled by the on / off state of the switches 64 to 69, in other words, by the control signal applied to the terminal 26a. That is, the LPF 20a is connected to the terminals 26a, 26b
The filter characteristics can be variously changed by the control signal applied to the filter.

Next, in the VCO 21, 88 is an LPF.
A buffer amplifier that amplifies the output of 20a, 91 is a ring oscillator, 90 is a current control circuit that controls the current of the ring oscillator 91,
Is controlled according to the output of the LPF 20a.

Next, in FIG. 1, the filter control circuit 26 is a circuit for outputting a control signal for controlling the filter characteristic of the LPF 20a,
A set of control signals is stored. One set is a control signal having a small feedback time constant of the PLL circuit, in other words, a control signal having a fast response, and the other set is a control signal having a large feedback time constant, that is, a control signal having a slow response. When the preamble detection signal LOCK is not output from the data clock extraction circuit 12, that is, when the PLL circuit is not locked, the filter control circuit 26 sends a control signal having a small feedback time constant to the terminals 26a and 26b. When the preamble detection signal LOCK is output, that is, when the PLL circuit is locked, a control signal that increases the feedback time constant is supplied to the terminals 26a and 26b.
Output to

The PLL circuit has a small feedback time constant and is easily locked when the response is fast, but is easily released at the same time, has a large feedback time constant and is hard to be locked when the response is slow, but is not easily released. Therefore, according to the above configuration, P is easily locked and hardly disengaged.
It can be an LL circuit.

Next, in FIG. 1, reference numerals 34, 35 and 36 denote a 1/2 frequency dividing circuit, a 1/4 frequency dividing circuit and a 1/8 frequency dividing circuit, respectively. A selector 37 selects and outputs one of the outputs of the frequency dividers 34 to 36 based on the output signals SA to SC of the range counter 38, and 39 is a 1/2 frequency divider. The range counter 38 determines the interval between the preamble signals existing in the data string DF by the clock signal XI (24.5).
76 MHz) to obtain a data string D
Determine the frequency of F. When the frequency of the data string DF is 12.288 MHz = 192 KHz × 64, the control signal SA is output. When the frequency is 6.144 MHz = 96 KHz × 64, the control signal SB is output. If 072 MHz = 48 KHz × 64 or “0” (no input),
Outputs control signal SC.

Reference numeral 97 denotes a phase synchronization detection circuit, which outputs a pulse signal when the PLL loop is synchronized with the clock signal XI. With the configuration described above, the sampling frequency of the input data sequence DF is 48 kHz, 96 kHz, 192 kHz.
In any case, the fluctuation range of the oscillation frequency of the VCO 21 is 13
1.07 MHz to 98.3 MHz.
Hereinafter, the relationship between the sampling frequency and the oscillation frequency of the VCO 21 will be described in detail.

First, when the input data string DF is 0 (no input), the range counter 38 outputs a signal SC. Thus, the selector 15 selects the output of the ６ frequency divider 29 and the selector 37 selects the output of the ８ frequency divider 36. 1/6 frequency dividing circuit 29 by selector 15
Is selected, a clock signal of 24.576 / 6 = 4.096 MHz is applied to the input terminal A of the selector 13 via the selector 15.

At this time, the output of the flip-flop 98 is "
0 ", so that the output of AND gate 96 is also"
0 ", and the selector 13 outputs the 4.096 MHz clock signal output from the selector 15 to the phase comparator 17a. As a result, the PLL loop locks to the 4.096 MHz clock signal,
Therefore, the oscillation frequency of the VCO 21 is 4.096 × 2 × 2 × 8 = 131.072 MHz. (The above 2, 2, and 8 are frequency dividing circuits 18, 39, 36
Is the frequency division ratio. )

On the other hand, the phase synchronization detection circuit 97 outputs a pulse signal when the PLL loop is synchronized with the clock signal XI. As a result, the flip-flop 98 is set, and the AND gate 96 is opened. However, at this time, the output of the input detection circuit 16 is "0", and therefore, the output of the AND gate 96 also continues to be "0".
No change occurs in the lock state of the LL loop.

Next, assuming that a data string DF (frequency: 192 × 64 = 12.288 MHz) based on a tone signal having a sampling frequency of 192 KHz is applied to the input terminal 11.
Range counter 38 outputs signal SA. Thus, the selector 15 selects the output of the 1/2 frequency dividing circuit 27, and the selector 37 selects the output of the 1/2 frequency dividing circuit 34. When the selector 15 selects the output of the frequency divider 27, the frequency 16.3 output from the frequency divider 27 is selected.
An 8 MHz clock signal is output from the selector 15,
The signal is applied to the input terminal A of the selector 13.

At this time, the input change detection circuit 94 detects a change in the signal SA and outputs a pulse signal to the flip-flop 98. As a result, the flip-flop 94 is reset, so that the AND gate 96 is closed, and “0” is supplied to the selection terminal SB of the selector 13. As a result, the output of the selector 15 of 16.38M
The clock signal of Hz is output to the phase comparator 17a via the selector 13. As a result, the PLL loop locks to the clock signal of 16.38 MHz, and the oscillation frequency of the VCO 21 becomes 16.384 × 2 × 2 × 2 = 131.072 MHz.

The phase synchronization detection circuit 97 outputs a pulse signal when the PLL loop is synchronized with the clock signal XI, as in the case described above. As a result, the flip-flop 98 is set, and the AND gate 96 is opened. At this time, the output of the input detection circuit 16 is "1", so that the output of the AND gate 96 is "1", and the selector 13 selects and outputs the output of the data / clock extraction circuit 12. Here, the output of the data / clock extraction circuit 12 is the one extracted from the data sequence DF.
2.288 MHz clock signal,
Thereafter, the PLL loop locks to this clock signal and
The oscillation frequency of CO21 is 12.288 × 2 × 2 × 2 = 98.304 MHz. That is, the oscillation frequency of the VCO 21 changes from 131.072 MHz to 98.304 MHz when locking to the clock signal extracted from the data string DF.

Next, a data string DF (frequency:
When 96 × 64 = 6.144 MHz) is applied, the range counter 38 outputs a signal SB. Thereby, the selector 1
5 selects the output of the 1/3 frequency dividing circuit 28, and the selector 37 selects the output of the 1/4 frequency dividing circuit 35. When the selector 15 selects the output of the frequency dividing circuit 28, a clock signal having a frequency of 8.19 MHz output from the frequency dividing circuit 28 is output from the selector 15 and applied to the input terminal A of the selector 13.

On the other hand, at this time, the input change detection circuit 94 detects a change in the signal SB, and outputs a pulse signal to the flip-flop 98. As a result, the flip-flop 94 is reset, the AND gate 96 is closed, and “0” is supplied to the selection terminal SB of the selector 13. As a result, the 16.38 MHz clock signal output from the selector 15 is output to the phase comparator 17a via the selector 13, and the PLL loop is connected to the 16.38M clock.
Hz clock signal and therefore VCO2
The oscillation frequency of No. 1 is 8.192 × 2 × 2 × 4 = 131.072 MHz.

The phase synchronization detection circuit 97 outputs a pulse signal when the PLL loop is synchronized with the clock signal XI. As a result, the flip-flop 98 is set, and the AND gate 96 is opened. At this time, the output of the input detection circuit 16 is "1", so that the output of the AND gate 96 is "1", and the selector 13 selects and outputs the output of the data / clock extraction circuit 12. Here, the output of the data clock extraction circuit 12 is
This is a 6.144 MHz clock signal extracted from the data string DF. Therefore, thereafter, the PLL loop locks to this clock signal, and the oscillation frequency of the VCO 21 is 6.144 × 2 × 2 × 4 = 98.304 MHz. Become. That is, the oscillation frequency of the VCO 21 changes from 131.072 MHz to 9% when locked to the clock signal extracted from the data string DF, as in the case described above.
It changes to 8.304 MHz.

Next, a data string DF (frequency:
When 48 × 64 = 3.072 MHz) is applied, the range counter 38 outputs a signal SC. Thereby, the selector 1
5 selects the output of the 1/6 frequency dividing circuit 29, and the selector 37 selects the output of the 1/8 frequency dividing circuit 36. As a result, the PLL loop locks to the 4.096 MHz clock signal, and the oscillation frequency of the VCO 21 becomes 4.096 × 2 × 2 × 8 = 131.072 MHz.

Next, the phase synchronization detection circuit 97
When a pulse signal is output when the loop is synchronized with the clock signal XI, the flip-flop 98 is set.
At this time, the output of the input detection circuit 16 is "1", so that the output of the AND gate 96 is "1", and the selector 13 selects and outputs the output of the data / clock extraction circuit 12. Here, the data clock extraction circuit 12
Is 3.072 MH extracted from the data sequence DF.
Therefore, the PLL loop locks to this clock signal, and the oscillation frequency of the VCO 21 becomes 3.072 × 2 × 2 × 8 = 98.304 MHz. That is, the oscillation frequency of the VCO 21 changes from 131.072 MHz to 9% when locked to the clock signal extracted from the data string DF, as in the case described above.
It changes to 8.304 MHz.

Next, when the data string DF returns to 0, the range counter 38 outputs the signal SC in the same manner as described above.
Is locked to the 4.096 MHz clock signal output from. Next, a pulse signal is output from the phase synchronization detection circuit 97, the flip-flop 98 is set, and the AND gate 96 is opened. At this time, the output of the input detection circuit 16 is "0". The output of the gate 96 keeps "0", and the PLL loop
Wait for the next input in synchronization with the output of 7.

FIG. 3 shows the output voltage V and VCO of the LPF 20a.
It is a figure which shows the relationship with the oscillation frequency of 21. (A) When a sampling frequency is 192 KHz, (B) is 96
In the case of KHz, (c) is the case of 48 KHz. As is clear from this figure, according to the above-described PLL circuit, the oscillation frequency width of the VCO 21 is 131.07 MHz or more.
By changing only in the range of 98.3 MHz, it is possible to correspond to an input data string ranging from the sampling frequency of 192 KHz to 48 KHz. As is clear from the above description, when the frequency of the data string DF changes, the PLL circuit first has the highest oscillation frequency of the VCO 21 of 131.07 MHz, and then shifts to the lower frequency of 98.3 MHz. And locked. In other words, since the lock always shifts to a lower frequency, it is possible to solve the problem that the lock is hardly obtained.

[0041]

As described above, according to the present invention, the detecting means for detecting whether or not the input signal is synchronized and the detection result of the detecting means are not synchronized. A filter constant for setting a filter constant at which the response speed of the low-pass filter increases, and setting a filter constant at which a response speed of the low-pass filter decreases when the detection result of the detection means is synchronized. With the provision of the means, it is possible to provide a PLL circuit which can be easily locked and which is hard to be released once locked.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 shows a phase comparator 1 according to the embodiment.
FIG. 7A is a circuit diagram illustrating details of an LPF 20a and a VCO 21;

FIG. 3 is a graph for explaining the operation of the embodiment.

FIG. 4 is a block diagram schematically showing a reproduction circuit of a CD player.

FIG. 5 is a timing chart for explaining an output of the CD player 1 in FIG. 4;

FIG. 6 is a timing chart of a clock signal and data output from DIR3 in FIG. 4;

FIG. 7 is a block diagram illustrating a configuration of a conventional PLL circuit.

[Explanation of symbols]

11 input terminal, 12 data clock extraction circuit, 1
7a: Phase comparator, 20a: LPF, 21 ...
VCO, 26a, 26b terminal, 43-45 NAND gate, 47-49 NOR gate, 51-53 terminal. 5
4-63: FET, 64-69: Analog switch, 7
0 to 76: switch, 80 to 85: resistor, 86 capacitor.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shoji Yasui 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha Corporation (72) Inventor Toru Shirayanagi 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha Corporation ( 72) Inventor Kiyoshi Ishijima 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka F-term in Yamaha Corporation (reference) 5D044 AB05 BC03 CC04 GM12 GM14 GM15 GM18 5J106 AA04 BB04 CC01 CC21 CC38 CC41 CC52 DD02 DD09 DD43 DD48 EE08 GG07 HH10KK

Claims (4)

[Claims] 1. A phase comparator to which an input signal is applied to a first input terminal, a low-pass filter to which an output of the phase comparator is input, and a voltage oscillating at a frequency according to an output voltage of the low-pass filter. A PLL synchronized with an output of the voltage controlled oscillator, wherein a signal synchronized with an output of the voltage controlled oscillator is applied to a second input terminal of the phase comparator. Detecting means for detecting whether or not synchronization with a signal is obtained, and setting a filter constant by which the response speed of the low-pass filter is increased when the detection result of the detecting means is not synchronized, Filter control means for setting a filter constant that reduces the response speed of the low-pass filter when the detection result of the detection means is synchronized. PLL circuit composed of Te. 2. The PLL circuit according to claim 1, wherein said low-pass filter is an integration circuit including a resistor and a capacitor, and said filter control means sets a charge / discharge current of said capacitor. 3. The PLL circuit according to claim 1, wherein said low-pass filter is an integration circuit including a resistor and a capacitor, and said filter control means sets a time constant of said integration circuit. 4. The low-pass filter is an integration circuit including a resistor and a capacitor, and the filter control means sets a charge / discharge current of the capacitor and a time constant of the integration circuit, respectively. 3. The PLL circuit according to 1.