JP2001125802A - Emulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an emulator for easily emulating both a system LSI and the test board of the system LSI. SOLUTION: This emulator is provided with a CPU evaluating chip 2, ROM 3 and 4, a host communication connector I/F 18, a control processor 6, an RAM 5, a control part 7, a trace memory 8, an LED 9, a uni-directional input/output I/F connector 13, a three-state bus I/F connector 14, buses 19 and 20, a switching circuit 12 for connecting the bus 20 with either the uni-directional input/output I/F connector 13 or the three-state bus I/F connector 14, a CPU clock signal line 21, a connector selection signal generating part 10 for generating a connector selection signal, and a connector selection signal input terminal 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a system LSI.
(Large Scale Integrated circuit)
(InCircuit Emulator) and other emulators.
In particular, the present invention relates to an emulator that can evaluate both a system LSI and a test board of the system LSI.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and high performance of computer systems and the like, LSI (Large Scale) has been developed.
The degree of integration of an integrated circuit has also been improved, and each chip such as a microprocessor, a memory, and an input / output (I / O) interface has been mounted on a one-chip LSI as a system LSI.

FIG. 8 is a diagram showing a configuration of a general system LSI. In FIG. 8, this system LSI
A microprocessor 81 for executing and controlling each program (logic), and a ROM for storing control programs and the like
(Read Only Memory) 83 and RAM for storing data
(Random Access Memory) 84 and user logic 85
, Analog logic 86, microprocessor 81
A bus 87 connecting between the microprocessor 81 and the gate circuit 82; a bus 88 provided between the microprocessor 81 and the gate circuit 82; An input / output signal terminal 89 for transmitting and receiving signals between the processor 81 and the outside of the system LSI is provided.

In evaluating such a system LSI, the microprocessor 81 and the gate circuit 82 are separated from each other, and an ICE (InCirc) for evaluating the system LSI is used.
uit Emulator) and the input / output signal terminal 89 were connected and evaluated.

At this time, the input / output signal terminal 89 of the system LSI connected to the target board is generally
There are many types of bidirectional three-state buses (3 State-Bus) (hereinafter, also simply referred to as “bidirectional three-state type”).

[0006]

Here, when evaluating a system LSI as shown in FIG. 8 and a program incorporated in the system LSI, the system LSI
It is better to create a breadboard with the same function as the system LSI before connecting it to the target board, and to connect this breadboard to the target board for evaluation, so that the development time is brought forward and debugging Efficiency is also increased. C in this breadboard
Digital circuits such as a PU (Central Processing Unit) and user logic are often configured on a gate array or cell basis, and the CPU core in this case is supplied as a macro cell.

At this time, each pin of a macro cell chip (hereinafter, also simply referred to as a “CPU core chip”), which is a CPU core formed on a breadboard or the like, has two-way pins due to design verification of user logic and restrictions on simulation. Instead of a state type, a unidirectional bus type separated into an input side and an output side is used.

However, according to a conventional emulator such as an ICE, since a terminal for connecting a target to be evaluated is of a bidirectional three-state type, a desired system LSI function is created as a breadboard, and In the case of evaluation (emulation), there is a problem that the breadboard and the ICE cannot be directly connected.

Further, in order to connect the breadboard and the ICE, it is necessary to separately provide a connection interface or the like, and there has been a problem that it takes much time and effort.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to simply provide both a system LSI and a system LSI test board without special consideration of the interface of a connector to be evaluated. Is to provide an emulator that can emulate the program.

[0011]

In order to solve the above problems, an emulator according to the present invention is an emulator for evaluating a system LSI and a test board of the system LSI, and evaluates the functions of the system LSI and a test board of the system LSI. Evaluation means for performing the evaluation, system LSI connection means for connecting the evaluation means and the system LSI to be evaluated,
Test board connecting means for connecting the evaluation means to the test board of the system LSI to be evaluated; and switch means for connecting either the system LSI connection means or the test board connection means to the evaluation means. Features.

At this time, the system LSI connection means may be a bidirectional input / output interface, and the test board connection means may be a unidirectional input / output interface.

By having two input / output interfaces, bidirectional and unidirectional, it is possible to easily evaluate both the system LSI and the test board of the system LSI without special consideration of the interface of the connector to be evaluated. Can be.

In the above emulator, the switch means includes a pull-up resistor and a switch for connecting a circuit including the pull-up resistor to the ground, and a selection signal generated in accordance with ON / OFF of the switch. Based on the above, one of the system LSI connection means and the test board connection means can be connected to the evaluation means, or the switch means comprises a pull-up resistor and a pull-down resistor, and the system LSI connection Based on a selection signal generated when one of the pull-up resistor and the pull-down resistor is connected by a terminal connected to either the test means or the test board connection means, or a system LSI connection means or a test to which the terminal is connected. One of the board connection means can be connected to the evaluation means. Furthermore, NA switching means includes an address decoder, coupled to the address decoder
An ND circuit and a register connected to the NAND circuit may be provided, and either the system LSI connection means or the test board connection means may be connected to the evaluation means based on the data held in the register. it can.
In this case, the switch means may determine data to be held in the register according to a control signal and an address signal from an internal control processor or an externally provided computer system.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an emulator for a system LIS according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an IC which is an emulator of the present invention.
It is a figure showing the example of composition of E (InCircuit Emulator). This ICE1 is connected to a system LSI (not shown)
And a CPU (Central Processing Uniform) that evaluates an evaluation breadboard (not shown) before trial production of a system LSI.
t) an evaluation chip 2; a ROM (Read Only Memory) 3 for storing a control program of the CPU evaluation chip 2;
Host computer such as RS-232C (not shown)
A host communication connector I / F (interface) 18 for connecting to the control processor 6 for controlling each component according to a control signal from the host computer
A ROM 4 for storing a control program of the control processor 6 and the like; a RAM connected to the CPU evaluation chip 2 and the control processor 6 for storing data
(Random Access Memory) 5, a control unit 7 for performing trace control, instruction break control, bus break control, timer counting, and the like when evaluating a system LSI or the like, and a trace memory connected to the control unit 7 and storing trace data. 8 and an LED (Light Em
itting Diode 9, a unidirectional input / output I / F connector 13 for inputting / outputting a signal in one direction to / from the device under evaluation, and a three-state bus (State- Bus) an I / F connector 14, a bus 20 for connecting the CPU evaluation chip 2 to each component, a bus 19 for connecting the control processor 6 to each component, and a bus 20
A switching circuit 12 for connecting either one of the unidirectional input / output I / F connector 13 and the three-state bus I / F connector 14, and a CPU connected to the switching circuit 12.
A CPU clock signal line 21 for supplying a CPU clock signal (CPUCLK) to the evaluation chip, and a connector selection signal for selecting one of the unidirectional input / output I / F connector 13 and the three-state bus I / F connector 14 And a connector selection signal input terminal 11 for inputting a connector selection signal from the connector selection signal generation unit 10 to the switching circuit 12.
And

Here, the bus 20 is connected to the switching circuit 1
2, a plurality of input signal lines 20a for input signals (only one is shown in FIG. 1) and a plurality of output signal lines 20b for output signals (only one is shown in FIG. 1) ) And a control signal line 20c for a data bus status signal.

The switching circuit 12 operates in response to a connector selection signal, and connects the CPU clock signal line 21 and the bus 20 to either the unidirectional input / output I / F connector 13 or the three-state bus I / F connector 14. A transmission gate circuit 15 for connecting to one of the
A buffer circuit 16 for an input signal line 20a connected to a three-state bus I / F connector 14;
And a clocked gate buffer circuit 17 for the output signal line 20b connected to the / F connector 14.

Thus, the switching circuit 12 sets the CPU clock signal line 21 and the bus 20 to the high level based on the connector selection signal from the connector selection signal generator 10, for example, the high level signal or the low level signal. , And to the unidirectional input / output I / F connector 13 when the signal is low, and to the three-state bus I / F
Connect to F connector 14.

FIG. 2 is a diagram showing an example of the configuration of the connector selection signal generator 10. In FIG. 2, the connector selection signal generator 10 includes a pull-up resistor 22 connected to the power supply VDD, and a dedicated switch C23 for grounding the pull-up resistor 22 to ground (GND). However,
In this case, the connector selection signal generator 10 has no connection with the bus 20.

In such a connector selection signal generator 10, a low level signal is output as a connector selection signal by turning on the dedicated switch C23. By turning off the dedicated switch C23, a high-level signal is output as a connector selection signal.

FIG. 3 is a diagram showing another example of the configuration of the connector selection signal generator 10. As shown in FIG. In FIG. 3, the connector selection signal generation unit 10 includes a pull-up resistor 31 connected to the power supply VDD, a dedicated switch D32 connecting the pull-up resistor 31 to the connector selection signal input terminal 11, and a ground (GND). And a dedicated switch E34 for connecting the pull-down resistor 33 to the connector selection signal input terminal 11. However, in this case, the connector selection signal generator 10 has no connection with the bus 20.

In such a connector selection signal generation section 10, an IC is connected to the unidirectional input / output I / F connector 13.
When the E connector cable (not shown) is connected,
The exclusive switch D32 is turned ON, and a high-level signal is output to the connector selection signal input terminal 11 as a connector selection signal. On the other hand, a three-state bus I / F connector 1
When the ICE-probe connection connector cable (not shown) is connected to 4, the dedicated switch E34 is turned ON, and a low-level signal is output to the connector selection signal input terminal 11 as a connector selection signal. However, in this case, the cables should not be inserted into both the unidirectional input / output I / F connector 13 and the three-state bus I / F connector 14 at the same time.

FIG. 4 is a diagram showing another example of the configuration of the connector selection signal generator 10. In FIG. 4, the connector selection signal generator 10 receives an address decoder 41 to which a read address signal is input, an address decoder 42 to which an initial data set address signal is input, and a write address signal. Address decoder 43
And the address (ADR2) from the address decoder 41
And a read control signal (RD). As a result, a NAND circuit 44 for outputting data in the register to the clocked gate buffer circuit 17, an address (ADR2) from the address decoder 42 and a write control signal (WR) are input. The NAND circuit 45 outputs the result as an initial data set signal, and the NAND which receives the address (ADR1) and the write control signal (WR) from the address decoder 43 and outputs the result as a data write signal.
Data is input from the circuit 46 and the output signal line 20b,
A register 47 for outputting a connector selection signal based on the data.

In the connector selection signal generator 10 as shown in FIG. 4, a host computer (not shown)
The user sets which of the unidirectional input / output I / F connector 13 and the three-state bus I / F connector 14 to use, and data corresponding to the setting is written in the register 47. A connector selection signal is output from the register 47 based on this data.

For example, when the unidirectional input / output I / F connector 13 is selected, the control processor 6 of the ICE sets the least significant bit of the address (ADR1) to “1”.
Write. Also, a three-state bus I / F connector 14
Is selected, the ICE control processor 6
Writes "0" to the least significant bit of the address (ADR1). Further, the register 47 is initialized by writing arbitrary data to the address (ADR2).

FIG. 5 is a flowchart showing a method of controlling the connector selection signal in the connector selection signal generator 10 shown in FIG.

In FIG. 5, first, a host computer (not shown) analyzes a command input from a user or the like, and determines whether the command is a command for reading data in the register 47 of the ICE1 or a command for reading the data in the register 47 of the ICE1. Is a command to write data to When the input command is the register read command, the setting monitor of the connector is selected. On the other hand, if the input command is a register write command,
, A command to select the unidirectional input / output I / F connector 13, or a command to select the three-state bus I / F connector 14 (step 501).

Next, the host computer proceeds to step 5
01, the command packet is sent to ICE1.
(Step 502).

On the ICE1 side, the host communication connector I /
The control processor 6 receives the command packet via F18 and analyzes the command packet (step 503).

If the command packet is a register read, the register 47 of the connector selection signal generator 10
Is read. On the other hand, when the command packet is a register write command for initializing the register 47, for example, the control processor 6 writes the address data (ADR2) into the register 47 as the predetermined data as described above. When the command packet is a register write command for selecting the unidirectional input / output I / F connector 13, for example, as described above, the least significant bit of the address data (ADR1) is set to “1” and the register 47 is set. And the data is read from the register 47. Alternatively, when the command packet is a register write command for selecting the three-state bus I / F connector 14, for example, as described above, the least significant bit of the address data (ADR1) is set to “0”.
Is written to the register 47, and the data is read from the register 47 (step 504).

Next, the control processor 6 sends the read result of the register 47 to the host communication connector I / F1.
The packet is issued as a result packet to the host computer through the step 8 (step 505).

The host computer receives the result packet from ICE1 and analyzes the contents (step 506).

Finally, the result of the analysis is displayed on a display device or the like as a result of reading the register 47 of the ICE 1 (step 507). The user can check the display result and determine whether the connector selected in ICE1 is correct.

Thus, in the connector selection signal generator 10 as shown in FIG. 4, the connector is set by the host computer (not shown), and the data corresponding to the setting is written into the register 47. A connector selection signal (a high-level “1” signal or a low-level “0” signal) is output from the register 47 based on the data of the register 47 (the value of the least significant bit of ADR1).

Next, a system L based on the ICE1 of the present invention will be described.
The emulation of the SI and the evaluation breadboard will be described.

FIG. 6 is a diagram showing a case where the evaluation breadboard before the trial production of the system LSI is emulated. In FIG. 6, ICE1 is a desired system LS
Emulate an evaluation breadboard 62 having the same function as I.

Here, the breadboard for evaluation 62 is
CE1 and a target board 64 on which a system LSI is finally mounted, and a driver for applying the CPU core chip 65, the memory chip 66, the user logic 67, the analog logic 68, and the user logic 67 on the target board 64 69 and a unidirectional input / output bus 70.

Here, the ICE 1 is connected to the host computer 61 via the host communication connector I / F 18 (FIG. 1).
It is connected to the. In addition, the unidirectional input / output I / F connector 13 is connected to the evaluation breadboard 62 via the ICE connector cable 63.

That is, C of evaluation breadboard 62
A terminal (unidirectional input / output I / F connector 1) of the emulator (ICE1) that substitutes for the macro of the PU core chip 65
3) has the same terminal structure as the macro of the CPU core chip 65. Therefore, when emulating this evaluation breadboard 62, there is no need to prepare a special connection interface between the ICE1 and the evaluation breadboard 62.

FIG. 7 is a diagram showing a case where the system LSI mounted on the target board 64 is emulated.

Here, the ICE 1 is connected to the host computer 61 via the host communication connector I / F 18 (FIG. 1).
It is connected to the. In addition, a bidirectional three-state bus I / O is connected via an ICE-probe connection connector cable 73.
The F connector 14 is connected to a system LSI 71 mounted on a target board 64. Here, the system LSI 71 and the ICE-probe connector cable 7
3 are connected by a probe jig 72.

That is, most of the terminals of the system LSI 71 mounted on the target board 64 have a bidirectional three-state bus terminal structure. Therefore, by using the ICE-probe connection connector cable 73, the system LSI 71 can be emulated.

The embodiment of the emulator of the present invention has been described above. As for the connector selection signal of the connector selection signal input terminal 11, a bidirectional connector is selected by a low-level connector selection signal, and a high-level connector is selected. A unidirectional connector may be selected by a selection signal.

[0045]

As described above, the emulator of the present invention has two input / output interfaces, bidirectional and unidirectional, so that the interface of the connector to be evaluated is not specially considered. It is now possible to easily emulate both the system LSI and the test board of the system LSI.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an embodiment of an emulator according to the present invention.

FIG. 2 is a schematic diagram showing a connector selection signal generator of an emulator according to the present invention.

FIG. 3 is a schematic diagram showing a connector selection signal generator of an emulator according to the present invention.

FIG. 4 is a schematic diagram showing a connector selection signal generator of an emulator according to the present invention.

FIG. 5 is a flowchart showing generation of a connector selection signal by a connector selection signal generation unit shown in FIG. 4;

FIG. 6 is a diagram showing emulation using an emulator according to the present invention.

FIG. 7 is a diagram showing emulation using an emulator according to the present invention.

FIG. 8 is a schematic diagram showing a configuration of a general system LSI.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ICE 2 CPU evaluation chip 3, 4, 83 ROM 5, 84 RAM 6 Control processor 7 Control part 8 Trace memory 9 LED 10 Connector selection signal generation part 11 Connector selection signal input terminal 12 Switching circuit 13 Unidirectional input / output I / F connector 14 3-state bus I / F connector 15 transmission gate circuit 16 buffer circuit 17 clocked gate buffer circuit 18 host communication connector I / F 19, 20, 87, 88 bus 20a input signal line 20b output signal line 20c control signal line 21 clock signal line 22, 31 pull-up resistor 23 dedicated switch C 32 dedicated switch D 33 pull-down resistor 34 dedicated switch E 41, 42, 43 address decoder 44, 45, 46 NAND circuit 47 register 61 Host computer 62 Evaluation breadboard 63 ICE connector cable 64 Target board 65 CPU core chip 66 Memory chip 67, 85 User logic 68, 86 Analog logic 69 Driver 71 System LSI 72 Probe jig 73 ICE-probe connection connector cable 81 Microprocessor 82 Gate circuit 89 I / O signal terminal

Claims (6)

[Claims] 1. A system LSI (Large Scale Integrat)
an evaluation circuit for evaluating a function of the system LSI and a test board of the system LSI, and a system LSI connection for connecting the evaluation means and the system LSI to be evaluated. Means, a test board connection means for connecting the evaluation means and a test board of the system LSI to be evaluated, and a switch for connecting one of the system LSI connection means or the test board connection means to the evaluation means An emulator comprising: means. 2. The switch means includes a pull-up resistor and a switch for connecting a circuit including the pull-up resistor to a ground, and based on a selection signal generated in accordance with ON / OFF of the switch, 2. The emulator according to claim 1, wherein one of a system LSI connection unit and the test board connection unit is connected to the evaluation unit. 3. The switch means has a pull-up resistor and a pull-down resistor, and the pull-up resistor or the pull-down resistor is connected to a terminal connected to one of the system LSI connection means and the test board connection means. A connection signal generated by connection of either one of the system LSI connection means and the test board connection means to which the terminal is connected, to the evaluation means. The emulator according to claim 1, wherein: 4. The switch means includes an address decoder, a NAND circuit connected to the address decoder, and a register connected to the NAND circuit,
2. The emulator according to claim 1, wherein one of the system LSI connection unit and the test board connection unit is connected to the evaluation unit based on data held in the register. 5. The switch according to claim 1, wherein the switch determines data to be stored in the register according to a control signal and an address signal from an internal control processor or a computer system provided externally. Item 7. The emulator according to Item 4. 6. The emulator according to claim 1, wherein said system LSI connection means is a bidirectional input / output interface, and said test board connection means is a unidirectional input / output interface.