JP2001125663A - Cycle monitoring circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cycle monitoring circuit which enables two CPUs to monitor the cycles of output signals of the opposite-side CPUs both without lowering operation efficiency. SOLUTION: Clock pulses outputted from a 1st CPU 11 are supplied to the set terminal of an RS flip-flop 13 and clock pulses outputted from a 2nd CPU 12 are supplied to the reset terminal. The uninverted output signal Y1 from the RS flip-flop 13 is supplied to an input port 11N of the 1st CPU 11 and the inverted output signal Y2 from the 2nd CPU 12 is supplied to an input port 12N of the 2nd CPU 12. Right before outputting the clock pulses, the CPUs 11 and 12 input the output signal of the RS flip-flop 13, detect whether or not the signal is an ON signal, and detect whether or not the output cycles of the CPUs have varied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cycle monitoring circuit which includes two CPUs and detects a change in the cycle of an output signal of a partner CPU.

[0002]

2. Description of the Related Art In recent years, as electric equipment (for example, a multi-optical axis photoelectric switch) has been improved in function and performance, an apparatus having two CPUs in a control unit to process an enormous amount of data has been developed. Are known. And conventionally, these two CPUs
The output signals of the other CPUs are taken in, and the cycle is monitored.

An example of a conventional cycle monitoring circuit is shown in FIG. 4, in which two CPUs 1 and 2 connect one of the output ports on the other side to one of their own input ports. Then, a clock pulse output from the partner CPU at a predetermined cycle is captured. And each of these CPs
The clock pulses output from U1 and U2 are set to have the same cycle as each other, and each of the CPUs 1 and 2 matches the cycle of the clock pulse output by the partner CPU with the cycle of the clock pulse output by itself. Or not.

The CPU generally operates at a constant cycle based on a reference signal received from a clock circuit.
Since a predetermined signal is output at a frequency obtained by dividing the reference signal, it is possible to determine whether the CPU is operating normally by diagnosing the frequency of the output signal.

[0005]

However, in the conventional cycle monitoring circuit described above, since it is not known when a clock pulse is input from the partner CPU, an interrupt process must be performed, and the operating efficiency of the CPU is reduced. Resulting in. Further, even if the input port is constantly monitored without performing the interrupt processing, the operation efficiency of the CPU is similarly reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is directed to a cycle monitoring circuit in which two CPUs can monitor the cycle of an output signal of a partner CPU without lowering the operation efficiency of both. For the purpose of providing.

[0007]

In order to achieve the above object, a cycle monitoring circuit according to the first aspect of the present invention is a cycle monitoring circuit for monitoring the presence or absence of a cycle variation between two CPUs outputting clock pulses of a predetermined cycle. In the circuit, when the cycle of the clock pulse output from one CPU is T1, the cycle of the clock pulse output from the other CPU is T2, and one pulse width of the other clock pulse is d, T2 + d ≦ T1 ≦ 1.5 × T2 + d is set, and one of these two clock pulses is applied to the set terminal of the RS flip-flop, the other is applied to the reset terminal, and the clock pulse is applied to the set terminal. The CPU takes in the non-inverted output signal of the RS flip-flop immediately before outputting the clock pulse, and The CPU that applies the clock pulse captures the inverted output signal of the RS flip-flop immediately before outputting the clock pulse, so that both CPUs continuously capture the off signal from the RS flip-flop during normal operation. And
Each CPU is characterized in that when the operation of taking in the ON signal next to the OFF signal is performed twice consecutively, it is determined that the period in which the CPU outputs the clock pulse has changed.

According to a second aspect of the present invention, there is provided a cycle monitoring circuit for monitoring the presence or absence of a cycle variation between two CPUs outputting clock pulses of a predetermined cycle. When the period is T1, the period of a clock pulse output from the other CPU is T2, and the width of one pulse of the other clock pulse is d, the following relationship is established: T2 + d ≦ T1 ≦ 1.5 × T2 + d The CPU which sets one of these two clock pulses to the set terminal of the RS flip-flop, applies the other to the reset terminal, and applies the clock pulse to the set terminal, immediately before outputting the clock pulse, The CPU that applies the clock pulse to the reset terminal while receiving the inverted output signal of the Immediately before outputting a pulse.
By capturing the non-inverted output signal of the S flip-flop, both CPUs are configured to continuously capture the ON signal from the RS flip-flop during normal operation.
Each CPU is characterized in that it determines that a change has occurred in the cycle in which the CPU outputs the clock pulse when the operation of taking in the off signal next to the on signal is performed twice consecutively.

[0009]

According to the first aspect of the present invention, the period T1 of one clock pulse is set to be T2 + d ≦ T1 ≦ 1.5 × from the period T2 of the other clock pulse.
T2 + d, where d is the pulse width of the other clock pulse, the CPU is shifted.
Is operating normally, a clock pulse is alternately supplied from each CPU to the set terminal and the reset terminal of the RS flip-flop, and each time each CPU outputs the clock pulse, the set operation and the reset operation are performed. Is repeated. Then, each CPU takes in the off signal from the RS flip-flop immediately before outputting the clock pulse. However, when the period of the CPU fluctuates due to abnormal operation of the CPU, the clock pulse is not alternately applied to the set terminal and the reset terminal. Is not performed, and one of the CPUs performs an operation of taking in the ON signal next to the OFF signal. Then, when this operation is performed twice consecutively, it is determined that the cycle of outputting the clock pulse has changed.

According to the second aspect of the present invention, the cycle T1 of one clock pulse is set to be T2 + d ≦ T1 ≦ 1.5 × T from the cycle T2 of the other clock pulse.
2 + d, where d is the pulse width of the other clock pulse, so that when the CPU is operating normally, the set terminal of the RS flip-flop and the reset Clock pulses are alternately applied to the terminals and the set operation and the reset operation are repeated each time each CPU outputs the clock pulse. Then, each CPU takes in the ON signal from the RS flip-flop immediately before outputting the clock pulse. However, when the period of the CPU fluctuates due to abnormal operation of the CPU, the clock pulse is not alternately applied to the set terminal and the reset terminal. Is not performed, and one CPU performs an operation of taking in an off signal next to an on signal. And
When this operation is performed twice consecutively, it is determined that the period for outputting the clock pulse has changed.

[0011]

According to the first and second aspects of the present invention, the CPU detects an abnormality of the CPU at the timing accompanying the output of the clock pulse, so that the CPU does not need interrupt processing, and always does not require any interrupt processing. It is not necessary to monitor the input port, and the operation efficiency of the CPU can be improved.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIG. The cycle monitoring circuit according to the present embodiment is shown in FIG. 1 and includes first and second CPUs 11 and 1.
2 and an RS flip-flop 13. The output terminal 11P of the first CPU 11 is connected to the set terminal of the RS flip-flop 13, and the second CPU 12 is connected to the reset terminal.
Output port 12P is connected. Also, the first CP
The non-inverting output terminal of the RS flip-flop 13 is connected to the input port 11N of U11, and the non-inverting output signal Y1 (see FIGS. 2 and 3) at a predetermined timing described later.
Is taken into the first CPU 11 while the second CPU 12
The inverted output terminal of the RS flip-flop 13 is connected to the input port 12N, and the inverted output signal Y2 (see FIG. 2 and FIG. 3) is taken into the second CPU 12 at a predetermined timing also described later.

Each of the CPUs 11 and 12 receives a reference signal from a separate clock circuit (not shown) at a constant cycle, and runs a main program (not shown) every time the CPU 11 and 12 receives this reference signal. Then, according to the settings of each of these main programs, as shown in FIG. 2, the first CPU 11 outputs a clock pulse from the output port 11P at a period T1,
The second CPU 12 outputs a clock pulse from the output port 12P in a cycle T2. Here, the cycle T2 of one clock pulse is set to be longer than the cycle T1 of the other clock pulse by one pulse width d of the clock pulse. Note that these periods T1 and T2 are:
The frequency of the reference signal is divided.
Both clock pulses output from the PUs 11 and 12 have the same pulse width d.

Each of the CPUs 11, 12 takes in inverted or non-inverted output signals Y1, Y2 applied to the input ports 11N, 12N of the respective CPU 11, 12 just before outputting a clock pulse in accordance with each main program. Specifically, each of the CPUs 11 and 12 starts a timer in each main program every time a clock pulse is output, and at a timing when the measurement time reaches a set time slightly shorter than one cycle of outputting the clock pulse. , Take in the signal given to the input port.

Each of the CPUs 11 and 12 determines whether the received signal is an ON signal (H-level signal) or an OFF signal (L-level signal). The setting is made such that when the “fetching operation” is performed twice consecutively, it is determined that a fluctuation has occurred in any one of the CPU cycles.

Next, the operation of this embodiment having the above configuration will be described. As shown at times S1 to S6 in FIG.
When clock pulses are alternately output from the PUs 11 and 12 to the RS flip-flop 13, the following operation is performed. First, the first CPU 11 determines the time S2 in FIG.
The clock pulse (see CP11 in FIG. 2A)
The signal is output to the set terminal of the S flip-flop 13 and the off signal which is the non-inverted output signal Y1 (see FIG. 2C) of the RS flip-flop 13 is taken immediately before the time S2. At time S2, the second CPU 12 does not supply a clock pulse to the reset terminal of the RS flip-flop 13 (see FIG. 2B), so that the RS flip-flop 13 performs the set operation at time S2 and outputs the non-inverted output signal. Y1 (see FIG. 2C) is inverted from off to on, and the inverted output signal Y2 (see FIG. 2D) is inverted from on to off.

Next, the second CPU 12 takes in the off signal which is the inverted output signal Y2 of the RS flip-flop 13 immediately before time S3, and outputs a clock pulse to the reset terminal of the RS flip-flop 13 at time S3. At this time S3, since the first CPU 11 has not output the clock pulse to the set terminal, the RS flip-flop 13 performs a reset operation and the non-inverted output signal Y1
Is inverted from on to off, and the inverted output signal Y2 is inverted from off to on. As a result, the output signals Y1 and Y2 of the RS flip-flop 13 return to the state immediately before time S2.

Each time a clock pulse is alternately applied from the CPUs 11 and 12 to the RS flip-flop 13, the set operation and the reset operation are repeated, as in the case of the times S2 and S3. 1
2 receives the off signal from the RS flip-flop 13.

Each of the CPUs 11 and 12 determines whether the received signal is an off signal or an off signal.
When the “operation to take in the ON signal next to the OFF signal” is performed twice consecutively, it is determined that a fluctuation has occurred in one of the CPU cycles.

Here, in the present embodiment, the second CPU 12
The period T2 of the clock pulse output from the first CPU
11 is set to be longer by one pulse width d than the cycle T1 of the clock pulse output from the CPU 11,
2 is operating normally, time S1 to S1 in FIG.
As shown in FIG. 6, a state in which clock pulses are alternately output from the CPUs 11 and 12 to the RS flip-flop 13 continues continuously. And both CPUs 11, 1
Clock pulse from RS flip-flop 1
3 (see time S0 in FIG. 2) or a situation in which two or more clock pulses are continuously supplied from only one of the CPUs. Since the clock pulses are shifted from each other by one pulse width d, the above situation does not occur twice consecutively.

Therefore, when the CPUs 11 and 12 are operating normally, the CPUs 11 and 12 do not perform the “operation of taking in the ON signal next to the OFF signal” twice consecutively from the RS flip-flop 13. It is not determined that a change has occurred in the predetermined cycle of the CPU.

On the other hand, as shown in FIG.
Is abnormal, and the cycle T1 of the clock pulse output from the first CPU 11 is twice as long as in the normal operation, as follows. In this case, for example, as shown at times S10 to S16 in the figure, while two clock pulses (see CP1 and CP1 in FIG. 3) are output from the first CPU 11, two clock pulses (see FIG.
The operation of outputting CP2 and CP2 of FIG.
Get up more than once in a row. Then, the cycle monitoring circuit of the present embodiment operates as follows.

That is, immediately before time S11, the second CPU 12 takes in the inverted output signal Y2 as an off signal,
The RS flip-flop 13 performs a reset operation to invert the inverted output signal Y2 from off to on. Next, before the second CPU 12 captures the inverted output signal Y2, the first CPU 11 does not output a clock pulse. ,
The RS flip-flop 13 does not perform the set operation, and the second CP
The inverted output signal Y2 captured next by U12 (immediately before time S12) becomes an ON signal. Therefore, the second CPU
12 is an operation of capturing an ON signal next to an OFF signal.
Once, for example, a flag is set to that effect.

Next, at time S13, the first CPU
11 outputs a clock pulse to cause the RS flip-flop 13 to perform a set operation, and the inverted output signal Y2 is inverted from on to off. Then, the second CPU 12 sets the time S14
, The inverted output signal Y2 is taken as an off signal, and the RS flip-flop 13 is reset.
The inverted output signal Y2 is inverted from off to on. However, again, the second CPU 12 next outputs the inverted output signal Y2.
Since the first CPU 11 does not output a clock pulse before capturing the ON signal, the RS flip-flop 13 does not perform the set operation, and the second CPU 12 captures the ON signal. As a result, the second CPU 12 continuously performs the “operation of capturing the ON signal next to the OFF signal” twice, determines that the output cycle of the clock pulse of the CPU has changed, and outputs, for example, a warning signal.

Similarly, when the cycle of the clock pulse of the second CPU 12 is twice as long as in the normal state,
Alternatively, also when the clock pulse cycle of the second CPUs 11 and 12 becomes half of the normal time, one of the CPUs can determine that the output cycle of the clock pulse has changed.

When the second CPU 12 performs the "operation of taking in the off signal twice" successively after performing the "operation of taking in the on signal next to the off signal" once, the flag is reset. Canceled. Also, for example,
If the cycle of the clock pulse of the first CPU 11 is longer than twice as long as the normal state, the second CPU 12 executes the “operation of taking in one or more off signals next to one off signal”.
In this case, the flag is not canceled because the above-described “operation of continuously taking in the off signal twice” is not performed, and it is determined that the period has changed.

As described above, according to the present embodiment, the CPU
Each of the CPUs 11 and 12 detects an abnormality in one of the CPUs 11 and 12 at a timing associated with the output of its own clock pulse. Therefore, the CPU does not need to perform an interrupt process and does not need to constantly monitor an input port. Operation efficiency can be improved.

<Other Embodiments> The present invention is not limited to the above embodiments. For example, the following embodiments are also included in the technical scope of the present invention.
In addition to the following, various changes can be made without departing from the scope of the invention. (1) In the above embodiment, the clock pulses output by both CPUs 11 and 12 have the same pulse width, but they may have different pulse widths.

(2) The cycle of the clock pulse output from both CPUs does not necessarily have to be set to be shifted by one pulse width as in the above embodiment.
The period T1 of the clock pulse output from
The relationship T2 + d ≦ T1 ≦ 1.5 × T2 + d may be provided between the period T2 of the clock pulse output from the PU and one pulse width d of the clock pulse.

(3) In the above embodiment, the first CPU 11 that applies a clock pulse to the set terminal receives the inverted output signal of the RS flip-flop 13, while the second CPU 12 that applies the clock pulse to the reset terminal.
Both CPUs 1 are connected so as to take in a non-inverted output signal.
When both 1 and 12 are operating normally, the on signal may be continuously taken in from the RS flip-flop.
In this case, when the CPUs 11 and 12 perform the operation of taking in the off signal next to the on signal twice in succession, it may be determined that the periodic fluctuation has occurred.

[Brief description of the drawings]

FIG. 1 is a block diagram of a cycle monitoring circuit according to an embodiment of the present invention.

FIG. 2 is a time chart when both CPUs are operating normally;

FIG. 3 is a time chart when a cycle of a clock pulse of a first CPU is doubled.

FIG. 4 is a block diagram of a conventional cycle monitoring circuit.

[Explanation of symbols]

 Reference numeral 13: RS flip-flop T1, T2: Clock pulse period 11, 12, CPU Y1: Non-inverted output signal Y2: Inverted output signal d: Pulse width

Claims (2)

[Claims] 1. A method for outputting a clock pulse having a predetermined period
In a cycle monitoring circuit that monitors the presence or absence of a cycle variation between two CPUs, a cycle of a clock pulse output from one of the CPUs is T1, and a cycle of a clock pulse output from the other CPU is T1.
2, when one pulse width of the other clock pulse is d, the following relationship is established: T2 + d ≦ T1 ≦ 1.5 × T2 + d, and either one of these two clock pulses is set to an RS flip-flop. While giving the other to the reset terminal, giving the other to the reset terminal, and giving the clock pulse to the set terminal, the CPU takes in the non-inverted output signal of the RS flip-flop immediately before outputting the clock pulse, The CPU giving the clock pulse captures the inverted output signal of the RS flip-flop immediately before outputting the clock pulse, so that both CPUs
During a normal operation, the CPU is configured to take in an off signal continuously from the RS flip-flop. A cycle monitoring circuit for determining that a variation has occurred in a cycle of outputting a pulse. 2. A circuit for outputting a clock pulse having a predetermined period.
In a cycle monitoring circuit that monitors the presence or absence of a cycle variation between two CPUs, a cycle of a clock pulse output from one of the CPUs is T1, and a cycle of a clock pulse output from the other CPU is T1.
2, when one pulse width of the other clock pulse is d, the following relationship is established: T2 + d ≦ T1 ≦ 1.5 × T2 + d, and either one of these two clock pulses is set to an RS flip-flop. The CPU which supplies the other to the set terminal and the other to the reset terminal, and applies the clock pulse to the set terminal, takes in the inverted output signal of the RS flip-flop immediately before outputting the clock pulse, and outputs the clock to the reset terminal. The CPU giving the pulse captures the non-inverted output signal of the RS flip-flop immediately before outputting the clock pulse, so that both CPUs
During normal operation, the CPU is configured to continuously capture an ON signal from the RS flip-flop. When the CPU performs an operation of capturing an OFF signal next to an ON signal twice in succession, the CPU receives a clock. A cycle monitoring circuit for determining that a variation has occurred in a cycle of outputting a pulse.