JPH086822A - Cpu device with runaway monitoring function - Google Patents

Abstract

PURPOSE:To securely detect a CPU being runaway through simple constitution. CONSTITUTION:An edge is detected from level variation at the time of runaway the switching of an external clock, which has cycles much longer than an interruption cycle of the CPU 22 as an object of monitoring, from a high level to a low level or vice versa, and it is judged whether or not the CPU 22 operates normally from whether or not the frequency (n) of interruption initiated in the high-level period or low-level period of the external clock up to the point is in the specified range (Nmin<=n<=Nmax). An oscillator 23 which generates the external clock can be connected not to the interruption input terminal of the CPU 22, but to the normal input port P0 and this device is specially effective in monitoring whether or not the low-function CPU 22 is runaway.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU with a runaway monitoring function that can easily and reliably detect a runaway of a CPU.
Regarding the device.

[0002]

2. Description of the Related Art CP with a conventional runaway monitoring function shown in FIG.
The U device 1 has a configuration in which a watchdog circuit 3 is connected to a CPU 2 incorporated in a vehicle-mounted electronic device and the watchdog circuit 3 immediately resets when an abnormal operation is found in the CPU 2. The CPU 2 executes the main job defined in the operation program, and a timer interrupt is applied at a predetermined cycle by an internal timer (not shown) in the middle of the process. In addition to the timer interrupt, an interrupt is generated by a diagnostic pulse sent from the external oscillator 3 and having a cycle shorter than the cycle of the operating program, and when operating normally, the watchdog is output from the output port P1 immediately after the interrupt. Output pulse. This watchdog pulse is taken into the watchdog circuit 4 through the clear input terminal and the cycle is discriminated. When a cycle abnormality is recognized, a reset signal is sent from the carry output terminal of the watchdog circuit 4 to the reset input terminal of the CPU 2. It is sent in and the CPU 2 is reset.

The watchdog circuit 4 shown in this example is
It has a built-in timer (not shown) that counts clock pulses of a fixed period, and when the CPU2 is operating normally, the timer value is changed by the watchdog pulse before the timer outputs carry (carry). If it is cleared, but the CPU 2 is not able to process the program normally and is running out of control, the watchdog pulse will not be output at all or the output will take a long period. The carry output is supplied to the reset input terminal of the CPU 2, whereby the CPU 2 is reset.

[0004]

The conventional CPU device 1 with the runaway monitoring function has a carry output for a failure in which the cycle of the watchdog pulse output by the CPU 2 becomes long or a failure in which the watchdog pulse is not output at all. CPU2 by the reset signal output from the terminal
However, if the CPU2 is reset, but the cycle of the watchdog pulse becomes short, that is, the CPU2 outputs a watchdog pulse regardless of the interrupt input to the interrupt input terminal, the reset signal is not output. Since the timer continues to be cleared, the CPU 2 is not reset forever and there is a problem that an abnormality cannot be found. Further, in the above-described conventional CPU device 1 having the runaway monitoring function, the oscillator 3 is connected to the interrupt input port INTP of the CPU 2 and the diagnostic pulse is input at a cycle shorter than the operation program round-trip processing time.
Since the oscillator 3 is required to have a high oscillation frequency, and strict edge detection cannot be performed via a normal input port, a plurality of interrupt input ports IN provided in the CPU 2 are provided.
One of the TPs must be surrendered to detect the edge of the diagnostic pulse, which is why the conventional CPU with runaway monitoring function
Device 1 is a low-function C with a limited number of interrupt input ports.
There is a problem that it cannot be applied when PU2 is used.

In order to monitor CPU runaway more fully, for example, a conventional CP with runaway monitoring function shown in FIG.
There is also known a device such as the U device 11 which uses a dedicated monitoring CPU 13 for the runaway monitoring of the CPU 12. In the case of the device 11, the operation program of the CPU 12 is divided into a plurality of blocks, and a flag is set every time the processing of the steps that must pass through is completed for each block, and when the processing of the operation program has been completed. All flag data is sent to the CPU 12 via the dedicated data bus 14.
From the CPU 13 to the monitoring CPU 13. At this time, C for monitoring
The PU 13 analyzes all flag data sent via the data bus 14 for diagnosis, and immediately issues a reset signal to the CPU 1 when an abnormality is found as a result of the diagnosis.
It was supposed to reset 2. However, the CPU device 11 with the runaway monitoring function of this kind must analyze all flag data in order to diagnose the progress of the operation program when it completes the loop processing of the operation program, and also transmits the flag data. For use in PU12
The monitoring CPU 13 and the monitoring CPU 13 must be connected by a dedicated data bus, and the monitoring CPU 13 is also required to have an analysis capability of analyzing the collected flag data, which causes a problem that the entire circuit configuration becomes complicated. It was something I had.

[0006]

DISCLOSURE OF THE INVENTION The present invention is to solve the above-mentioned problems by executing interrupt processing at a predetermined interrupt cycle and outputting a watchdog pulse to the outside at the end of the interrupt processing. During the processing period, as long as the external clock input port has the same signal level, the number of interrupts is incremented each time the interrupt processing is performed, and the signal count of the external clock input port is inverted to reset the interrupt count value to zero. A CP that determines the threshold value of the interrupt count value at the start of the interrupt process, and shifts to the abnormal process without performing the interrupt process if the interrupt count value deviates from the specified range.
U, an oscillator for inputting an external clock having a period sufficiently larger than the interrupt period to the external clock input port of the CPU, and a period of a watchdog pulse externally output by the CPU. CPU
And a watchdog circuit for resetting.

The present invention also executes a program in which a plurality of blocks are arranged in processing order, sets a flag each time the blocks are exhausted, and compares the total number of flags with a specified value at the end of the loop processing. A CPU that outputs a watchdog pulse from a watchdog pulse output port only when the total number of flags matches a specified value;
A watchdog circuit for monitoring the cycle of the watchdog pulse externally output by U and resetting the CPU if there is a cycle abnormality is provided.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit block diagram showing an embodiment of a CPU device with a runaway monitoring function of the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 3 is a diagram of the CPU shown in FIG. 7 is a flowchart illustrating an interrupt processing operation.

CPU device 2 with runaway monitoring function shown in FIG.
1 is, for example, a CPU 2 used in an in-vehicle electronic control unit
2, the oscillator 23 and the watchdog circuit 2 used to monitor the runaway of the CPU 22 and prevent the runaway.
4 and the like are arranged. The CPU 22 executes a main job in accordance with an operation program that has been loaded in advance, and also executes various interrupt processes at a predetermined cycle by a timer interrupt. Further, the CPU 22 has a built-in counter 25 that counts the number of interrupts stepwise each time interrupt processing is performed. The counter 25 is reset to zero at the edge portion of the external clock supplied to the external clock input port, and restarts counting the number of interrupts from zero again. Further, the CPU 22 determines that the number of interrupts n counted by the counter 25 is within a specified range (Nmin ≦
Only when n ≦ Nmax), the watchdog pulse output port P1 outputs the watchdog pulse to the outside by receiving the increment or reset of the counter 25.

The oscillator 23 sends an external clock having a period sufficiently larger than the timer interrupt period to the external clock input port P0 of the CPU 22. For example, the external clock alternately switches to a high level and a low level at a period of about 50 ms. Output. The external clock has a significant meaning at the time of switching from the low level to the high level, that is, at the rising edge and at the switching time of the high level to the low level, that is, at the falling edge. Whether or not there is a runaway is diagnosed by timing with. This timing operation only needs to identify whether the external clock is at a high level or a low level.
It does not require time differentiation for capturing a change in signal level as in edge detection, and is therefore possible not only at an interrupt input terminal but also at a normal input port P0. That is, since it is only necessary to detect the level of the external clock input port P0, the oscillator 23 can be connected to the CPU 22 having a relatively low function.

In the runaway monitoring, first, in step (101) shown in FIG. 3, it is determined whether or not the count value n of the counter 25 is less than or equal to the specified maximum value Nmax. In this case, if the count value n exceeds the specified maximum value Nmax, the process immediately proceeds to the abnormal processing in step (102) and the output of the watchdog pulse from the watchdog pulse output port P1 is stopped. The watchdog circuit 24 supplies a reset signal to the reset input terminal of the CPU 22 to reset the CPU 22.

On the other hand, when the count value n is equal to or less than the specified maximum value Nmax, one cycle of interrupt processing is executed in step (103). In parallel with the execution of this interrupt processing, the level of the external clock input port P0 is detected as shown in step (104). Then, if the level of the external clock input port P0 has not changed at this time, as shown in FIGS. 2A and 2B, in response to the positive determination result of the determination step (105), the step ( In 106), 1 is added to the count value of the counter 25 to increment it. However, when the edge of the external clock is detected from the level change at the external clock input port P0, the determination step (10
Subsequent to the positive determination result of 5), the process proceeds to a determination step (107). At this time, the count value n is the specified minimum value N
If it is greater than or equal to min, the count value n of the counter 25 is reset to zero in the subsequent step (108). However, when the count value n is less than the specified minimum value Nmin, the process proceeds to the abnormality processing in step (109). For this reason,
The output of the watchdog pulse from the watchdog pulse output port P1 is stopped, and the watchdog circuit 24 receiving this stops supplying the reset signal to the reset input terminal of the CPU 22 to reset the CPU 22.

After the count value of the counter 25 is incremented or reset in steps (106) and (108), a watchdog pulse is output in the final step (110), and the interrupt processing is terminated. Therefore, every time the interrupt process is normally performed, as shown in FIG. 2C, the watchdog pulse is output to the watchdog circuit 24 once every two interrupt processes. Therefore, if the watchdog pulse output in a cycle twice as long as the interrupt cycle is lost even once, the watchdog circuit 24 can catch this as an abnormal cycle of the watchdog pulse and immediately issue a reset signal.

As described above, the CPU with the runaway monitoring function
According to the device 21, the external clock whose period is sufficiently longer than the interrupt period of the CPU 22 which is the runaway monitoring target detects the edge by level detection when switching from the high level to the low level or from the low level to the high level, and detects the external clock. The number of interrupts n that occurred during the high level period or the low level period up to that point is within the specified range (Nm
in ≦ n ≦ Nmax)
The operation of 22 can be judged to be normal or abnormal. Further, the oscillation cycle of the oscillator 23 may be set to match the time required for the operating program of the CPU 22 to make one round, so that high-speed oscillation operation is unnecessary. Further, since the CPU 22 may reset the count value of the counter 25 to zero when the level of the external clock changes, the external clock is not detected to the interrupt input port having the edge detection function, but to detect the difference in signal level. Possible normal input port P0
, So that the interrupt input port INTP of the CPU 22 can be released from runaway monitoring. Further, since the CPU 22 makes an abnormality determination with the count value n of the counter 25 immediately after the start of the interrupt processing and then outputs the watchdog pulse upon receiving the increment or reset of the counter 25, the abnormality determination is not made. A processing abnormality of the CPU 22, such as not outputting a watchdog pulse, can be detected on the spot, and is very useful when applied to a relatively inexpensive CPU 22 having a limited number of ports.

CPU device 3 with runaway monitoring function shown in FIG.
In No. 1, the operation program of the CPU 32 is divided into blocks of 1 to n, and each block is provided with a place where a flag is set to a step which always passes. The CPU 32 sets a flag each time each block is exhausted, compares the total number of flags with a specified value at the end of one round of processing, and only when the total number of flags matches the specified value n, the watchdog pulse output port P1 outputs a watchdog pulse. Output pulse externally.
The watchdog pulse externally output by the CPU 32 is sent out to the watchdog circuit 34 via the signal line 33. When the watchdog circuit 34 finds an abnormal cycle of the watchdog pulse, the CP
U32 is reset.

That is, when the CPU 32 is operating normally, as shown in FIG. 5, when the operation program divided into n blocks has been smoothly processed for each block, each block is processed. The total number of flags raised each time it reaches n. Therefore, the judgment step (n +
The determination in 1) is affirmed, and the watchdog pulse is output from the output port P1. However, if the total number of flags has not reached n and the determination in the determination step (n + 1) is negative, the watchdog pulse cannot be obtained and therefore the watchdog circuit 34 causes the CPU 3
2 is reset. The CPU device 31 with the runaway monitoring function causes the CPU 32 itself to count the total number of flags set up each time it processes an individual block, and leaves it up to the CPU 32 to determine whether or not the counted value matches the specified value n. As a result, the watchdog circuit 34 and the CPU 3
2 can be connected not by the data bus but by one signal line 33 for the watchdog pulse, which can simplify the entire circuit configuration.

[0017]

As described above, according to the present invention,
An external clock whose period is sufficiently longer than the interrupt period of the CPU that is the runaway monitor detects an edge by looking at the level change when switching from high level to low level or from low level to high level, and detects the high level of the external clock until then. The CPU determines whether the number of interrupts generated during the level period or the low level period matches the specified number.
Since the operation of is determined to be normal or abnormal, the oscillation cycle of the oscillator may be set to match the time required for the operating program of the CPU to make one round. Therefore, high-speed oscillation operation is not necessary, and the CPU also has the level of the external clock. Since it is only necessary to reset the count value of the counter to zero upon detection, connect the oscillator that generates the external clock to the normal input port that can detect the difference in signal level, not to the interrupt input port that has the edge detection function. This allows the interrupt input port of the CPU to be released from runaway monitoring, and the CPU performs the abnormality determination with the count value of the counter immediately after entering the interrupt processing and then increments or resets the counter. Since it receives a watchdog pulse and outputs a watchdog pulse, no abnormality judgment was made, but The process abnormalities and went CPU does not output a Chidogguparusu, it is possible to detect immediately, C of a relatively low functionality with limited number of ports
It has excellent effects such as being particularly suitable when using PU.

Further, according to the present invention, a CP which is a runaway monitoring target
U executes a program in which a plurality of blocks are arranged in processing order, sets a flag each time the blocks are exhausted, and compares the total number of flags with a specified value at the end of one round of processing. Only when the values match, the watchdog pulse output port outputs the watchdog pulse externally, the watchdog circuit monitors the cycle of this watchdog pulse, and resets the CPU if there is a cycle abnormality. Letting it count the total number of flags it has set each time it processes an individual block,
C until the count value matches the specified value
By leaving it to the PU, the watchdog circuit and CPU
Need only be connected with a single signal line for the watchdog pulse instead of the data bus, which simplifies the overall circuit configuration and is particularly suitable for monitoring low-function CPUs with a limited number of ports. Produce the effect.

[Brief description of drawings]

FIG. 1 is a schematic circuit block diagram showing an embodiment of a CPU device with a runaway monitoring function according to the present invention.

FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG.

FIG. 3 is a flowchart for explaining an interrupt processing operation by the CPU shown in FIG.

FIG. 4 is a schematic circuit block diagram showing another embodiment of the CPU device with the runaway monitoring function of the present invention.

5 is a flow chart for explaining the operation of the CPU device with a runaway monitoring function shown in FIG. 4. FIG.

FIG. 6 is a schematic circuit block diagram showing an example of a conventional CPU device with a runaway monitoring function.

FIG. 7 is a schematic circuit block diagram showing another example of a conventional CPU device with a runaway monitoring function.

[Explanation of symbols]

 21, 31 CPU device with runaway monitoring function 22, 32 CPU 23 Oscillator 33 Signal line 24, 34 Watchdog circuit 25 Counter P0 External clock input port P1 Watchdog pulse output port

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazumi Nakae 1-42 Jomi, Chuo-ku, Osaka-shi, Osaka NEC Home Electronics Co., Ltd.

Claims (2)

[Claims] 1. An interrupt process is executed at a predetermined interrupt cycle, a watchdog pulse is externally output at the end of the interrupt process, and the interrupt signal is output as long as the external clock input port has the same signal level during the interrupt process period. In addition to counting the number of interrupts in each process,
The interrupt count value is reset to zero in response to the signal level inversion of the external clock input port, and the interrupt count value is discriminated as a threshold value at the start of the interrupt processing, and the interrupt count value falls within a specified range. CPU deviating from the above, the CPU shifts to abnormal processing without interrupt processing
And an oscillator for inputting an external clock having a period sufficiently larger than the interrupt period to the external clock input port of the CPU, and a period of a watchdog pulse externally output by the CPU. A CPU device with a runaway monitoring function, comprising a watchdog circuit for resetting 2. A program in which a plurality of blocks are arranged in a processing order is executed, a flag is set each time the blocks are exhausted, and the total number of flags is compared with a prescribed value at the end of one round of processing, and the total number of flags is calculated. CPU that outputs a watchdog pulse externally from the watchdog pulse output port and the cycle of the watchdog pulse that is externally output by the CPU is monitored only when is equal to the specified value, and if there is a cycle abnormality, the CPU is reset. A CPU device with a runaway monitoring function, comprising a watchdog circuit.