CN114968681A

CN114968681A - Method and device for monitoring I2C bus communication abnormity and I2C master device

Info

Publication number: CN114968681A
Application number: CN202210379872.8A
Authority: CN
Inventors: 许林华
Original assignee: Xiamen Ziguang Zhanrui Technology Co ltd
Current assignee: Xiamen Ziguang Zhanrui Technology Co ltd
Priority date: 2022-04-12
Filing date: 2022-04-12
Publication date: 2022-08-30

Abstract

The application discloses a method and a device for monitoring I2C bus communication abnormity, and an I2C master device, wherein a master device and at least one slave device are connected to an I2C bus, and the method comprises the following steps: acquiring a clock signal sent by a master device to a slave device; acquiring a feedback signal corresponding to the clock signal on an SCL; determining an abnormal device by comparing the clock signal and the feedback signal. The scheme of the application can quickly and accurately locate the abnormal equipment on the I2C bus.

Description

Method and device for monitoring I2C bus communication abnormity and I2C master device

Technical Field

The application relates to the technical field of communication, in particular to a method and a device for monitoring I2C bus communication abnormity and I2C main equipment.

Background

The I2C (Inter-Integrated Circuit) bus is a simple, bi-directional two-wire synchronous serial bus that is widely used in low-speed communication scenarios. I2C communication operates in a master-slave manner, typically with most of the communication being between a master device and multiple slave devices. The I2C bus uses SCL (Serial Clock Line) and SDA (Serial Data Address bus) to implement connection communication with the slave devices, respectively, and the basic architecture of the I2C bus system is shown in fig. 1 and includes one master device and N slave devices.

In the prior art, when communication abnormality occurs on the I2C bus, the slave devices on the I2C bus are usually removed one by disassembling the devices, and a specific slave device is excluded from the abnormality. The problem can not be found visually in the mode, the problem point needs to be positioned by disassembling equipment, and time and labor are wasted.

Disclosure of Invention

The embodiment of the application provides a method and a device for monitoring I2C bus communication abnormity and I2C main equipment, so that abnormal equipment on an I2C bus can be positioned quickly and accurately.

In order to solve the above technical problem, an embodiment of the present application provides the following technical solutions:

in one aspect, an embodiment of the present application provides a method for monitoring communication abnormality of an I2C bus, where a master device and at least one slave device are connected to the I2C bus, the method includes:

acquiring a clock signal sent by a master device to a slave device;

acquiring a feedback signal corresponding to the clock signal on an SCL;

determining an abnormal device by comparing the clock signal and the feedback signal.

Optionally, the feedback signal is delayed by a certain period from the clock signal.

Optionally, the determining an abnormal device by comparing the clock signal and the feedback signal comprises: and if the feedback signal is 0 when the clock signal is 1 and lasts for a certain time, determining that the slave device is abnormal.

Optionally, the method further comprises: and if the delay signal of the clock signal is consistent with the clock signal but keeps unchanged for a certain time, determining that the master equipment is abnormal.

Optionally, the method further comprises: generating an interrupt signal under the condition that the equipment abnormality is detected; and controlling the I2C bus communication according to the interrupt signal.

Optionally, the controlling I2C bus communication according to the interrupt signal includes: reading the interrupt signal when the I2C bus communication is abnormal; if the interrupt signal represents that the main equipment is abnormal, resetting the main equipment; and if the interrupt signal indicates that the slave equipment is abnormal, ending the communication.

On the other hand, the embodiment of the present application further provides an apparatus for monitoring communication abnormality of an I2C bus, where a master device and at least one slave device are connected to the I2C bus, the apparatus includes:

the clock signal acquisition module is used for acquiring a clock signal sent by the master device to the slave device;

the feedback signal acquisition module is used for acquiring a feedback signal corresponding to the clock signal on the SCL;

and the first judgment module is used for determining abnormal equipment by comparing the clock signal with the feedback signal.

Optionally, the first determining module is specifically configured to determine that the slave device is abnormal when the feedback signal is 0 and lasts for a certain time when the clock signal is 1.

Optionally, the first determining module includes: the first time delay device, the inverter, the first AND gate and the first timer; the first AND gate is provided with three input ends, wherein one input end inputs an I2C working state signal, the other two input ends are respectively connected with the output end of the first delayer and the output end of the phase inverter, and the output end of the first AND gate is connected with the input end of the first timer; the output end of the first AND gate is connected with the input end of the first timer;

the first delay is used for inputting the clock signal;

the inverter is used for inputting the feedback signal;

the first AND gate is used for outputting a high level to trigger the first timer to start timing when the clock signal is 1 and the feedback signal is 0;

the first timer is used for outputting a slave device abnormity indication signal after the timed time reaches a set first duration.

Optionally, the apparatus further comprises: and the second judgment module is used for determining that the master equipment is abnormal under the condition that the delay signal of the clock signal is consistent with the clock signal but keeps unchanged for a certain time.

Optionally, the second determining module includes: the second time delay, the exclusive-nor gate, the second and gate and the second timer; the output end of the second delayer is connected with one input end of the exclusive nor gate; the other input end of the exclusive-nor gate inputs the clock signal; the second AND gate is provided with two input ends, wherein one input end inputs an I2C working state signal, and the other input end is connected with the output end of the exclusive-OR gate; the output end of the second AND gate is connected with the input end of the second timer;

the second delay is used for inputting the clock signal;

the second AND gate is used for outputting a high level to trigger the second timer to start timing under the condition that the feedback signal is consistent with the clock signal;

and the second timer is used for outputting a main equipment abnormity indication signal after the timing time reaches a set second duration.

Optionally, the slave device abnormality indication signal and the master device abnormality indication signal are interrupt signals; the device further comprises: and the control module is used for controlling the I2C bus communication according to the interrupt signal.

Optionally, the control module is specifically configured to read the interrupt signal when the I2C bus communication is abnormal, and reset the master device if the interrupt signal indicates that the master device is abnormal; and if the interrupt signal indicates that the slave equipment is abnormal, ending the communication.

On the other hand, the embodiment of the application also provides an I2C master device, and the device comprises the device for monitoring the I2C bus communication abnormity.

In another aspect, the present invention also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transitory storage medium, and has a computer program stored thereon, where the computer program is executed by a processor, and the computer program causes the foregoing method to be performed.

In another aspect, an apparatus for monitoring I2C bus communication abnormality is provided, which includes a memory and a processor, where the memory stores a computer program executable on the processor, and the processor executes the computer program to cause the method to be performed.

According to the method and the device for monitoring I2C bus communication abnormity and the I2C master device, the clock signal sent by the master device to the slave device is obtained, the feedback signal corresponding to the clock signal on the SCL is obtained, and then the abnormal device can be determined by comparing the clock signal with the feedback signal.

Further, the abnormal device can be determined by comparing the delayed signal of the clock signal with the clock signal.

The scheme that this application embodiment provided need not to disassemble equipment on the I2C bus, can be simply, conveniently, fast accurate location whether master equipment or slave unit appear unusually, makes things convenient for the investigation of I2C bus system abnormal conditions.

Drawings

FIG. 1 is a basic architecture diagram of a conventional I2C bus system;

FIG. 2 is a schematic diagram illustrating a method for monitoring I2C bus communication anomalies according to an embodiment of the present application;

FIG. 3 is a flowchart of a method for monitoring I2C bus communication anomalies according to an embodiment of the present application;

FIG. 4 is a flow chart illustrating control of I2C bus communication according to an interrupt signal in an embodiment of the present application;

FIG. 5 is a schematic structural diagram of an apparatus for monitoring I2C bus communication abnormality according to an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a first determining module in the apparatus for monitoring I2C bus communication abnormality according to the embodiment of the present application;

FIG. 7 is a schematic structural diagram of a second determining module in the apparatus for monitoring I2C bus communication abnormality according to the embodiment of the present application;

fig. 8 is another schematic structural diagram of the apparatus for monitoring I2C bus communication abnormality according to the embodiment of the present application.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.

Aiming at the problem that abnormal equipment on an I2C bus cannot be simply and quickly positioned after the I2C bus is abnormal in the prior art, the embodiment of the application provides a method and a device for monitoring communication abnormality of the I2C bus and I2C master equipment, clock signals sent by the master equipment to slave equipment and feedback signals corresponding to the clock signals are obtained from an SCL, and then the abnormal equipment can be determined by comparing the clock signals with the feedback signals.

Fig. 2 is a schematic diagram illustrating a method for monitoring an I2C bus communication abnormality according to an embodiment of the present application.

A logic circuit 21 is provided in the master device, and the logic circuit 21 is connected to the SCL.

As shown IN fig. 2, the logic circuit 21 has two ports, i.e., an OUT port and an IN port. The port OUT is an output end, and the port IN is an input end.

The output terminals OUT and SCL of the logic circuit 21 are connected to the connection point OE, and the input terminals IN and SCL of the logic circuit 21 are connected to the pin pad. The SCL clock signal is a clock signal driven by the master device and sent to the slave device. The output terminal OUT of the logic circuit 21 outputs a clock signal, the input terminal IN of the logic circuit 21 monitors the clock signal on SCL, and the input terminal IN captures a feedback signal corresponding to the clock signal, which may also be referred to as a monitor signal. Typically, the feedback signal may be delayed by N clock cycles (N typically being 1-2) from the clock signal output at the output OUT by a corresponding timing control.

Since the clock signal output from the output OUT of the logic circuit 21 is known, it can be compared with the feedback signal monitored from the input IN, and whether there is a device abnormality on the I2C bus is determined according to the comparison result.

Specifically, the internal control logic of the logic circuit 21 compares the clock signal output by the output terminal OUT with the feedback signal obtained by the input terminal IN, and if the output of the output terminal OUT is 1, but the feedback signal monitored by the input terminal IN is 0 and lasts for a certain time, it indicates that the master device is normal, and the slave device pulls down the bus abnormally. Further, if the delayed signal of the clock signal output by the OUT is consistent with the clock signal but remains 1 or 0 for a long time, it indicates that the master device is abnormal.

Based on the foregoing principle, a flowchart of a method for monitoring I2C bus communication abnormality according to the embodiment of the present application is shown in fig. 3, and includes the following steps:

step 301, acquiring a clock signal sent by the master device to the slave device.

Step 302, obtaining a feedback signal corresponding to the clock signal on the SCL.

It should be noted that, through the corresponding timing control, the feedback signal may be delayed by a certain period than the clock signal, for example, by 1-2 clock periods. That is, the feedback signal refers to a monitoring signal acquired on the SCL after the master device transmits the clock signal and delays for a certain period.

In the embodiment of the present application, the clock signal is a clock signal that is transmitted by the master device and transmitted on the SCL. The feedback signal corresponding to the clock signal refers to a signal on the SCL monitored by the master device after sending the clock signal. That is, the clock signal is actually sent by the master device, and the feedback signal is the actual signal on SCL delayed by a certain period after the master device sends the clock signal.

Step 303, determining an abnormal device by comparing the clock signal and the feedback signal.

If the master device and the slave device are normal, the feedback signal is consistent with the clock signal, but if the slave device is abnormal, the feedback signal is inconsistent with the clock signal. Specifically, a clock signal sent by the master device to the slave device is compared with a feedback signal corresponding to the clock signal on the SCL, and if the feedback signal is 0 when the clock signal is 1 and lasts for a certain time (usually in the order of seconds, such as 2-3 seconds), it is determined that the slave device is abnormal.

Further, in another non-limiting embodiment of the method for monitoring the I2C bus communication abnormality, the abnormal device can be determined by comparing the delay signal of the clock signal with the clock signal. Specifically, if the delayed signal of the clock signal is consistent with the clock signal but remains unchanged for a certain time (for example, 2-3 clock cycles), it is determined that the master device is abnormal.

It should be noted that the delay signal may be delayed by a certain clock period, for example, by 1-2 clock periods, compared with the clock signal.

Further, if the slave device is abnormal, the specific slave device can be judged according to the slave device address stored in the current register.

According to the method for monitoring the I2C bus communication abnormity, whether the slave device is abnormal on the I2C bus can be quickly judged by acquiring the clock signal sent by the master device to the slave device and monitoring the feedback signal which is transmitted on the SCL and corresponds to the clock signal. Further, whether the master device is abnormal or not can be determined by comparing the delay signal of the clock signal with the clock signal.

In another non-limiting embodiment of the method for monitoring the I2C bus communication abnormality, an interrupt signal may be generated when a device abnormality is detected on I2C, and the I2C bus communication may be controlled according to the interrupt signal.

As shown in fig. 4, it is a flowchart of controlling I2C bus communication according to an interrupt signal in the embodiment of the present application, and includes the following steps:

in step 401, the master device and the slave device start communication.

At step 402, a determination is made as to whether the I2C bus communication is normal. If so, go to step 403; otherwise, step 404 is performed.

In step 403, normal communication is performed.

Step 404, reading the interrupt signal, and determining an abnormal device according to the interrupt signal. If the slave device is abnormal, executing step 405; if it is a master exception, step 406 is performed.

Step 405, the communication is ended.

At step 406, the master device is reset and then returns to step 401.

In a specific application, the reset of the master device can be performed for multiple times, if the abnormality of the master device is still detected after the multiple times of reset, it indicates that the abnormality of the master device cannot be eliminated through the reset operation, at this time, the communication can be ended, and then the master device is checked through other modes.

It should be noted that, in a specific application, the method for monitoring the I2C bus communication abnormality according to the embodiment of the present application may be implemented by a combination of hardware and software. For example, the interrupt signal is written into an interrupt register, and the interrupt register is read to determine whether there is a device exception, and whether it is a master exception or a slave exception.

Correspondingly, an apparatus for monitoring I2C bus communication abnormality is further provided in the embodiments of the present application, as shown in fig. 5, which is a schematic structural diagram of the apparatus for monitoring I2C bus communication abnormality in the embodiments of the present application.

In this embodiment, the apparatus 500 includes a clock signal obtaining module 501, a feedback signal obtaining module 502, and a first determining module 503. Wherein:

the clock signal acquiring module 501 is configured to acquire a clock signal sent by a master device to a slave device;

the feedback signal acquiring module 502 is configured to acquire a feedback signal corresponding to the clock signal on an SCL;

the first determining module 503 is configured to determine an abnormal device by comparing the clock signal and the feedback signal, and specifically, determine that a slave device is abnormal when the feedback signal is 0 when the clock signal is 1 and lasts for a certain time.

Further, in another non-limiting embodiment of the present application, a device for monitoring I2C bus communication anomalies, the device may further comprise: and a second determining module (see the later embodiment shown in fig. 8), configured to determine that the master device is abnormal when the delay signal of the clock signal is consistent with the clock signal but remains unchanged for a certain time.

In this embodiment, the first determining module 503 may determine whether there is an abnormality of a slave device on the I2C bus according to a comparison between the clock signal and the corresponding feedback signal. After determining that the slave device is abnormal, it may further locate which slave device is abnormal, for example, it may be determined by software reading the slave device address stored in the current register, which slave device is abnormal specifically. Of course, other determination methods in the prior art may also be adopted, and the embodiment of the present application is not limited.

The first determining module 503 may be implemented by pure hardware, for example, in a non-limiting embodiment, the first determining module 503 is configured to determine that the slave device is abnormal if the feedback signal is 0 and lasts for a certain time while the clock signal is 1.

The working principle of the first determining module and the second determining module in the embodiment of the present application is described in detail below with reference to fig. 6 and 7.

Fig. 6 is a schematic structural diagram of a first determining module in the apparatus for monitoring I2C bus communication abnormality according to the embodiment of the present application.

In this embodiment, the first determining module includes: a first delay 61, an inverter 62, a first and gate 63, and a first timer 64. The first and gate 63 has three input ends, wherein one input end inputs the I2C working state signal, the other two input ends are respectively connected with the output end of the first delayer 61 and the output end of the inverter 62, and the output end of the first and gate 63 is connected with the input end of the first timer 64; the output of the first and gate 63 is connected to the input of a first timer 64.

Wherein:

the first delayer 61 is used for inputting the clock signal;

the inverter 62 is used for inputting the feedback signal;

the first and gate 63 is configured to output a high level to trigger the first timer 64 to start timing when the clock signal is 1 and the feedback signal is 0;

the first timer 64 is used for outputting a slave device abnormality indication signal after the timed time reaches a set first duration.

The I2C operation status signal, i.e. the I2C _ busy signal in fig. 6, is used to indicate that the I2C bus is in an operation status, which is different from the I2C idle status signal, i.e. the master device and the slave device on the I2C bus are in communication. According to the scheme, only when the I2C is in a working state, whether the device on the I2C bus is abnormal or not is detected.

In a specific application, when the I2C bus is in an active state, the I2C _ busy signal may be set to 1, and when the I2C bus is in an idle state, the I2C _ busy signal may be set to 0.

Referring to fig. 6, the working logic of the first judging module is as follows:

the I2C bus is IN busy state, i.e. the I2C bus is working, because the IN signal (i.e. the feedback signal) will be delayed by 1-2 clock cycles than the OUT signal (i.e. the clock signal), the OUT signal will be delayed by 1-2 clock cycles to match with the IN signal, then the IN signal and the OUT signal are compared, when the OUT signal is output as 1, the IN signal is monitored to be 0, the first timer 64 will be triggered to count time, when the set time (the time is set by the chip manufacturer according to the actual situation, such as 2S) is reached, the slave device is judged to be abnormal, and the first timer 64 outputs the slave device abnormal indication signal.

Fig. 7 is a schematic structural diagram of a second determining module in the apparatus for monitoring I2C bus communication abnormality according to the embodiment of the present application.

In this embodiment, the second determining module includes: a second delay 71, an xor gate 72, a second and gate 74, and a second timer 75. Wherein, the output end of the second delay 71 is connected with one input end of the xor gate 72; the other input terminal of the exclusive nor gate 72 inputs the clock signal; the second and gate 74 has two input terminals, one of which inputs the I2C operation status signal, and the other of which is connected to the output terminal of the xor gate 72; the output of the second and gate 74 is connected to the input of a second timer 75. Wherein:

the second delay 71 is used for inputting the clock signal;

the second and gate 74 is configured to output a high level to trigger the second timer 75 to start timing if the feedback signal is consistent with the clock signal;

the second timer 75 is configured to output a master device abnormality indication signal after the counted time reaches a set second duration.

Referring to fig. 7, the operating logic of the second judging module is as follows:

the I2C bus is in busy state, that is, the I2C bus is working, comparing whether the signal is consistent with the signal in the last clock cycle before and after the OUT signal, because the SCL signal is a periodic 0/1 jump, as long as the signal is consistent with the signal in the last cycle after delaying one clock cycle, the second timer 75 starts to be triggered to start timing, and after the set time (for example, the time can be set to be 2-3 cycles), it is determined that the master device is abnormal, and the second timer 75 outputs a master device abnormal indication signal.

It should be noted that the timing lengths of the first timer 64 and the second timer 75, i.e., the first length and the second length, may be set to be the same or different, and the embodiment of the present application is not limited thereto.

In addition, it should be noted that, in order to reset the first timer 64 and the second timer 75 after the timing length is reached, the following signals are detected continuously. As shown in fig. 6 and 7, the first timer 64 and the second timer 75 are reset by the

respective reset inverters

60, 70, respectively.

Fig. 8 is a schematic structural diagram of an apparatus for monitoring I2C bus communication abnormality according to an embodiment of the present application.

Unlike the embodiment shown in fig. 5, in this embodiment, the apparatus 500 further includes a second determining module 505 and a control module 504.

In this embodiment, the slave device abnormality indication signal and the master device abnormality indication signal are interrupt signals, and the interrupt signals are generated by the first determining module 503 and the second determining module 505, for example, when the first determining module 503 determines that a slave device is abnormal, the first determining module outputs corresponding signals to the first I/O port of the control module 504; similarly, when the second determining module 505 determines that the master device is abnormal, it outputs a corresponding signal to the second I/O port of the control module 504. Wherein the first I/O port and the second I/O port are not specific I/O ports, but are different I/O ports.

Correspondingly, the control module 504 is configured to control I2C bus communication according to the interrupt signal, specifically, read the interrupt signal when I2C bus communication is abnormal, and reset the master device if the interrupt signal indicates that the master device is abnormal; and if the interrupt signal indicates that the slave equipment is abnormal, ending the communication.

It should be noted that the reset operation of the control module 504 on the master device may be repeated multiple times (generally less than 5 times). For example, the control module 504 forcibly resets the master device through software, and notifies the upper layer caller to re-initiate a communication, and then continues the communication; if the communication is abnormal again, continuing to read the interruption condition, if the communication is abnormal again, continuing to reset the main equipment and informing an upper layer caller to re-initiate the communication, and then continuing the communication; if the master device is always abnormal, the software can forcibly reset the master device for N times (the N times are generally less than 5 times); if the master device is detected again as abnormal, the communication is ended.

In a specific application, the device for monitoring the I2C bus communication abnormality according to the embodiment of the present application may be disposed in a master device.

The device for monitoring I2C bus communication abnormity provided by the embodiment of the application can rapidly judge whether equipment on an I2C bus is abnormal or not by acquiring the clock signal sent by the master equipment to the slave equipment and monitoring the feedback signal transmitted on the SCL and corresponding to the clock signal, and further can determine abnormal equipment by comparing the delay signal of the clock signal with the clock signal, thereby facilitating the investigation of I2C bus system abnormal conditions.

In a specific implementation, the device for monitoring the I2C bus communication abnormality may correspond to a Chip with a corresponding function in the terminal device, such as a System-On-a-Chip (SOC), a baseband Chip, a Chip module, and the like.

In a specific implementation, each module/unit included in each apparatus and product described in the foregoing embodiments may be a software module/unit, may also be a hardware module/unit, or may also be a part of a software module/unit and a part of a hardware module/unit.

For example, for each device or product applied to or integrated into a chip, each module/unit included in the device or product may be implemented by hardware such as a circuit, or at least a part of the module/unit may be implemented by a software program running on a processor integrated within the chip, and the rest (if any) part of the module/unit may be implemented by hardware such as a circuit; for each device or product applied to or integrated with the chip module, each module/unit included in the device or product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least some of the modules/units may be implemented by using a software program running on a processor integrated within the chip module, and the rest (if any) of the modules/units may be implemented by using hardware such as a circuit; for each device and product applied to or integrated in the terminal, each module/unit included in the device and product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program running on a processor integrated in the terminal, and the rest (if any) part of the modules/units may be implemented by using hardware such as a circuit.

Correspondingly, the embodiment of the application also provides an I2C master device, and the device comprises the device for monitoring the I2C bus communication abnormity.

Accordingly, the present application also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transitory storage medium, and stores thereon a computer program, which is executed by a processor to perform the steps in the above-mentioned method embodiments.

Correspondingly, the embodiment of the present application further provides an apparatus for monitoring I2C bus communication abnormality, which includes a memory and a processor, where the memory stores a computer program executable on the processor, and the processor executes the steps in the above-mentioned method embodiments when executing the computer program.

It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein indicates that the former and latter related objects are in an "or" relationship.

The "plurality" appearing in the embodiments of the present application means two or more.

The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for illustrating and differentiating the objects, and do not represent the order or the particular limitation of the number of the devices in the embodiments of the present application, and do not constitute any limitation to the embodiments of the present application.

Embodiments provided herein may be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. The procedures or functions described in accordance with the embodiments of the present application are produced in whole or in part when the computer instructions or the computer program are loaded or executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus and system may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative; for example, the division of the unit is only a logic function division, and there may be another division manner in actual implementation; for example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be physically arranged separately, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

Although the present application is disclosed above, the present application is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present disclosure, and it is intended that the scope of the present disclosure be defined by the appended claims.

Claims

1. A method for monitoring communication abnormality of an I2C bus, wherein a master device and at least one slave device are connected to the I2C bus, the method comprising:

acquiring a clock signal sent by a master device to a slave device;

acquiring a feedback signal corresponding to the clock signal on an SCL;

2. The method of claim 1, wherein the feedback signal is delayed from the clock signal by a period.

3. The method of claim 1, wherein the determining an anomalous device by comparing the clock signal and the feedback signal comprises:

and if the feedback signal is 0 when the clock signal is 1 and lasts for a certain time, determining that the slave device is abnormal.

4. The method of claim 3, further comprising:

and if the delay signal of the clock signal is consistent with the clock signal but keeps unchanged for a certain time, determining that the master equipment is abnormal.

5. The method according to any one of claims 1 to 4, further comprising:

generating an interrupt signal under the condition that the equipment abnormality is detected;

and controlling the I2C bus communication according to the interrupt signal.

6. The method of claim 5, wherein the controlling I2C bus communications according to the interrupt signal comprises:

reading the interrupt signal when the I2C bus communication is abnormal;

if the interrupt signal represents that the main equipment is abnormal, resetting the main equipment; and if the interrupt signal indicates that the slave equipment is abnormal, ending the communication.

7. An apparatus for monitoring I2C bus communication abnormality, a master device and at least one slave device are connected to the I2C bus, the apparatus comprising:

8. The apparatus of claim 7, wherein the feedback signal is delayed from the clock signal by a period.

9. The apparatus of claim 7,

the first determining module is specifically configured to determine that the slave device is abnormal when the feedback signal is 0 and lasts for a certain time when the clock signal is 1.

10. The apparatus of claim 9, wherein the first determining module comprises: the first time delay device, the inverter, the first AND gate and the first timer; the first AND gate is provided with three input ends, wherein one input end inputs an I2C working state signal, the other two input ends are respectively connected with the output end of the first delayer and the output end of the phase inverter, and the output end of the first AND gate is connected with the input end of the first timer; the output end of the first AND gate is connected with the input end of the first timer;

the first delay is used for inputting the clock signal;

the inverter is used for inputting the feedback signal;

11. The apparatus of any one of claims 7 to 10, further comprising:

and the second judgment module is used for determining that the master equipment is abnormal under the condition that the delay signal of the clock signal is consistent with the clock signal but keeps unchanged for a certain time.

12. The apparatus of claim 11, wherein the second determining module comprises: the second delayer, the exclusive-nor gate, the second AND gate and the second timer; the output end of the second delayer is connected with one input end of the exclusive nor gate; the other input end of the exclusive-nor gate inputs the clock signal; the second AND gate is provided with two input ends, wherein one input end inputs an I2C working state signal, and the other input end is connected with the output end of the XOR gate; the output end of the second AND gate is connected with the input end of the second timer;

the second delay is used for inputting the clock signal;

13. The apparatus of claim 12, wherein the slave device exception indication signal and the master device exception indication signal are interrupt signals; the device further comprises:

and the control module is used for controlling the I2C bus communication according to the interrupt signal.

14. The apparatus of claim 13,

the control module is specifically configured to read the interrupt signal when the I2C bus communication is abnormal, and reset the master device if the interrupt signal indicates that the master device is abnormal; and if the interrupt signal indicates that the slave equipment is abnormal, ending the communication.

15. An I2C master device, characterized in that the device comprises means for monitoring I2C bus communication anomalies as claimed in any one of claims 7 to 14.

16. A computer-readable storage medium, being a non-volatile storage medium or a non-transitory storage medium, having a computer program stored thereon, which, when executed by a processor, causes the method of any of claims 1 to 6 to be performed.

17. An apparatus for monitoring I2C bus communication anomalies, comprising a memory and a processor, the memory having stored thereon a computer program operable on the processor, wherein the processor, when executing the computer program, causes the method of any of claims 1 to 6 to be performed.