JP2001122700A - Semiconductor wafer, method of producing light emitting diode, and method and device for evaluating fracture strength of semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor wafer almost free from the formation of cracks or the like and a method of evaluating fracture strength which is capable of evaluating the difficulty of crack formation in the semiconductor wafer. SOLUTION: The grain sizes of abrasive materials to be used are optimized according to the kinds of the abrasive materials so that the means length of micro-cracks MC formed along the cleavage plane of a lapped surface 14b becomes <=1 μm. Thereby, the frequency of occurrence of cracks or the like in a semiconductor wafer 14 is markedly suppressed. The most optimized particle size of the abrasive material for making the mean length of the micro-cracks MC within the range mentioned above is >=#2,000 and <=#3,000 when a green silicon carbide fine powder abrasive material is used and is >=#1,200 and <=#2,000 when an artificial abrasive material is used. The easiness of crack formation in the semiconductor wafer 14 can be evaluated by allowing a ball to naturally fall onto the main surface 14a of the semiconductor wafer 14 and measuring the height of a position from where the ball is allowed to fall and causes cracks on the semiconductor wafer 14. As the easiness of the crack formation in the semiconductor wafer 14 by an outer face can be quantitatively grasped by this method, it becomes possible to produce or select the semiconductor wafer 14 hard to be cracked.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor wafer,
The present invention relates to a method for manufacturing a light emitting diode, a method for evaluating the breaking strength of a semiconductor wafer, and a device for evaluating the breaking strength of a semiconductor wafer.

[0002]

2. Description of the Related Art A light emitting diode is an element that directly converts electric energy into light by passing a forward current through a pn junction of a semiconductor. A group III-V compound semiconductor single crystal has a band gap corresponding to the wavelength of ultraviolet light or infrared light, and thus is often used as a material for a light emitting diode. Among them, gallium phosphide (GaP) -based light-emitting diodes that emit light from red to green and gallium arsenide (GaAs) -based light-emitting diodes that emit light from infrared to yellow are particularly widely used.

[0003] Light emitting diodes are usually sliced from compound semiconductor single crystal rods such as gallium phosphide or gallium arsenide.
A compound semiconductor epitaxial wafer having a pn junction by growing a plurality of epitaxial layers in a liquid phase or a vapor phase on a compound semiconductor single crystal substrate (hereinafter sometimes simply referred to as “substrate”) obtained by polishing. (Hereinafter sometimes simply referred to as “epitaxial wafer”). Subsequently, a metal exhibiting low contact resistance is vacuum-deposited on each of the p-side and n-side main surfaces of the epitaxial wafer, and further heat-treated to form an electrode. After formation, the epitaxial wafer is manufactured by cutting into chips and separating. Hereinafter, when the compound semiconductor single crystal substrate and the compound semiconductor epitaxial wafer are collectively referred to, they are referred to as a compound semiconductor wafer.

[0004] "Semiconductor wafer" is a general term for compound semiconductor wafers and silicon wafers. Further, “silicon wafer” is a general term for a silicon single crystal substrate and a silicon epitaxial wafer formed by forming an epitaxial layer on the silicon single crystal substrate.

[0005] In the manufacturing process of the light emitting diode, in order to improve the light extraction efficiency of the light emitting diode or to meet the demand for thinning along with the miniaturization of the light emitting diode, an epitaxial wafer is formed before the electrode is formed. 2. Description of the Related Art A substrate on the main back side is thinned by lapping. Further, the substrate on the main rear surface side of the epitaxial wafer may be completely removed.

In the lapping of the main back surface of the epitaxial wafer, a slurry (Slurry) obtained by mixing a pH-adjusted aqueous solution and abrasive grains is disposed between the lapping plate and the epitaxial wafer, and a load is applied to the epitaxial wafer. This is performed by rotating the lapping plate while adding the abrasive, and shaving the main back surface of the epitaxial wafer by rolling and scratching of the abrasive grains.

Conventionally, lapping of such a compound semiconductor epitaxial wafer has a particle size of # 800 to # 1.
200 GC abrasive grains (green silicon carbide-based abrasive) are used. Silicon carbide-based abrasives are obtained by sufficiently mixing silica or silica sand and a carbon material such as coke with auxiliary raw materials such as industrial salts, and then heating and reacting at 1700 ° C. to 2200 ° C. in an electric resistance furnace. It is produced by finely pulverizing the silicon carbide crystal obtained by the method described above. As such a silicon carbide-based abrasive, in addition to the GC abrasive, a C abrasive having a higher purity (black silicon carbide-based abrasive) is also known.

By the way, the grain size of abrasive grains used for lapping is often determined empirically from the processing accuracy and productivity. The grain size of the abrasive grains is specified by the number (#) by the sedimentation test method or the electric resistance test method in the Japanese Industrial Standard R6002 abrasive particle size test method (revised on December 1, 1987). In the lapping of the compound semiconductor epitaxial wafer, GC abrasive grains having a relatively coarse particle size of # 800 to # 1200 are used. This is because the hardness of SiC is practically the second highest after diamond and lapping can be performed efficiently.

[0009]

However, according to the study of the present inventors, the mechanical strength of an epitaxial wafer after lapping, specifically, the generation of cracks, depends on the grain size of abrasive grains used for lapping. It turned out that the difficulty was greatly affected. In particular, particle sizes # 800 to # 1
In the case of using 200 GC abrasive grains, when lapping the back surface of the epitaxial wafer, or when cutting and separating the epitaxial wafer on which the electrodes are further formed into chips, chipping or cracking occurs in the epitaxial wafer. It turned out that there was a problem that became easier.

Also, a compound semiconductor single crystal substrate, especially Ga
A substrate used for manufacturing an epitaxial wafer for a P-based light emitting diode is as thin as about 250 μm. Furthermore, in recent years, epitaxial wafers having a thickness of 200 μm or less have been introduced into the manufacturing process of light-emitting diodes due to miniaturization of light-emitting diodes, and the frequency of occurrence of cracks due to external force has increased more and more.

However, the easiness of cracking of the compound semiconductor wafer could not be quantitatively measured under the same conditions, so that a specific analysis of the easiness of cracking of the wafer could not be performed. For example, an attempt has been made to use the frequency of occurrence of cracks in the process as an index for the easiness of cracking, but there have been problems such as large errors and difficulty in preparing the same conditions for samples.

An object of the present invention is to provide a semiconductor wafer that is unlikely to crack, a method of manufacturing a light-emitting diode using the semiconductor wafer, a method of evaluating a fracture strength that can evaluate the difficulty of cracking of a semiconductor wafer, and a method of using the same. Another object of the present invention is to provide a strength evaluation device.

[0013]

In order to solve the above-mentioned problems, a semiconductor wafer according to the present invention is a semiconductor wafer having a lapping surface which is a lapping surface. Is characterized in that the average length of the cracks occurring along the length is 1 μm or less.

The present inventors have conducted various investigations on the factors governing the mechanical strength of a semiconductor wafer having a lapping surface, and have found that the processing conditions for forming the lapping surface,
Specifically, it was found that the length of a crack generated along the cleavage plane on the lapping surface was significantly changed depending on the type and the grain size of the abrasive used for the lapping process. As a result of further intensive studies, as a result, the average length of the cracks generated along the cleavage plane is 1 μm or less.
By optimizing the particle size according to the type of abrasive used, the mechanical strength of the semiconductor wafer is significantly improved, specifically, when an external force such as an impact is applied,
The inventors have found that the frequency of occurrence of cracks and the like in a semiconductor wafer is significantly reduced, and have completed the present invention. Cleavage means that crystals are easily broken in a certain direction,
This refers to creating a smooth surface, that is, a cleavage plane. Crystals of the same species are recognized regardless of the individual (ie, wafer)
The index of the cleavage interface is also substantially constant. For example, GaP or GaAs
In the case of a group III-V compound semiconductor single crystal and a zinc blende structure as in s, the cleavage plane is a {110} plane.

[0015] The effect of the present invention is particularly remarkably exhibited because the cleavage fracture mechanism particularly tends to cause cracks and the like.
-In the field of semiconductor wafers using Group V compound semiconductor single crystal substrates. As such a semiconductor wafer, a III-V having a main surface with a plane orientation of approximately (111), which is widely used in the manufacture of electronic components such as light-emitting diodes.
A group compound semiconductor epitaxial wafer, for example, a wafer in which an epitaxial layer is formed on a gallium phosphide single crystal substrate can be exemplified. Note that the abbreviation (111) means
The horizontal angle with respect to the (111) plane is 0 (zero) or within several degrees. Such an epitaxial wafer has two main surfaces. For example, an epitaxial layer is formed on the main surface side, and the main back surface is processed as a lapping surface. On the main back surface, by selecting the type and particle size of the abrasive so that the length of the cracks generated along the cleavage plane is within the above range, for example, during the lapping process, or further, the electrode When cutting and separating the epitaxial wafer formed with the chips into chips, the frequency of occurrence of chips and cracks can be significantly reduced, and the product yield can be improved.

The optimum grain size of the abrasive for keeping the average length of cracks generated along the cleavage plane in the above range depends on the type of abrasive used. For example,
When a green silicon carbide based fine abrasive is used, the particle size is # 20.
It is preferable to set the value between 00 and # 3000. It is also possible to use so-called artificial emery as an abrasive, and in this case, the particle size is preferably from # 1200 to # 2000. "Emery" is the name of a natural mineral originally having a mixed structure of corundum and magnetite, but artificial emery is a corundum crystal or mullite crystal obtained by smelting and reducing an alumina material in an electric resistance furnace. Refers to a synthetic material mainly composed of As an example,
There is a composite artificial emery in which brown alumina-based abrasive grains and zircon-based abrasive grains are mixed, and these are also called FO abrasive grains. As described above, the particle size of the abrasive (abrasive) is determined by the method of testing the particle size of the Japanese Industrial Standard R6002 abrasive (Showa 62).
(Revised on December 1, 2000), the value measured by the sedimentation test method or the electric resistance test method is adopted.

When any of the above abrasives is used, if the grain size is larger than the upper limit (in the case of the count (#), it is smaller than the lower limit), cracks that occur along the cleavage plane are reduced. It is difficult to reduce the average length to 1 μm or less, and cracks and the like are very likely to occur. When the particle size is less than the lower limit (exceeding the upper limit in terms of the count (#)),
The speed of lapping polishing is too low, and the efficiency is greatly reduced.

For example, when a light emitting diode is manufactured using a compound semiconductor single crystal substrate, the following method is possible according to the present invention. First, an epitaxial layer is grown on the main surface of the compound semiconductor single crystal substrate (epitaxial layer growth step). Next, lapping processing is performed on the main back surface of the compound semiconductor single bonding uppermost substrate (lapping processing step).
At this time, a green silicon carbide based fine abrasive having a particle size of # 2000 or more and # 3000 or less, or a particle size of # 1200 or more #
By using an artificial emery abrasive of 2000 or less, the average length of cracks generated along the cleavage plane on the lapping plane can be kept to 1 μm or less. And
After the lapping process, necessary electrodes are formed (electrode forming process).

Next, in the method for evaluating the breaking strength of a semiconductor wafer according to the present invention, the sphere is naturally dropped on the main surface of the semiconductor wafer, and the semiconductor wafer is easily broken based on the sphere drop starting position when the semiconductor wafer is broken. It is characterized by evaluating the In addition, the semiconductor wafer breaking strength evaluation apparatus of the present invention provides a semiconductor wafer having one principal surface (for example, a principal surface).
Holds the semiconductor wafer so that it faces upward, naturally drops the sphere toward the upper surface of the held semiconductor wafer, and includes a drop start position adjuster for adjusting the drop start position of the sphere. The susceptibility of the semiconductor wafer to cracking is evaluated based on the sphere drop start position at which cracks begin to occur. According to this evaluation method / apparatus, the susceptibility of the semiconductor wafer to external force cracking can be quantitatively grasped, so that a semiconductor wafer that is difficult to crack can be manufactured or sorted.

More specifically, the above-described semiconductor wafer breaking strength evaluation apparatus comprises: a semiconductor wafer holder made of an elastic material, which holds a first main surface side of a semiconductor wafer; It is arranged above the semiconductor wafer held by, is inserted from the upper opening, and naturally falls from the lower opening toward the second main surface of the semiconductor wafer while guiding the inserted sphere. And a drop height measuring instrument for measuring the drop height of the sphere from the drop start position. One of the main surface and the main back surface is a first main surface, and the other is a second main surface.

By using an elastic material for the semiconductor wafer holder, for example, a relatively soft elastic material such as silicone rubber, the collision form between the held semiconductor wafer and the sphere is made inelastic, and the impact force of the fall is reduced by the semiconductor. It can be efficiently converted into the breaking force of the wafer. Further, since the drop start position can be defined by the position of the upper opening of the drop tube by using the charging tube, it is possible to reduce variation in the drop start position due to an artificial factor. These make it possible to evaluate the breakdown strength of the semiconductor wafer with high reliability.

The breaking strength evaluation apparatus of the present invention can be used not only for measuring the breaking strength of a compound semiconductor wafer but also for measuring the breaking strength of a silicon wafer.

[0023]

Embodiments of the present invention will be described below with reference to the accompanying drawings. Here, a light emitting diode, a method for manufacturing the light emitting diode, and a device for evaluating breaking strength according to the present invention will be described in detail. First, a compound semiconductor epitaxial wafer is manufactured according to the process shown in FIG. That is, a compound semiconductor single crystal substrate (hereinafter also simply referred to as a substrate) 51 obtained by slicing and polishing a III-V group compound semiconductor single crystal rod such as gallium phosphide (GaP) or gallium arsenide (GaAs) is prepared. . This substrate 51 is substantially (1 °) within an off-angle of ± 1 °.
11) having a plane orientation of, for example, 200 to 500 μm in thickness
The carrier concentration is adjusted to a predetermined value so as to indicate the first conductivity type (for example, n-type). Next, as shown in FIG. 1B, a first epitaxial layer 55 is grown on the main surface of the substrate 51. This epitaxial growth may be performed by either the liquid phase growth method or the vapor phase growth method. Here, the case of using the liquid phase growth method will be described as an example.

That is, as shown in FIG. 1A, a liquid-phase epitaxial growth apparatus 50 composed of a quartz boat or the like is used.
The substrates 51 are attached to both sides of each substrate holding plate 52 so that the main surface faces outward. In this state, a melt of a growth material is introduced into the liquid phase epitaxial growth apparatus 50 to form a first epitaxial layer 55 on the main surface of each substrate 51. Usually, the substrate 51 is not a perfect single crystal but often contains some lattice defects such as dislocations. In this case, the first epitaxial layer 55 is
If a lattice defect such as a dislocation moving from the side is absorbed, or if a lattice constant mismatch exists between the substrate 51 and the substrate 51, the layer serves as a buffer layer for alleviating the mismatch. On the other hand, assuming that the carrier concentration between the substrate 51 and the later-described second epitaxial layer 56 does not become too steep, the carrier concentration is intermediate between the two.
The first epitaxial layer 55 may be formed.

Subsequently, as shown in FIGS. 1C and 1D, the second epitaxial layer 56 and the third epitaxial layer 57 are similarly epitaxially grown. In each of the second and third epitaxial layers 56 and 57, a dopant of the second conductivity type (for example, p-type) different from the substrate 51 and the first epitaxial layer 55 is set to have a predetermined carrier concentration. Has been added. The second epitaxial layer 56 forms a pn junction with the first epitaxial layer 55. In addition, the third epitaxial layer 57 is used to reduce the contact resistance between the third epitaxial layer 57 and a metal electrode to be formed thereafter (for example, an ohmic contact).
The carrier concentration is set higher than that of the second epitaxial layer 56. Thus, epitaxial wafer 14 having three epitaxial layers 55 to 57 formed on main surface 14a side of compound semiconductor single crystal substrate 51 is obtained.

Next, as shown in FIG. 3, the substrate 51 located on the main back side 14b of the epitaxial wafer 14 is
By lapping processing, the thickness is, for example, 20
The thickness is reduced to about 0 to 300 μm. In this lapping process, as shown in FIG. 2, a slurry SL obtained by mixing an aqueous solution LQ whose pH has been adjusted and abrasive grains PG is disposed between a lapping plate 34 and the epitaxial wafer 14. Is performed by rotating the lapping plate 34 while applying a load to the main surface 14b (FIG. 3) of the epitaxial wafer by rolling and scratching the abrasive grains PG. Here, in order to polish the main back side of the epitaxial wafer 14 on one side,
A lap master type lapping machine is used. Several rings 33 are placed on a lapping plate 34, the epitaxial wafer 14 is arranged inside the rings 33, and a load is applied by the weight 30. Reference numeral 31 indicates a center roller, and reference numeral 3
Reference numeral 2 denotes a guide roller, both of which are in contact with the outer peripheral surface of the ring 33 and serve to rotate the ring 33 as the lap plate 34 rotates. The slurry SL containing the abrasive grains PG is supplied from the slurry supply nozzle 35 onto the lapping plate 34. The abrasive PG is, for example, a green silicon carbide-based fine abrasive (so-called GC abrasive) having a particle size of # 2000 to # 3000, or a particle size of # 1200 to # 200.
Zero or less artificial emery abrasive (so-called FO abrasive grains) is used.

When the lapping of the main back side is completed,
As shown in FIG. 4, the first electrode 60 is provided on the main back surface 14b (that is, the substrate 51 side), and the main surface 14a (that is, the main surface 14a).
A second electrode 61 on the surface of the third epitaxial layer 57);
Each is formed by vacuum vapor deposition of a metal such as gold or aluminum (after the vapor deposition, heat treatment may be appropriately performed for the purpose of improving the ohmic contact of the electrode, etc.), and further, as shown in FIG. Is cut and separated into chips 64 by a dicing device or the like (the substrate 51 before cutting).
And portions derived from the epitaxial layers 55 to 57 are shown by adding “′” to the corresponding reference numerals, respectively). Each of the chips 64 becomes a light emitting diode product through a lead wire attaching process, a molding process, and the like.

FIG. 9 is a schematic explanatory view of a fracture strength evaluation apparatus according to the present invention. The fracture strength evaluation device 10 is for quantitatively evaluating the crack impact resistance of the lapping-processed epitaxial wafer 14 (an embodiment of a semiconductor wafer; hereinafter, also referred to as a semiconductor wafer 14), A gantry 11 is provided. An underlaying plate 12 (for example, having a thickness of 10 mm) made of a hard resin (for example, an acrylic resin) is disposed on the gantry 11, and a mat 13 as a semiconductor wafer holder is further disposed thereon. The mat 13 is made of an elastic material such as rubber, here made of silicone rubber, and has a thickness of, for example, about 5 mm. This mat 1
The semiconductor wafer 14 to be evaluated is placed on the main surface 1
4a is placed almost horizontally (that is, when the impact force is applied from the upper surface side, the lower surface side that becomes the state of tensile bending stress becomes the lapping surface (main back surface) 14b).

A column 15 is provided on the upper surface of the gantry 11 so as to rise substantially vertically, and a horizontal arm 18 is attached so as to be able to move up and down along the column 15 and to hold an arbitrary position. Specifically, the base end of the horizontal arm 18 is attached to a slider 21 that can move up and down along the column 15. The slider 21 is fixed at an arbitrary position on the column 15 by a drop height adjusting screw 19 that is screwed into the outer surface of the column 15 through its wall. Horizontal arm 1
Numeral 8 extends from the slider 21 toward a position above the semiconductor wafer 14 on the mat 13, and a glass input tube 16 is attached substantially vertically to a position near the front end thereof. The injection tube 16 is inserted with a sphere, for example, a glass sphere 17 from the upper opening 16a, and guides the inserted glass sphere 17 to the lower opening 16b.
From the semiconductor wafer 14 toward the semiconductor wafer 14. The length of the charging pipe 16 from the upper opening 16a to the lower opening 16b is L.

Loosen the drop height adjusting screw 19 and move the slider 2
When the arm 1 is moved up and down along the column 15, the horizontal arm 18 and the input pipe 16 also move up and down integrally with the slider 21. Thereby, the height direction position of the upper opening 16a of the input tube 16 that defines the drop starting height of the glass ball 17 can be arbitrarily changed. The distance D between the main surface of the semiconductor wafer 14 placed on the mat 13 and the lower opening 16b of the charging tube 16 can be read by the dial gauge 20. The dial gauge 20 forms an essential part of the drop height measuring device. For example, while the rack 22 is arranged on the outer surface of the column 15 along the height direction, the slider 2
On one side, a pinion 23 engaging with the pinion 23 is provided, and a slider 2
By instructing the dial gauge 20 on the rotational displacement of the pinion 23 due to the vertical movement of 1, the changed interval D can be immediately read when the height position of the slider 21 is changed.

The reason why the mat 13 made of silicone rubber is employed as a holder for the semiconductor wafer 14 is that the silicone rubber has a moderate elasticity and the semiconductor wafer 14 placed on the mat 13 and the glass sphere 17 which has fallen are used. The collision can be made an inelastic collision and the semiconductor wafer 1
This is because it is easy to place the 4 horizontally on the mat 13. When the glass sphere 17 completely collides with the semiconductor wafer 14, the energy of the glass sphere 17 is completely stored, so that the semiconductor wafer 14 is not cleaved.
Due to the inelastic collision, the mat 1 is made of an elastic body that can use the potential energy of the glass ball 17 immediately before dropping as much as possible to cleave the semiconductor wafer 14.
For example, an elastic body that is a collision close to a completely inelastic collision (that is, a collision in which the glass ball 17 hardly repels) is ideal.

At the time of measuring the breaking strength of the semiconductor wafer 14, for example, a glass bulb 17 having a diameter of 4 mm and a weight of 87 mg is used.
Is inserted through the upper opening 16a of the input tube 16, and is naturally dropped from the lower opening 16b so as to collide with the semiconductor wafer 14 substantially perpendicularly. When the semiconductor wafer 14 does not break, the position of the horizontal arm 18 is adjusted slightly higher and the measurement is performed again. This measurement is repeated until the semiconductor wafer 14 breaks. And the breaking strength of the semiconductor wafer 14 is
It can be expressed by the minimum drop height H required for the semiconductor wafer 14 to start cracking. Here, the drop height H
Is the length L of the input tube 16 and the semiconductor wafer 1
4 between the main surface of No. 4 and the lower opening 16b of the input pipe 16
And H = L + D ‥‥ (1).

The drop height H required for the measurement greatly varies depending on the type and size of the sphere used for the measurement. For example,
When the glass sphere 17 having a diameter of 4 mm and a weight of 87 mg is used for measuring the breaking strength of the compound semiconductor wafer 14, it is preferable that the drop height H can be varied in the range of 50 mm to 400 mm.

In place of the glass ball 17, for example, an iron ball or a lead ball may be used. However, since iron and lead have a higher specific gravity than glass, it is necessary to make the diameter considerably smaller than the glass sphere or lower the drop starting height.
For example, the semiconductor wafer 14 whose breakdown strength is to be measured
However, glass balls are used for compound semiconductor wafers that are relatively easy to break, and iron balls or lead balls are used for silicon wafers that are relatively hard to break. You may use them properly. In this case, as a parameter reflecting the potential energy of the sphere, for example, a value obtained by multiplying the drop height H by the mass M of the sphere to be used may be used as an index for evaluating the breaking strength.

The inventors of the present invention have invented the above-described fracture strength evaluation apparatus 10 shown in FIG. 9, and have measured the easiness of cracking of various compound semiconductor epitaxial wafers whose main and back surfaces have been lapped. Was. As a result, they found that the easiness of cracking differs depending on the grain size of the abrasive grains used in the lapping process. That is, it was found that the smaller the grain size of the abrasive grains, the easier the crack was, and conversely, the larger the grain size of the abrasive grains, the harder the wafer was to crack.

More specifically, a particle size of # 2000 or more and # 3
When the main back surface of the compound semiconductor epitaxial wafer was lapped using GC abrasive grains of 000 or less, cracking was difficult. On the other hand, when the GC abrasive grains having a grain size of # 240 or more and # 1500 or less were used, it was very easy to break. When GC abrasives having a particle size of # 4000 or more were used, it was found that the lapping speed was extremely slow, which was not suitable for production.

The main back surface of the compound semiconductor epitaxial wafer wrapped with an artificial emery abrasive (FO abrasive) having a grain size of # 1200 or more and # 2000 or less was hard to crack. On the other hand, when FO abrasive grains having a grain size of # 240 or more and # 1000 or less were used, they were very easily broken. When FO abrasive grains having a particle size of # 3000 or more are used, the lapping speed is extremely low, and thus the lapping rate is not suitable for production. Here, the FO abrasive is a composite artificial emery in which brown alumina-based abrasive and zircon-based abrasive are mixed.

Further investigation was carried out. With respect to the compound semiconductor epitaxial wafer, when the lapping surface (lapping surface) was enlarged and observed with a scanning electron microscope (SEM), for example, as shown in FIG. It was found that there were small cracks (hereinafter referred to as “microcracks”) having a length of 5 μm or less, which were generated by small cracks along the crystal.

In the following description, the crystal plane is expressed as (hkl) and the crystal axis is expressed as [hkl] using the Miller index. As described above, a negative sign indicating a negative exponent is generally put on the exponent.

[0040]

(Equation 1)

However, in the present specification, the above and are conveniently expressed as 'and' below. (H-kl) ‥‥‥ '[h-kl] ‥‥‥'

FIG. 6 shows a lapping surface (main back surface) 14 of a compound semiconductor epitaxial wafer having a plane orientation (111).
The surface state of b is conceptually shown. Micro crack MC is
(1-10), (01-1), and (-10)
1) It occurs in three directions along the plane, each at an angle of 120 °. Cleavage means that a crystal is easily broken in a certain direction to form a smooth surface, that is, a cleavage surface.
In the case of a group III-V compound semiconductor single crystal and a zinc-blende structure such as GaP or GaAs, the cleavage plane is {11}.
0 ° plane.

According to the study of the present inventors, the susceptibility of the compound semiconductor epitaxial wafer 14 to cracking is determined by the micro crack M generated along the cleavage plane on the main back surface.
Under the influence of the length of C, it was found that when the average length of the microcracks MC was 1 μm or less, the incidence of cracks was significantly reduced. That is, the length of the microcracks MC generated during the lapping process depends on the grain size of the abrasive grain used, and is a GC abrasive grain having a grain size of # 2000 to # 3000 or a grain size of # 1200 to # 2000.
When using the following FO abrasive grains, use micro crack MC
Can be suppressed to 1 μm or less,
As a result, even when an external force such as an impact is applied, the occurrence of cracks and the like can be extremely effectively suppressed.
On the other hand, a GC with a particle size of # 240 or more and # 1500 or less
Abrasive grains or FO with a grain size of # 240 or more and # 1000 or less
When abrasive grains are used, the average length of the micro crack MC is 1
When the thickness exceeds μm, the epitaxial wafer 14 is easily broken.

The case of lapping a GaP-based compound semiconductor epitaxial wafer has been described above, but the present invention is also applicable to a GaAs-based compound semiconductor epitaxial wafer. Also for silicon wafers, measurement of the easiness of cracking using the fracture strength measuring apparatus of the present invention can be similarly applied.

[0045]

(Example 1) A diameter of 60 mm and a thickness of 200 μm
m, a thickness of 100 on the main surface of an n-type GaP single crystal substrate having an (111) plane orientation within an off angle of ± 1 °.
μm n-type GaP epitaxial layer and 20 μm thick p
-Type GaP epitaxial layer and liquid phase growth to a total thickness of 32
A GaP epitaxial wafer having a 0 μm pn junction was manufactured. Next, the main back surface side, that is, the substrate side of the GaP epitaxial wafer was removed by lapping by 60 μm using GC abrasive grains having a grain size of # 3000, and the thickness of the wafer was set to 260 μm. Using this as an example, the results of measuring the length of microcracks generated by lapping with a SEM at a magnification of 3000 times are shown in FIG. 10, and a destruction test was performed using the destruction strength evaluation apparatus 10 of FIG. The results are shown in FIG. FIG.
Shows an example of the SEM observation image.

That is, when GC abrasive grains having a grain size of # 3000 are used, as shown in FIG. 10, the average length of the microcracks is 0.61 μm and the maximum is 1.58 μm, and all of them are 2 μm or less. . Further, as shown in FIG. 11, when the easiness of cracking of the epitaxial wafer is represented by the above-mentioned breaking height H, the average value is 196 mm and the minimum value is 17
0 mm.

On the other hand, as a comparative example, G of particle size # 1200
The same evaluation was performed on the epitaxial wafer 14 lapped under the same conditions as in Example 2 except that C abrasive grains were used. FIG. 12 shows the result of measuring the length of the microcrack generated by the lapping process, and FIG. 13 shows the result of performing a destructive test using the fracture strength evaluation device 10 of FIG. FIG. 8 shows an example of the SEM observation image. In the case of using a GC abrasive having a grain size of # 1200, as shown in FIG. 12, the average length of the microcracks was 1.04 μm, the maximum was 3.75 μm, and the length was 2 μm.
m or more microcracks were often observed (FIG. 8).
When the SEM observation image of Example 1 is compared with the SEM observation image of FIG. 7 of the example product, it can be seen that the average microcrack length is clearly longer.) In addition, as shown in FIG. 13, when the easiness of cracking of the epitaxial wafer is represented by the breaking height, the average value is 143 mm and the minimum value is 120 mm, which indicates that the wafer is very susceptible to cracking as compared with the result of the example. I understand.

(Example 2) In the same manner as in Example 1, p-
A 320 μm-thick GaP epitaxial wafer having an n-junction was fabricated. Next, the main back surface of the GaP epitaxial wafer, that is, the substrate side, was removed by lapping by 60 μm using GC abrasive grains of various particle sizes, and the thickness of the wafer was set to 260 μm. Then, in exactly the same manner as in Example 1, the measurement of the length of the microcracks generated by the lapping and the destruction test were performed on each wafer. In each abrasive grain condition, the number of test pieces was 10, and the average values of the microcrack length and the breaking height H were calculated. The above results are shown in Table 1, and a graph in which the fracture height H is plotted against the microcrack length is shown in FIG. The data corresponding to a microcrack length of 0 relates to an uninvented product which was subjected to chemical mechanical polishing after lapping until the microcracks on the surface almost disappeared ("Polish" in the table). Data).

[0049]

[Table 1]

According to the results, when the average length of the microcracks exceeds 2 μm, the breaking height H is 50 mm.
When the average length of the microcracks is 1 μm or less (especially 0.6 μm or less), the breaking height H is 150 to
It is 200 μm, which is three to four times as large as when the average length of microcracks exceeds 2 μm. In other words, it can be seen that when the average length of the microcracks generated on the lapping surface is particularly 1 μm or less, the impact resistance of the epitaxial wafer is remarkably improved, and cracks are less likely to occur.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a process of forming an epitaxial layer on a compound semiconductor single crystal substrate by a liquid phase growth method.

FIG. 2 is a perspective view showing an example of a lapping apparatus.

FIG. 3 is a diagram illustrating a process of lapping the main back surface of the compound semiconductor epitaxial wafer.

FIG. 4 is a diagram illustrating a process of forming electrodes on a compound semiconductor epitaxial wafer for manufacturing a light emitting diode.

FIG. 5 is a diagram schematically showing a light emitting diode chip obtained from the compound semiconductor epitaxial wafer of FIG. 4;

FIG. 6 is a view conceptually showing a surface state of a lapping surface of a compound semiconductor epitaxial wafer having a plane orientation of (111).

FIG. 7 is polished using a GC abrasive having a particle size of # 3000;
SEM observation image showing the lapping surface of the GaP epitaxial wafer of the example product.

FIG. 8 is polished using a GC abrasive having a particle size of # 1200,
SEM observation image showing a lapping surface of a GaP epitaxial wafer of a comparative example product.

FIG. 9 is a schematic side view showing an example of the semiconductor wafer breaking strength evaluation apparatus of the present invention.

FIG. 10 is a histogram showing the results of measuring the microcrack length of the GaP epitaxial wafer of the example in Example 1.

FIG. 11 is a histogram showing the measurement results of the breaking height.

FIG. 12 is a histogram showing a measurement result of a microcrack length of a GaP epitaxial wafer of a comparative example in Example 1.

FIG. 13 is a histogram showing the results of measuring the breaking height.

FIG. 14 is a graph in which the results of Example 2 are plotted in relation to the fracture height and the microcrack length.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 Breakdown strength evaluation device for semiconductor wafer 13 Mat (semiconductor wafer holder) 16 Input tube 17 Glass ball (sphere) 19 Drop height adjusting screw (drop start position adjuster) 20 Dial gauge (drop height measuring device) 14 Compound Semiconductor epitaxial wafer (semiconductor wafer) 14a Main surface 14b Main back surface (lapping surface) PG abrasive grain MC Micro crack (crack) 51 Compound semiconductor single crystal substrate 55-57 Epitaxial layer 60,61 Electrode 64 chip

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 33/00 H01L 33/00 BF Term (Reference) 2G061 AA14 BA03 CB16 DA01 EA10 3C058 AA07 BA02 BA09 CB02 CB10 DA02 DA17 4G077 AA03 BE43 CG01 ED02 FG11 HA02 4M106 AA01 AB09 BA11 CA46 CA70 DH01 DH11 DJ05 DJ32 5F041 AA46 CA23 CA37 CA63 CA77

Claims (17)

[Claims] 1. In a semiconductor wafer having a lapping surface which is a lapping surface, an average length of cracks generated along a cleavage plane on the lapping surface is one.
A semiconductor wafer having a size of not more than μm. 2. The semiconductor wafer according to claim 1, wherein the plane orientation is substantially (1).
The semiconductor wafer according to claim 1, which is a group III-V compound semiconductor epitaxial wafer having the main surface of item 11). 3. The semiconductor wafer according to claim 2, wherein an epitaxial layer is formed on a main surface side of the semiconductor wafer, and a main back surface is the lapping surface. 4. The semiconductor wafer according to claim 2, wherein said semiconductor wafer has an epitaxial layer formed on a gallium phosphide single crystal substrate. 5. The semiconductor wafer according to claim 1, wherein the lapping surface is processed using a green silicon carbide based fine abrasive having a grain size of # 2000 or more and # 3000 or less. 6. The semiconductor wafer according to claim 1, wherein the lapping surface is processed using an artificial emery abrasive having a grain size of # 1200 or more and # 2000 or less. 7. An epitaxial layer growing step of growing an epitaxial layer on a main surface of a compound semiconductor single crystal substrate, and a step of graining the main back surface of the compound semiconductor single crystal substrate to a particle size of # 2000.
A method for manufacturing a light emitting diode, comprising: performing a lapping process using a green silicon carbide-based fine abrasive of # 3000 or less and an electrode forming process of forming an electrode in this order. 8. An epitaxial layer growing step of growing an epitaxial layer on a main surface of a compound semiconductor single crystal substrate, and a step of forming a main back surface of the compound semiconductor single crystal substrate with a grain size of # 1200.
A method for manufacturing a light-emitting diode, comprising: performing a lapping step of lapping using an artificial emery abrasive material of # 2000 or less and an electrode forming step of forming an electrode in this order. 9. An average length of a crack generated along a cleavage plane on a lapping surface by the lapping process is as follows:
9. The method for manufacturing a light emitting diode according to claim 7, wherein the thickness is 1 μm or less. 10. The light emitting diode according to claim 7, wherein the compound semiconductor single crystal substrate is a group III-V compound semiconductor single crystal substrate having a main surface having a plane orientation of substantially (111). Production method. 11. The method for manufacturing a light emitting diode according to claim 7, wherein said compound semiconductor single crystal substrate is a gallium phosphide single crystal substrate. 12. Destruction of a semiconductor wafer, wherein a sphere is naturally dropped on a main surface of a semiconductor wafer, and the fragility of the semiconductor wafer is evaluated based on a sphere drop start position at which the semiconductor wafer is cracked. Strength evaluation method. 13. The semiconductor wafer has a cleavage plane.
13. The method for measuring breaking strength according to claim 12, wherein the sphere is a group III-V compound semiconductor single crystal, and the sphere is a glass sphere. 14. A semiconductor wafer is held so that one main surface of the semiconductor wafer faces upward, a sphere is naturally dropped toward an upper surface of the held semiconductor wafer, and a drop start position of the sphere is adjusted. A semiconductor wafer breaking strength evaluation apparatus, comprising: a falling start position adjuster for evaluating the degree of cracking of a semiconductor wafer based on a sphere falling start position at which cracking starts to occur in the semiconductor wafer. 15. A semiconductor wafer holder made of an elastic material for holding a first main surface side of the semiconductor wafer, and disposed above the semiconductor wafer held on the semiconductor wafer holder. A sphere is inserted from the opening of the semiconductor wafer, and a guiding pipe for guiding the sphere into the natural opening of the semiconductor wafer from the lower opening toward the second main surface of the semiconductor wafer. The apparatus for evaluating the breaking strength of a semiconductor wafer according to claim 14, further comprising a fall height measuring tool for measuring a fall height of the sphere. 16. The breaking strength evaluation apparatus according to claim 15, wherein said semiconductor wafer holder is made of silicone rubber. 17. The breaking strength evaluation apparatus according to claim 15, wherein the sphere is a glass sphere, and the semiconductor wafer is a compound semiconductor epitaxial wafer having a lapping surface.