JP2001119380A - Device and method for generating clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for generating clock, with which a synchronizing clock is generated on the basis of an analog signal to be inputted. SOLUTION: The average value of maximum and minimum values of a digital signal within a prescribed period is used as a threshold value, rise time and fall time are detected while using the digital signal, a time interval between the adjacent rise time and fall time is found for the prescribed period, the minimum value of this time interval is defined as an input rate and on the basis of the input rate, the synchronizing clock is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation device and a clock generation method, and more particularly to a device for generating a synchronization clock for an input analog signal.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram of a conventional clock generator. As shown in the figure, a conventional clock generation device 1300 includes an analog input terminal 1301, a threshold input terminal 1302, a synchronization signal output terminal 1303, a synchronization clock output terminal 1304, a comparison circuit 1305, a clock supply circuit 1306, and a counter circuit 1307. , A decoder circuit 1308, an edge detection circuit 1309, and a D-type flip-flop 1310.

[0003] The comparison circuit 1305 has an analog signal S13.
This is a circuit that compares whether the level of “01” is larger or smaller than the threshold value S1302 and outputs the comparison result, and operates using a clock supplied from the oscillation circuit of the clock supply circuit 1306 as a reference clock.

The clock supply circuit 1306 is a crystal oscillation circuit or the like using a crystal, and its clock frequency is an integer multiple of the input rate of the input analog signal S1301.

The counter circuit 1307 operates using the clock signal S1306 from the clock supply circuit 1306 as a reference clock, and counts the count value of the decoder circuit 1301.
8 is supplied. This counter circuit 1307 includes an output from the edge detection circuit 1309 and a decoder circuit 1308.
And operates as a clear signal.

The operation will be described below. First, the analog signal S1301 and the threshold S1302 are respectively supplied to the analog input terminal 1301 and the threshold input terminal 130.
2 is input to the comparison circuit 1305. Comparison circuit 1
In 305, the level of the analog signal S1301 is
A comparison is made as to whether the value is larger or smaller than 1302, and the comparison result is output. The binarized comparison signal S1305 output from the comparison circuit 1305 is used as an edge detection circuit 1309.
, Where the edge of the comparison signal S1305 is detected. The signal whose edge has been detected is supplied to the counter circuit 1307, and clears the counter. By this series of edge detection and counter clearing operations, the count value of the counter circuit 1307 and the comparison signal S1305
, Ie, the phase coincides.

Since the count value of the counter is usually composed of a plurality of bits, the decoder circuit 1308
Using the sample clock signal S1304 as a supply clock, decoding is performed so that the analog input signal S1301 can be captured at an appropriate phase. Then, the D-type flip-flop 1310 latches the comparison signal S1305.
The counter clear signal S1308 output from the decoder circuit 1308 determines the frequency division ratio of the counter 1307.

[0008]

However, as described above, the conventional clock generating device requires the analog signal to be supplied to the clock supply circuit if the clock frequency of the clock supply circuit is not an integral multiple of the rate of the input analog signal. If the same state is held for a longer period than the clock cycle (for example, if the high level continues), the phase error exceeds the allowable range, and the analog signal may be erroneously recognized. There was a problem. Further, when there are a plurality of types of analog signal rates, there is a problem that a plurality of types of oscillation circuits corresponding to each type are required.

Further, when the conventional clock generation device is realized by a semiconductor integrated circuit, if the clock frequency of the clock supply circuit is increased in order to improve the characteristics, unnecessary radiation from the semiconductor integrated circuit may occur. However, there is a problem that power consumption increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a clock generation device and a clock generation method for generating a synchronization clock based on an input analog signal. Aim.

[0011]

According to a first aspect of the present invention, there is provided a clock generating apparatus comprising: an A / D converter for converting an input analog signal into a digital signal; a synchronizing clock based on the digital signal; And a calculating means for generating a threshold value, comparing the digital signal with a signal larger or smaller than the threshold value, outputting a binary signal, and latching the binary signal with the synchronization clock. Latch means for performing the operation.

According to a second aspect of the present invention, in the clock generating apparatus according to the first aspect, the arithmetic means detects a maximum value and a minimum value of the digital signal within a predetermined period, Threshold value detection means for outputting the average value of the maximum value and the minimum value as the threshold value; and rise time detection means for detecting a rise time at which the analog signal is higher than the threshold value using the digital signal. A falling time that is a time at which the analog signal becomes lower than the threshold value, a falling time detecting unit that detects the falling time using the digital signal, and a time interval between the adjacent rising time and the falling time. An input rate detecting means for obtaining a predetermined period and outputting a minimum value of the time interval as an input rate; It is obtained by the one having a synchronized clock output means for outputting a synchronization clock.

According to a third aspect of the present invention, in the clock generating apparatus according to the first aspect, the arithmetic means detects an integrated value of the digital signal within a predetermined time period, and Threshold value detection means for outputting an average value of the analog signal as the threshold value; rising time time at which the analog signal becomes higher than the threshold value; rising time detection means for detecting the rising time using the digital signal; A fall time that is a time lower than a threshold value, a fall time detection unit that detects using the digital signal, a time interval between the adjacent rise time and the fall time is obtained for a predetermined period,
An input rate detecting means for outputting the minimum value of the time interval as an input rate, and a synchronization clock output means for outputting the synchronization clock based on the input rate.

According to a fourth aspect of the present invention, there is provided a clock generating apparatus according to any one of the first to third aspects, further comprising an oversampling digital filter for interpolating the adjacent digital signal. .

According to a fifth aspect of the present invention, there is provided a clock generating method for converting an input analog signal into a digital signal.
/ D conversion step, an operation step of generating a synchronization clock and a threshold value based on the digital signal, and comparing whether the digital signal is larger or smaller than the threshold value, and outputting a binarized signal. And a latch step of latching the binarized signal with the synchronization clock.

According to a sixth aspect of the present invention, in the clock generation method according to the fifth aspect, the calculating step detects a maximum value and a minimum value of the digital signal within a predetermined period, A threshold detecting step of outputting the average value of the maximum value and the minimum value as the threshold value; and a rising time detecting step of detecting, using the digital signal, a rising time at which the analog signal becomes higher than the threshold value. A falling time that is a time at which the analog signal becomes lower than the threshold, a falling time detecting step of detecting using the digital signal, and a time interval between the adjacent rising time and the falling time. An input rate detecting step of obtaining a predetermined period and outputting a minimum value of the time interval as an input rate; Based on over bets, it is obtained by those having a synchronized clock output step of outputting the synchronous clock.

In a clock generation method according to a seventh aspect of the present invention, in the clock generation method according to the fifth aspect, the calculating step detects an integrated value of the digital signal within a predetermined period, and detects the integrated value. A threshold value detection step of outputting an average value of the analog signal as the threshold value, a rising time point at which the analog signal is higher than the threshold value, a rising time detecting step of detecting the rising edge time using the digital signal, A fall time detection step of detecting a fall time, which is a time lower than a threshold, by using the digital signal; and determining a time interval between the adjacent rise time and the fall time for a predetermined period. An input rate detection step of outputting a minimum value of the interval as an input rate; and It was assumed that a synchronization clock output step of outputting the initialized clock.

A clock generating method according to claim 8 of the present invention is the clock generating method according to any one of claims 5 to 7, further comprising an oversampling step of interpolating the adjacent digital signals.

[0019]

Embodiments of the present invention will be described below. (Embodiment 1) FIG. 1 is a block diagram of a clock generator according to Embodiment 1 of the present invention. Embodiment 1
, A clock signal input terminal 101, a clock signal input terminal 102, a synchronization signal output terminal 103, a synchronization clock output terminal 104, an A / D
Converter 105, arithmetic circuit 106, comparison circuit 107,
And a latch circuit 108.
An analog signal S101 on which data is superimposed and a clock signal S102 are input, and a synchronization signal S103,
It outputs a synchronization clock S104.

The A / D converter 105 outputs a digital signal S109 which is a digital discrete value by sampling the analog signal S101 according to the timing of the clock signal S102. The arithmetic circuit 106 receives the digital signal S109 and the clock signal S
102, and a threshold value S106a, which is a reference value for binarizing the digital signal S109, and a binary signal S109.
It outputs a synchronization clock S106b for latching the signal 110, and details thereof will be described later.

The comparison circuit 107 has a digital conversion signal S1.
09 and the threshold value S106a, and the clock signal S10
2 and performs a magnitude comparison with the digital signal S109 based on the threshold value S106a. For example, if the digital signal S109 is larger than the threshold value S106a, “1” is set. Is output as the binary signal S110. Latch circuit 1
08 is a binary signal S11 output from the comparison circuit 107.
0 is a D input, a synchronization clock S106b is a clock input, and a synchronization signal S103 is output.

FIG. 2 is a block diagram of an arithmetic circuit of the clock generator according to the first embodiment of the present invention. The arithmetic circuit 106 according to the first embodiment includes a threshold detection block 200 that detects the threshold S106a, a rising detection block 201 that detects a rising time when the analog signal S101 becomes higher than the threshold S106a, and a threshold detection block 201 that detects the threshold S106a. Fall detection block 2 for detecting a fall time that is a time lower than
02, an input rate detection block 203 that detects the rate of the digital signal S109 using the rising time and the falling time, and a synchronization clock output block 204 that outputs a synchronization clock S106b.

The operation of the clock generator will be described below. The analog signal S101 is input to the A / D converter 105 via the analog signal input terminal 101, and the clock signal S102 is input to the A / D converter 105, the arithmetic circuit 106, and the clock signal input terminal 102. The signal is input to the comparison circuit 107.

The A / D converter 105 outputs a digital signal S109, which is a digital discrete value, to the arithmetic circuit 106 and the comparison circuit 107 by sampling the analog signal S101 according to the timing of the clock signal S102.

The arithmetic circuit 106 generates a digital signal S109
And the clock signal S102, and the digital signal S
Threshold value S106a which is a reference value for binarizing 109
And a synchronization clock S106b for the latch circuit 108 to latch the binarized signal S110. The details will be described later.

The comparison circuit 107 receives the digital signal S109
And the threshold S106a, and the digital signal S10
A comparison is made whether 9 is large or small. For example, threshold S
If the digital signal S109 is larger than 106a, "1" is set. If the digital signal S109 is smaller, "0" is set.
Output as 0. The latch circuit 108 outputs the binarized signal S
110 is a D input, a synchronization clock S106b is a clock input, and a synchronization signal S1 which is a synchronization signal output.
03 is output.

In the following, the arithmetic circuit 106 sets the threshold value S106
a and the operation of outputting the synchronization clock S106b will be described with reference to the flowcharts of FIGS. FIG. 3 is a flowchart showing the operation of the arithmetic circuit according to the first embodiment of the present invention. First, the threshold detection block 200 detects the threshold S106a (Step 30).
0), output to the rise detection block 201, the fall detection block 202, and the comparison circuit 107 (step 301). Note that the threshold detection method will be described later.

Next, the rise detection block 201
The rising time Rise (j), which is the time when the analog signal S101 becomes higher than the threshold value S106a, is detected (Step 302), and is output to the input rate detection block 203 and the synchronization clock output block 204 (Step 303). Similarly, the falling detection block 202
Detects a fall time Fall (j), which is a time at which the analog signal S101 becomes lower than the threshold value S106a, and outputs the fall time Fall (j) to the input rate detection block 203 and the synchronization clock output block 204. Note that “j” is an argument and indicates the order in which the respective times are detected. The rising time detecting method and the falling time detecting method will be described later.

Next, the input rate detection block 203
Rise time Rise (j) and fall time F
Based on all (j), the rate Rate of the digital signal S109 is detected (step 304) and output to the synchronization clock output block 204 (step 305).
The input rate detection method will be described later. Then, the synchronization clock output block 204 outputs the synchronization clock s106b (Step 306). In addition,
The synchronization clock output method will be described later.

FIG. 4 is a flowchart showing a threshold value detecting method according to the first embodiment of the present invention. First, a digital signal S109 output from the A / D converter at an arbitrary time
As the 0th data A ₀ , this is set as an initial value (step 400), and this data A ₀ is
6, and input "1" to the internal pointer i and the number of repetitions N (step 401). In addition,
The repetition number N indicates the number of digital signals S109, and the greater the number, the more the accuracy of the threshold value S106a is improved.

Next, the data is stored in the order in which the internal pointer i points.
Digital signal S109 is received, and the received data is received.
Data A_iIs larger than the data in the internal register Amax
A comparison is made as to whether it is smaller or smaller (step 402). This and
Data A_iIs larger than the data in the internal register Amax
If it can, the data of the internal register Amax is _i
(Step 403). Conversely, data A_iBut
If it is smaller than the data in the internal register Amax,
TA A_iIs greater than the data in the internal register Amin
A comparison is made as to whether it is smaller (step 404). At this time
Data A_iIs smaller than the data in the internal register Amin.
If the data of the internal register Amin is the data A_iTo
Replace (step 405).

Thereafter, the internal pointer i is incremented (step 406), and it is checked whether the value of the internal pointer i is equal to the number of repetitions N (step 40).
7). At this time, if the value of the internal pointer i is not equal to the number of repetitions N, that is, if the value of the internal pointer i is smaller than the number of repetitions N, the process proceeds to step 402 to accept the next digital signal S109, and if they are equal, the internal register Amax Is output as the threshold value S106a (step 408).

FIG. 5 is a flowchart showing a rising time detecting method according to the first embodiment of the present invention. First, "2" is input to the internal pointer i, and the internal pointer j is further cleared. Then, the digital signal S109 received at an arbitrary time is defined as data A ₀ , the digital signal S109 received next to the data A ₀ is defined as data A ₁ ,
Further, an input of the number of repetitions M is received (step 50).
0).

Further, a digital signal S109 is received (step 501). Here, when step 501 is executed for the first time, since the internal pointer i is already set to “2”, the digital signal S109 received at this time becomes data A ₂ .

Next, the value of the data A _i-1 is equal to the threshold value S106a.
Less than, and the value of the data A _i to determine whether greater than the threshold S 106 a (step 502). At this time, if the value of the data A _i-1 is larger than the threshold value S106a or if the value of the data A _i is smaller than the threshold value S106a, the internal pointer i is incremented and step 5
01 is executed (step 503). Data A
The value of _i-1 is smaller than the threshold value S106a and the data A _i
Is larger than the threshold value S106a, the analog signal S101 crosses the threshold value S106a to generate a rising time, and thus the j-th rising time Rise
(J) is output (step 504). The details of this calculation will be described later.

Next, the internal pointer j is incremented (step 505), and it is monitored whether M rising times Rise (j) have been detected (step 506).
At this time, the process is completed if M pieces have been detected, but otherwise returns to step 501 and repeats the above processing until M pieces of rising times are detected.

FIG. 6 is a timing chart for explaining a rising time detecting method according to the first embodiment of the present invention. At time T _i−1 , data A _i−1 of digital signal S109 which is an output of A / D converter 105 is received, and this value is below threshold value S106a. Also, at time T _i, is accepted data A _i of the digital signal S109. This data A _i is equal to the threshold S106
a. Thus between the times T _i-1 and the time T _i, the analog signal S101 intersects the threshold S 106 a.

An alternate long and short dash line 600 indicates a straight line approximated by a straight line based on the data of the two points. Analog signal S10
The time when 1 crosses the threshold value S106a is indicated by a dashed-dotted line 600.
If it is approximated that the time has crossed the threshold S106a, it means that the time x _i-1 has elapsed from the time T _i-1 . That is, the one-dot chain line 600 is the intersection time approximation straight line, and _x1-1 is the rising intersection time correction time.

Here, assuming that the origin of the time axis of the dashed line 600 is the point in time when the data A _i-1 is inputted, the parameter of the time axis is x, and the amplitude axis of the input signal is y, y = A _{i− 1 + (a i -A i-} 1) x , and the time x _i-1 to the dashed line 600 intersects the threshold S106a, when the threshold value is _{THR, THR = a i-1} + (a i -A i- ₁ ) It is given by x _i-1 .

Therefore, this linear equation is calculated and x
by obtaining the _i-1, a _{= x i-1 (THR-} A i-1) / (A i -A i-1). Since this x _i−1 corresponds to the decimal part of the rise time Rise (j), the rise time Rise (j) obtained in step 504 is Rise (j) = i−1 + xi ₋₁ .

FIG. 7 is a flowchart showing a falling time detecting method according to the first embodiment of the present invention. FIG.
In FIG. 5, those having the same reference numerals as those in FIG. 5 correspond to those in FIG. Since the fall time detection method shown in the flowchart of FIG. 7 detects whether or not step 702 has fallen, the determination condition is reversed from that of step 502, and the value of the data A _i-1 is equal to the threshold value S106a. greater than, and that determines whether the value of the data a _i is smaller than the threshold S 106 a, and that a calculation result in step 704 is output as Fall (j) are respectively the rise time detection method described above , 502, and 504.

The input rate of the analog signal can be detected based on the rise time and fall time detected by the above-described processing. That is, if the time from a certain rise time Rise (j) to the next fall time Fall (j) is obtained,
Since the time is always a multiple of the input rate, a difference value between a plurality of rising times and falling times may be obtained, and the minimum value may be set as the input rate.

FIG. 8 is a flowchart showing an input rate detection method according to the first embodiment of the present invention. First, an initial value is input to the internal register Rate, and the internal pointer j
, An initial value "1" is input to set the number of repetitions M (step 800). Here, M means the number of data at a plurality of rising times Rise and falling times Fall obtained in step 302.

Next, a time interval between the rise time Rise (j) and the fall time Fall (j) is calculated, and the result is stored in the internal register Temp (step 801). The internal register Temp has a rise time Rise corresponding to an argument prepared for convenience of operation.
(J) and a save register for saving a difference value between the fall time Fall (j).

Next, the value of the internal register Rate is compared with the value of the internal register Temp (Step 802). At this time, if the value of the internal register Temp is smaller than the value of the internal register Rate, the value of the internal register Temp is input to the internal register Rate and the values are exchanged (step 803). If the value of the internal register Temp is larger than the value of the internal register Rate, the internal pointer j is incremented and step 801 is executed again.

When the value of the internal pointer j is equal to the value of the number of repetitions M, that is, when the specified number of processes have been completed, the process is completed.
The value of e is set as the input rate, and if the specified number of processes has not been completed, step 804 is executed (step 80).
5).

FIG. 9 is a flowchart showing a synchronized clock output method according to the first embodiment of the present invention. First, the threshold value S106a detected in step 300 and the input rate Rate detected in step 305 are accepted, and the internal pointer i is cleared (step 9).
00).

Next, performs reception of the digital signal S109 in the order in which internal pointer i is pointing, the difference between the difference between the received data A _i and the threshold S 106 a, the previous received data A _i-1 and the threshold S 106 a, (Step 902). If the value is 0 or more, the internal pointer i is incremented (Step 903). Conversely, if the value is less than 0, Step 504 and Step 7 are performed.
Based on the same principle as that of step S04, Xi and the edge time Edge (j), which is the time of intersection with the threshold value S106a, are calculated (step 904). Edge obtained by this
(I) is divided into an integer part i and a decimal part Xi.
/ 2 is also divided into an integer part r and a decimal part ri. And
Edge (i) and Rate / 2 are added, and as a result, an integer part Sam and a decimal part Xs are obtained (step 905).
By the calculation in this step, the first synchronization clock S106b has a timing half the input rate Rate, that is, a middle timing with respect to one rate of the input signal, after the edge of the signal comes.

Next, it is monitored that the Sam-th data Asam for generating the synchronization clock S106b is input (step 906). If the input of the data Asam is detected, the synchronization clock S106b is detected. Is generated once (step 907). Then, the second and subsequent synchronization clock timing values are calculated (step 908). In this step, when the first synchronization clock is generated in step 905, Sam + Xs, which is the timing for generating the synchronization clock in the middle of the input rate, is calculated. Therefore, the value of the internal register Rate is simply calculated. If added, the second and subsequent clocks can be generated in the middle of the input rate.

Thereafter, the above processing is repeated to output a synchronization clock. In the clock generation device and the clock generation method according to the first embodiment, an input rate is detected from a digital signal obtained by A / D conversion of an input analog signal, and a synchronization clock is generated based on the input rate. Therefore, when latching the binarized signal, the phase error between the synchronized clock and the binarized signal can be kept within one clock of the synchronized clock. Even when the input analog signal has a plurality of types of input rates, the circuit can be operated with only one type of supplied clock.

Furthermore, the clock generation device according to the first embodiment is usually realized by a semiconductor integrated circuit. In this case, it is not necessary to increase the frequency of the supplied clock in order to improve its characteristics. Thus, the problem that unnecessary radiation generated from the semiconductor integrated circuit increases and the problem that power consumption increases do not occur.

(Embodiment 2) FIG. 10 is a block diagram of an arithmetic circuit of a clock generation device according to Embodiment 2 of the present invention. In the clock generation device according to the second embodiment, the arithmetic circuit 106 of the clock generation device according to the first embodiment shown in FIG. 1 is the same as that shown in FIG. 10 except for the configuration. This is the same as in the clock generation device according to mode 1.

As shown in FIG. 10, the arithmetic circuit 106
Is a threshold detection block 100 for detecting the threshold S106a.
0, a rising detection block 201 that detects a rising time that is a time when the analog signal S101 becomes higher than the threshold value S106a;
6a, a falling detection block 202 for detecting a falling time, which is a time lower than 6a, an input rate detecting block 203 for detecting a rate of the digital signal S109 using the rising time and the falling time, and a synchronization clock S106b. It comprises a synchronized clock output block 204 for outputting.

The operation will be described below. The operations of the rise detection block 201, the fall detection block 202, the input rate detection block 203, and the synchronization clock output block 204 are the same as those in the first embodiment, and a description thereof will be omitted here. Next, an operation in which the threshold detection block 1000 detects the threshold S106a will be described with reference to FIG.

FIG. 11 is a flowchart showing a threshold value detecting method according to the second embodiment. First, the arithmetic circuit 10
6, the internal register Acc and the internal pointer i are cleared, and the repetition number N is received (step 110).
0). Note that the number of repetitions N indicates the number of digital signals S109, and the greater the number, the higher the accuracy of the threshold value S106a.

Next, while receiving the digital signal S109, it is monitored whether or not the value of the internal pointer i is larger than the number of repetitions N (step 1101). If the value of the internal pointer i at this time is smaller than the number of repetitions N, added one after another internal register Acc data A _i received in step 1101, further increments the internal pointer i (step 1102). As a result, the data A _{i of the} digital signal S109 is stored in the internal register Acc.
Of i = 0, that is, from 0th data, i = N, i.e. the integral value of the data A _i of (N + 1) digital signal S109 to the N-th is accumulated in the internal register Acc. If the value of the internal pointer i is larger than the number of repetitions N, the value of the internal register Acc is divided by the number of integrated data, that is, N + 1, and the value is output as the threshold value S106a (step 1103).

In the clock generation device and the clock generation method according to the second embodiment, the average value of the integrated value of the digital signal is used as the threshold value, so that the clock generation device and the clock generation device according to the first embodiment are used. In addition to the effect of the method, the detection of the threshold value is less susceptible to noise or the like, and an effect of detecting a more accurate threshold value is obtained.

(Embodiment 3) FIG. 12 is a block diagram of a clock generator according to Embodiment 3 of the present invention.
In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here. The clock generation device according to the third embodiment includes an oversampling digital filter 1201 at a stage subsequent to the A / D converter 105 of the clock generation device according to the first embodiment. Oversampling digital filter 120
Reference numeral 1 designates an input signal for giving an arbitrary frequency characteristic and performing oversampling,
7 is output.

In the clock generation device and the clock generation method according to the third embodiment, the oversampling digital filter gives an arbitrary frequency characteristic to the digital signal, thereby removing unnecessary signals such as noise. Further, by performing oversampling, the number of sample data also increases, and the time resolution of the digital signal can be increased.

The clock generator according to the third embodiment is similar to the clock generator according to the first embodiment.
Although the oversampling digital filter is provided after the / D converter, it may be provided after the A / D converter of the clock generation device according to the second embodiment.

Further, in the first to third embodiments, the clock generation device and the clock generation method according to the present invention have been described by taking as an example a case where a television signal in which VBI data is superimposed during a flyback period is input. , But not limited to, CD (Compact Disk) and MD (Mini Disk)
May be input.

[0062]

As described above, according to the clock generation device of the first aspect of the present invention, A / D conversion means for converting an input analog signal into a digital signal, and synchronization based on the digital signal. Arithmetic means for generating a clock and a threshold, binarization means for comparing whether the digital signal is larger or smaller than the threshold, and outputting a binarized signal, and a latch for latching the binarized signal with a synchronization clock Means for generating a synchronization clock on the basis of a digital signal obtained by A / D conversion of an input analog signal, so that when the binarized signal is latched, The phase error with the digitized signal can be kept within one clock of the synchronization clock, and even if the input analog signal has a plurality of types of input rates,
There is an effect that the circuit can be operated with only one kind of supplied clock.

According to the clock generation device of the second aspect of the present invention, in the clock generation device of the first aspect, the arithmetic means detects the maximum value and the minimum value of the digital signal within a predetermined period, Threshold detection means that outputs an average value of the maximum value and the minimum value as a threshold, and a rising time at which an analog signal is higher than the threshold,
Rising time detecting means for detecting using a digital signal, falling time detecting means for detecting a falling time at which an analog signal becomes lower than a threshold value using a digital signal, and adjacent rising time and falling An input rate detecting means for obtaining a time interval from the time for a predetermined period and outputting a minimum value of the time interval as an input rate, and a synchronization clock output means for outputting a synchronization clock based on the input rate. Therefore, by detecting an input rate from a digital signal obtained by A / D conversion of an input analog signal and generating a synchronization clock based on the input rate, when latching a binary signal,
The phase error between the synchronization clock and the binary signal can be kept within one clock of the synchronization clock.
Even when the input analog signal has a plurality of types of input rates, there is an effect that the circuit can be operated with only one type of supplied clock.

According to the clock generation device of the third aspect of the present invention, in the clock generation device of the first aspect, the arithmetic means detects an integrated value of the digital signal within a predetermined period, and detects the integrated value. Threshold value detecting means for outputting an average value of the threshold value as a threshold, rising time detecting means for detecting a rising time at which the analog signal becomes higher than the threshold value by using a digital signal, and a time at which the analog signal becomes lower than the threshold value. Falling time detecting means for detecting a falling time using a digital signal, a time interval between an adjacent rising time and a falling time is obtained for a predetermined period, and the minimum value of the time interval is output as an input rate. And a synchronization clock output means for outputting a synchronization clock based on the input rate. In, in addition to the effects of the clock generating apparatus according to claim 2, less susceptible to noise and the like when detecting the threshold, there is an effect that it is possible to detect a more accurate threshold.

According to a clock generation device according to a fourth aspect of the present invention, there is provided the clock generation device according to any one of the first to third aspects, further comprising an oversampling digital filter for interpolating an adjacent digital signal. Therefore, by giving an arbitrary frequency characteristic to the digital signal, unnecessary signals such as noise can be removed, and by performing oversampling, the number of sample data also increases. There is an effect that the resolution can be increased.

According to the clock generation method of the fifth aspect of the present invention, an A / D conversion step of converting an input analog signal into a digital signal;
A calculating step of generating a synchronization clock and a threshold;
Compare whether the digital signal is larger or smaller than the threshold,
Since the apparatus includes a binarizing step of outputting a binarized signal and a latching step of latching the binarized signal with a synchronization clock, the digital signal is based on a digital signal obtained by A / D converting an input analog signal. When the binarized signal is latched, the phase error between the synchronized clock and the binarized signal can be kept within one clock of the synchronized clock when the binarized signal is latched. Even if the analog signal to be input has multiple input rates,
There is an effect that the circuit can be operated with only one kind of supplied clock.

According to a clock generation method according to claim 6 of the present invention, in the clock generation method according to claim 5, the calculating step detects a maximum value and a minimum value of the digital signal within a predetermined period, A threshold detection step of outputting an average value of the maximum value and the minimum value as a threshold, a rise time detection step of detecting a rise time at which an analog signal becomes higher than the threshold using a digital signal, and an analog signal A falling time, which is a time at which the time becomes lower than the threshold, is detected by using a digital signal, and a time interval between an adjacent rising time and a falling time is obtained for a predetermined period. An input rate detection step of outputting the minimum value as an input rate, and outputting a synchronization clock based on the input rate Having assumed that an initialized clock output step, the input analog signal A /
Detects the input rate from the D-converted digital signal and generates a synchronization clock based on this to synchronize the phase error between the synchronization clock and the binary signal when latching the binary signal. The clock can be kept within one clock, and even when the input analog signal has a plurality of types of input rates, the circuit can be operated with only one type of supplied clock.

According to a clock generation method of a seventh aspect of the present invention, in the clock generation method of the fifth aspect, the calculation step detects an integrated value of the digital signal within a predetermined period, and calculates the integrated value. A threshold detection step of outputting the average value of the threshold as a threshold, a rising time detection step of detecting a rising time at which the analog signal becomes higher than the threshold using a digital signal, and a time at which the analog signal becomes lower than the threshold. A falling time detecting step of detecting the falling time using a digital signal, obtaining a time interval between an adjacent rising time and a falling time for a predetermined period, and outputting a minimum value of the time interval as an input rate. An input rate detection step to
A synchronization clock output step of outputting a synchronization clock based on the input rate.
When detecting the threshold value, it is less susceptible to noise and the like,
There is an effect that a more accurate threshold can be detected.

According to a clock generation method according to claim 8 of the present invention, in the clock generation method according to any one of claims 5 to 7, an oversampling step for interpolating adjacent digital signals is provided. Therefore, by giving an arbitrary frequency characteristic to the digital signal, unnecessary signals such as noise can be removed, and by performing oversampling, the number of sample data also increases. There is an effect that can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock generation device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an arithmetic circuit of the clock generation device according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing an operation of the arithmetic circuit according to the first embodiment of the present invention.

FIG. 4 is a flowchart illustrating a threshold detection method according to the first embodiment of the present invention.

FIG. 5 is a flowchart illustrating a rising time detection method according to the first embodiment of the present invention.

FIG. 6 is a timing chart for explaining a rising time detection method according to the first embodiment of the present invention.

FIG. 7 is a flowchart illustrating a fall time detection method according to the first embodiment of the present invention.

FIG. 8 is a flowchart illustrating an input rate detection method according to the first embodiment of the present invention.

FIG. 9 is a flowchart showing a synchronized clock output method according to the first embodiment of the present invention.

FIG. 10 is a block diagram of an arithmetic circuit of the clock generation device according to the second embodiment.

FIG. 11 is a flowchart illustrating a threshold detection method according to the second embodiment of the present invention.

FIG. 12 is a block diagram of a clock generation device according to a third embodiment of the present invention.

FIG. 13 is a block diagram of a conventional clock generation device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 clock generation device 101 analog signal input terminal 102 clock input terminal 103 synchronization signal output terminal 104 synchronization clock output terminal 105 A / D converter 106 arithmetic circuit 107 comparison circuit 108 latch circuit 1201 oversampling digital filter

Claims (8)

[Claims] An A / D converter for converting an input analog signal into a digital signal; an arithmetic unit for generating a synchronization clock and a threshold based on the digital signal; A clock generation device comprising: a binarizing unit that compares whether the value is larger or smaller and outputs a binarized signal; and a latch unit that latches the binarized signal with the synchronization clock. 2. The clock generation device according to claim 1, wherein the arithmetic unit detects a maximum value and a minimum value of the digital signal within a predetermined period, and calculates an average value of the maximum value and the minimum value. Threshold detection means for outputting as the threshold value; rising time detection means for detecting, using the digital signal, a rising time at which the analog signal becomes higher than the threshold value; and the analog signal being lower than the threshold value. Falling time detecting means for detecting a falling time, which is a time, by using the digital signal; determining a time interval between the adjacent rising time and the falling time for a predetermined period; a minimum value of the time interval Input rate detecting means for outputting the input clock as an input rate; and a synchronization clock for outputting the synchronization clock based on the input rate. A clock output device. 3. The clock generation device according to claim 1, wherein the calculating means detects an integrated value of the digital signal within a predetermined period, and outputs an average value of the integrated value as the threshold value. Means, rising time detecting means for detecting, using the digital signal, a rising time at which the analog signal becomes higher than the threshold value; and a falling time at which the analog signal becomes lower than the threshold value. Falling time detecting means for detecting the time interval between the adjacent rising time and the falling time for a predetermined period, and inputting the minimum value of the time interval as an input rate. Rate detection means, and synchronization clock output means for outputting the synchronization clock based on the input rate. A clock generation device, characterized in that: 4. The clock generation device according to claim 1, further comprising an oversampling digital filter for interpolating the adjacent digital signal. 5. An A / D conversion step of converting an input analog signal into a digital signal, an operation step of generating a synchronization clock and a threshold based on the digital signal, and wherein the digital signal is higher than the threshold. A clock generation method, comprising: a binarizing step of comparing whether the value is larger or smaller and outputting a binarized signal; and a latching step of latching the binarized signal with the synchronization clock. 6. The clock generation method according to claim 5, wherein the calculating step detects a maximum value and a minimum value of the digital signal within a predetermined period, and calculates an average value of the maximum value and the minimum value. A threshold detection step of outputting as the threshold, a rising time at which the analog signal is higher than the threshold, a rising time detection step of detecting the rising edge using the digital signal, and the analog signal being lower than the threshold. A fall time detection step of detecting a fall time that is a time using the digital signal; and determining a time interval between the adjacent rise time and the fall time for a predetermined period, and determining a minimum value of the time interval. An input rate detecting step of outputting as an input rate; and A clock output step for outputting a clock signal. 7. The clock generating method according to claim 5, wherein the calculating step detects a digital signal integrated value within a predetermined period, and outputs an average value of the integrated value as the threshold value. A rising time detection step of detecting, by using the digital signal, a rising time at which the analog signal becomes higher than the threshold; and a falling time at which the analog signal becomes lower than the threshold. A falling time detecting step of detecting the time using the digital signal, obtaining a time interval between the adjacent rising time and the falling time for a predetermined period, and outputting a minimum value of the time interval as an input rate. A rate detecting step, and a synchronization clock for outputting the synchronization clock based on the input rate. A clock generation method, comprising: an output step. 8. The clock generation method according to claim 5, further comprising an oversampling step of interpolating the adjacent digital signals.