GB2306066B - Method of processing multi-level signals for simple clock recovery - Google Patents

Method of processing multi-level signals for simple clock recovery

Info

Publication number
GB2306066B
GB2306066B GB9620488A GB9620488A GB2306066B GB 2306066 B GB2306066 B GB 2306066B GB 9620488 A GB9620488 A GB 9620488A GB 9620488 A GB9620488 A GB 9620488A GB 2306066 B GB2306066 B GB 2306066B
Authority
GB
United Kingdom
Prior art keywords
method
clock recovery
level signals
processing multi
simple clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9620488A
Other versions
GB2306066A (en
GB9620488D0 (en
Inventor
Michael Altmann
Bernard Guay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Nortel Networks Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US467895P priority Critical
Priority to US08/715,218 priority patent/US5825825A/en
Application filed by Nortel Networks Ltd filed Critical Nortel Networks Ltd
Publication of GB9620488D0 publication Critical patent/GB9620488D0/en
Publication of GB2306066A publication Critical patent/GB2306066A/en
Application granted granted Critical
Publication of GB2306066B publication Critical patent/GB2306066B/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating pulses not covered by one of the other main groups in this subclass
    • H03K5/153Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1532Peak detectors
GB9620488A 1995-10-02 1996-10-02 Method of processing multi-level signals for simple clock recovery Expired - Fee Related GB2306066B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US467895P true 1995-10-02 1995-10-02
US08/715,218 US5825825A (en) 1996-09-17 1996-09-17 Method of processing multi-level signals for simple clock recovery

Publications (3)

Publication Number Publication Date
GB9620488D0 GB9620488D0 (en) 1996-11-20
GB2306066A GB2306066A (en) 1997-04-23
GB2306066B true GB2306066B (en) 2000-02-16

Family

ID=26673328

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9620488A Expired - Fee Related GB2306066B (en) 1995-10-02 1996-10-02 Method of processing multi-level signals for simple clock recovery

Country Status (1)

Country Link
GB (1) GB2306066B (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4335381B2 (en) * 1999-10-18 2009-09-30 パナソニック株式会社 Clock generation device, and a clock generation method
US7212580B2 (en) * 2002-02-15 2007-05-01 Quellan, Inc. Multi-level signal clock recovery technique
WO2003077423A2 (en) 2002-03-08 2003-09-18 Quellan, Inc. High speed analog-to-digital converter using a unique gray code having minimal bit transitions
WO2004008782A2 (en) 2002-07-15 2004-01-22 Quellan, Inc. Adaptive noise filtering and equalization
US7934144B2 (en) 2002-11-12 2011-04-26 Quellan, Inc. High-speed analog-to-digital conversion with improved robustness to timing uncertainty
KR101109847B1 (en) 2003-08-07 2012-04-06 ?란 인코포레이티드 Method and system for crosstalk cancellation
US7804760B2 (en) 2003-08-07 2010-09-28 Quellan, Inc. Method and system for signal emulation
DE602004030032D1 (en) 2003-11-17 2010-12-23 Quellan Inc Method and system for extinction by aerial disorders
US7616700B2 (en) 2003-12-22 2009-11-10 Quellan, Inc. Method and system for slicing a communication signal
US7522883B2 (en) 2004-12-14 2009-04-21 Quellan, Inc. Method and system for reducing signal interference
US7725079B2 (en) 2004-12-14 2010-05-25 Quellan, Inc. Method and system for automatic control in an interference cancellation device
US9252983B2 (en) 2006-04-26 2016-02-02 Intersil Americas LLC Method and system for reducing radiated emissions from a communications channel
CN102201810A (en) * 2010-03-23 2011-09-28 奇景光电股份有限公司 Device and method for controlling clock recovery

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2031694A (en) * 1978-09-14 1980-04-23 Itt Ternary to binary conversion
US4464771A (en) * 1982-04-02 1984-08-07 Motorola, Inc. Phase-locked loop circuit arrangement
US4651026A (en) * 1983-07-06 1987-03-17 Motorola, Inc. Clock recovery circuit
EP0407031A2 (en) * 1989-07-06 1991-01-09 Advanced Micro Devices, Inc. Apparatus for transmitting digital data in analog form
US5237590A (en) * 1989-03-13 1993-08-17 Hitachi, Ltd. Timing extraction circuit and communication system utilizing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2031694A (en) * 1978-09-14 1980-04-23 Itt Ternary to binary conversion
US4464771A (en) * 1982-04-02 1984-08-07 Motorola, Inc. Phase-locked loop circuit arrangement
US4651026A (en) * 1983-07-06 1987-03-17 Motorola, Inc. Clock recovery circuit
US5237590A (en) * 1989-03-13 1993-08-17 Hitachi, Ltd. Timing extraction circuit and communication system utilizing the same
EP0407031A2 (en) * 1989-07-06 1991-01-09 Advanced Micro Devices, Inc. Apparatus for transmitting digital data in analog form

Also Published As

Publication number Publication date
GB2306066A (en) 1997-04-23
GB9620488D0 (en) 1996-11-20

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20131002