GB9620488D0 - Method of processing multi-level signals for simple clock recovery - Google Patents
Method of processing multi-level signals for simple clock recoveryInfo
- Publication number
- GB9620488D0 GB9620488D0 GBGB9620488.8A GB9620488A GB9620488D0 GB 9620488 D0 GB9620488 D0 GB 9620488D0 GB 9620488 A GB9620488 A GB 9620488A GB 9620488 D0 GB9620488 D0 GB 9620488D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- clock recovery
- level signals
- processing multi
- simple clock
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1532—Peak detectors
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US467895P | 1995-10-02 | 1995-10-02 | |
US08/715,218 US5825825A (en) | 1996-09-17 | 1996-09-17 | Method of processing multi-level signals for simple clock recovery |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9620488D0 true GB9620488D0 (en) | 1996-11-20 |
GB2306066A GB2306066A (en) | 1997-04-23 |
GB2306066B GB2306066B (en) | 2000-02-16 |
Family
ID=26673328
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9620488A Expired - Fee Related GB2306066B (en) | 1995-10-02 | 1996-10-02 | Method of processing multi-level signals for simple clock recovery |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2306066B (en) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4335381B2 (en) | 1999-10-18 | 2009-09-30 | パナソニック株式会社 | Clock generation apparatus and clock generation method |
AU2003211094A1 (en) * | 2002-02-15 | 2003-09-09 | Quellan, Inc. | Multi-level signal clock recovery technique |
US6816101B2 (en) | 2002-03-08 | 2004-11-09 | Quelian, Inc. | High-speed analog-to-digital converter using a unique gray code |
AU2003256569A1 (en) | 2002-07-15 | 2004-02-02 | Quellan, Inc. | Adaptive noise filtering and equalization |
US7934144B2 (en) | 2002-11-12 | 2011-04-26 | Quellan, Inc. | High-speed analog-to-digital conversion with improved robustness to timing uncertainty |
US7804760B2 (en) | 2003-08-07 | 2010-09-28 | Quellan, Inc. | Method and system for signal emulation |
DE112004001455B4 (en) | 2003-08-07 | 2020-04-23 | Intersil Americas LLC | Cross-talk cancellation method and system |
JP4510832B2 (en) | 2003-11-17 | 2010-07-28 | ケラン インコーポレイテッド | Method and system for antenna interference cancellation |
US7616700B2 (en) | 2003-12-22 | 2009-11-10 | Quellan, Inc. | Method and system for slicing a communication signal |
US7725079B2 (en) | 2004-12-14 | 2010-05-25 | Quellan, Inc. | Method and system for automatic control in an interference cancellation device |
US7522883B2 (en) | 2004-12-14 | 2009-04-21 | Quellan, Inc. | Method and system for reducing signal interference |
KR101372361B1 (en) | 2006-04-26 | 2014-03-12 | 인터실 아메리카스 엘엘씨 | Method and system for reducing radiated emissions from a communications channel |
CN102201810A (en) * | 2010-03-23 | 2011-09-28 | 奇景光电股份有限公司 | Device and method for controlling clock recovery |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2840006C2 (en) * | 1978-09-14 | 1980-10-02 | Deutsche Itt Industries Gmbh, 7800 Freiburg | CMOS circuit for converting a ternary signal into two binary signals and using this CMOS circuit |
US4464771A (en) * | 1982-04-02 | 1984-08-07 | Motorola, Inc. | Phase-locked loop circuit arrangement |
GB2143096B (en) * | 1983-07-06 | 1987-02-04 | Motorola Israel Ltd | Clock recovery circuit |
US5237590A (en) * | 1989-03-13 | 1993-08-17 | Hitachi, Ltd. | Timing extraction circuit and communication system utilizing the same |
US5115450A (en) * | 1989-07-06 | 1992-05-19 | Advanced Micro Devices, Inc. | High speed digital to analog to digital communication system |
-
1996
- 1996-10-02 GB GB9620488A patent/GB2306066B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB2306066B (en) | 2000-02-16 |
GB2306066A (en) | 1997-04-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20131002 |