JP2001119037A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having improved characteristics and reliability. SOLUTION: This semiconductor device is provided with an insulation substrate, a semiconductor film containing a region that is formed at the upper portion of the insulation substrate and has added P-type or N-type impurities, a gate insulation film that is formed in contact with the semiconductor film, a gate electrode where a side surface formed in contact with the gate insulation film is into a tapered shape, an interlayer insulation film formed at the upper portion of the gate electrode, and wiring that is formed on the interlayer insulation film and is connected to a region, where the P-type or N-type impurities have been added.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating gate type semiconductor device on an insulating substrate at a low temperature of 450 ° C. or less and an integrated circuit in which many of them are formed with good yield.
And a semiconductor device formed by such a method. The semiconductor device according to the present invention is used as a drive circuit for an active matrix such as a liquid crystal display, an image sensor, or the like, or as a thin film transistor in an SOI integrated circuit or a conventional semiconductor integrated circuit (a microprocessor, a microcontroller, a microcomputer, a semiconductor memory, or the like). Is what is done.

[0002]

2. Description of the Related Art In recent years, research on forming an insulated gate semiconductor device (MOSFET) on an insulating substrate has been actively conducted. Forming a semiconductor integrated circuit on an insulating substrate in this manner is advantageous in driving the circuit at high speed. Because
This is because the speed of the conventional semiconductor integrated circuit is mainly limited by the capacitance (floating capacitance) between the wiring and the substrate, but such a floating capacitance does not exist on the insulating substrate. A MOSFET formed on an insulating substrate and having a thin-film active layer is called a thin film transistor (TFT). In a conventional semiconductor integrated circuit, for example, SRA
A TFT is used as the M load transistor.

[0003] Recently, a product that requires a semiconductor integrated circuit to be formed on a transparent substrate has appeared. For example, a driving circuit for an optical device such as a liquid crystal display or an image sensor. Here also, a TFT is used. Since these circuits are required to be formed in a large area, a lower temperature of the TFT manufacturing process is required. Also, for example, in a device having a large number of terminals on an insulating substrate, even when the terminals need to be connected to the semiconductor integrated circuit, in order to reduce the packaging density, the first stage of the semiconductor integrated circuit, Alternatively, it has been considered to form the semiconductor integrated circuit itself monolithically on the same insulating substrate.

Conventionally, a TFT has been coated with an amorphous, semi-amorphous, or microcrystalline semiconductor film.
Annealing at a temperature of from 1 to 1200 ° C. has improved the crystallinity and improved the quality of the semiconductor film (that is, the mobility is sufficiently large). Amorphous TFT using amorphous material for semiconductor coating
Although mobility is less than 5 cm ² / Vs, usually 1 cm
Its use is greatly limited because it is as small as about ² / Vs, the operation speed is low, and the P-channel type TFT cannot be obtained. TFT with mobility of 5 cm ² / Vs or more
In order to obtain the above, annealing at the above temperature was necessary. Further, a P-channel TFT (PTFT) could be formed by such annealing.

[0005]

However, in such a thermal process, the substrate material is significantly restricted. In other words, in a so-called high-temperature process (a process in which the maximum process temperature is 900 to 1200 ° C.), a high-quality thermal oxide film can be used as the gate oxide film. Only materials that were difficult to convert could be used.

On the other hand, in a low-temperature process (a process in which the maximum process temperature is 450 to 750 ° C.), a wider range of substrate materials can be selected than in a high-temperature process. Distortion and shrinkage are problems. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has an object to overcome the above-described restrictions on substrate materials and the problems of distortion and shrinkage, in which the maximum process temperature is 450 ° C. or less. .

[0007]

The present invention is characterized in that the crystallinity of a semiconductor film is improved not by a conventional thermal equilibrium process but by irradiation of a pulsed laser beam or similar intense light. Is what you do. As a result, annealing to improve the crystallinity of the semiconductor coating no longer determines the maximum process temperature, but other factors (eg, hydrogenation anneal, gate oxide anneal, etc.) determine the maximum process temperature. As a result, the range of substrate selection is significantly improved.

For example, soda glass or alkali-free glass (for example, Corning 7059 glass) has a low softening point, and it has been conventionally impossible to form and operate a TFT thereon, but according to the present invention, With appropriate measures, the TFT can be operated.

The process of the present invention comprises a step of forming a semiconductor film on an insulating substrate, a step of forming an insulating film which is transparent to laser light or similar strong light thereon, and a step of forming a pulse on this laminated film. Irradiating a laser beam or a similar intense light thereon to improve the crystallinity of the semiconductor film; removing the insulating film to form a gate insulating film on the surface of the semiconductor film; A step of introducing an impurity element into a semiconductor film in a self-aligned manner by ion implantation or ion doping using the gate electrode as a main mask, and further irradiating a pulsed laser beam or similar intense light. And improving the crystallinity of the semiconductor film destroyed in the process of introducing the impurity element. Further, the latter two steps may be replaced by laser doping (for example, Japanese Patent Application No. 4-100479) filed by the present inventors. In the present invention, a low-resistance metal material such as aluminum is preferable as a material of the gate electrode and the wiring. The pulse laser used in the present invention includes KrF, Ar
An ultraviolet laser such as an excimer laser such as F, XeCl, or XeF is desirable. Preferably, the insulating substrate and the semiconductor film are provided with an insulating film made of a material selected from silicon nitride, aluminum oxide, and aluminum nitride, or a laminated film of the insulating film and a silicon oxide film. This silicon oxide film has a thickness of 300 to 3000 °, preferably 500 to 1500 °. The insulating film made of a material selected from the group consisting of silicon nitride, auminium oxide and aluminum nitride has a thickness of 300 to 3000 °, preferably 1000 to 2 °.
000. Further, halogen infrared lamp light can be used as the strong light. The intense light (pulse light) equivalent to laser light is light energy or light energy for crystallization within a short time within a range where impurities are not sufficiently segregated during crystallization, generally within 5 minutes. Means the auxiliary energy of heat.

A feature of the present invention is that the protective layer provided when the crystallinity of the active layer is improved by irradiation with laser light or similar intense light is removed, and another film is formed as the gate insulating film. It is to use. Through this process, various characteristics of the TFT could be significantly improved. This is assumed as follows. That is, in crystallization from such an amorphous state, the interface is not always clear, and a compound having a non-stoichiometric ratio is often formed at the interface. In this case, silicon oxide containing much silicon is likely to be formed near the interface. However, such a non-stoichiometric silicon oxide works only insufficiently as an insulator or a semiconductor. It is well known that the interface is important in an insulated gate element, but sufficient characteristics cannot be obtained if silicon oxide having such a non-stoichiometric ratio is left.

However, if irradiation with laser light or similar strong light is performed without any protective layer, the surface of the film will have severe irregularities, and sufficient characteristics cannot be obtained. To remove the protective layer once provided as in the present invention means to also remove the above-mentioned non-stoichiometric silicon oxide. Silicon will appear at the interface. In particular, good results were obtained by performing wet etching using hydrofluoric acid or the like to remove the protective layer. While dry etching causes damage to the silicon film, wet etching does not cause such damage, and fluorine or hydrogen before the dangling bond of the outermost silicon atom double bonds with another silicon atom. It is thought that this is because the extremely stable surface is formed.

In the present invention, the depth of a region having good crystallinity formed by annealing with laser light or similar strong light is described in Japanese Patent Application No. 50793/1991 by the present inventors. The active layer may be freely set or changed as required, and as a result, the active layer may have a two-layer structure to reduce the leak current between the source and the drain. Further, in the present invention, when annealing with a laser or infrared lamp,
Auxiliary heating at 0 to 500 ° C, typically 300 to 400 ° C, is preferable because uniformity is improved.

A first application example of the present invention is a peripheral circuit of an active matrix (AM) type liquid crystal display (LCD) using amorphous silicon (a-Si) TFT. The a-SiTFT-AMLCD uses an alkali-free glass (for example, Corning 7059) as a substrate and usually forms an a-SiTFT at a temperature of 400 ° C. or lower. However, the a-SiTFT has a high OFF resistance,
Although it is ideal as an active matrix switching element, the peripheral drive circuit uses a single crystal integrated circuit (IC) because the operation speed is slow and a CMOS cannot be formed as described above. The terminals of the matrix are connected to the terminals of the IC by a method such as TAB. However, such a mounting method becomes more difficult as the size of the pixel becomes smaller, and the cost required for mounting occupies a large part of the module.

However, in the conventional process, it is difficult to form a peripheral circuit on the same substrate as the matrix because of a thermal problem. However, according to the present invention, a TFT having higher mobility can be formed at the same temperature as that required for forming an a-Si TFT.

A second application is to form a TFT on a material such as soda glass which is less expensive than non-alkali glass. In this case, when the TFT is formed in close contact with soda glass, mobile ions such as sodium contained in the glass penetrate, so that an insulating film containing silicon nitride, aluminum oxide, or aluminum nitride as a main component is formed on the glass. It is desired to form a TFT after forming a base insulating film thereon using a material such as silicon oxide. In order to further reduce defects, the matrix TFT should be NT
It is preferable to use a PTFT over an FT. This is because, in the case of NTFT, when mobile ions enter from the substrate, a channel is formed and the TFT is always on. On the other hand, in the case of PTFT, no channel is formed even if mobile ions enter.

As a third application example, there is a peripheral circuit of a simple matrix LCD which performs static driving. For example, since a ferroelectric liquid crystal material (FLC) has a memory property, a high contrast can be obtained even with a simple matrix, but conventionally, a peripheral circuit is a-SiTFT-AML.
Like the CD, the IC was connected by TAB or the like. Similarly, an LCD that performs a static operation using a phase change between a cholesteric phase and a nematic phase of a liquid crystal
Also, the peripheral circuits were connected by TAB. LCDs that perform static driving by combining a nematic liquid crystal and a ferroelectric polymer (for example, see
−1152) has also been proposed, but the peripheral circuit is still T
It is assumed that AB connection is established.

Since these LCDs are simple matrices, they are characterized in that a large screen can be obtained using an inexpensive substrate and higher definition can be obtained. In order to achieve high definition, the pitch between terminals must be narrowed, but this makes it difficult to mount ICs.
According to the present invention, a peripheral circuit can be formed monolithically without worrying about a thermal problem even with an inexpensive substrate.

As a fourth application example, a TFT is formed in a semiconductor integrated circuit after a metal wiring is formed.
A so-called three-dimensional IC can be used. Various other applications are also possible.

[0019]

[Embodiment 1] An example in which a peripheral circuit of an active matrix (AM) type LCD using an a-Si TFT is formed according to the present invention will be described. As described above, the conventional s-SiTFT AMLCD is formed by TAB connection because the peripheral circuit cannot be integrally formed. However, in the TAB method, the cost of the IC and the cost for the connection are enormous, and occupy more than 20% of the panel module. This was monolithically formed on the same glass substrate to reduce costs.

First, a substrate (Corning 7059, 300
mm × 300mm or 100mm × 100mm) 1
01 as a base oxide film 102 having a thickness of 100 to 300 n
m silicon oxide film was formed. As a method of forming this oxide film, a film obtained by decomposing and depositing a TEOS by a plasma CVD method or a sputtering method in an oxygen atmosphere may be annealed at 450 to 650 ° C.

Thereafter, a plasma CVD method or an LPCVD method
The amorphous silicon film 103 by 30 to 1
Deposit 50 nm, preferably 50-100 nm.
Then, as a protective layer 104 by a plasma CVD method,
Acid having a thickness of 20 to 100 nm, preferably 50 to 70 nm
A silicon oxide or silicon nitride film was formed. And FIG.
As shown in (A), a KrF excimer laser (wavelength 2
Irradiation of 48 nm and pulse width of 20 nsec.
The crystallinity of the film 103 was improved. Laser energy
-Density is 200 to 400 mJ / cm^Two , Preferably 25
0-300mJ / cm ^Two And Formed in this way
The crystallinity of the etched silicon film 103 by Raman scattering spectroscopy.
The peak of single crystal silicon (521c
m^-1) Different from 515cm^-1Blow relatively near
Peak was observed. At the time of laser irradiation, 100 ~
Auxiliary heating at 500 ° C improves crystal uniformity
You. Thereafter, annealing was performed at 350 ° C. for 2 hours in hydrogen.

Next, the protective layer 104 is removed to expose the silicon layer 103, which is patterned into an island shape.
An NTFT region 105 and a PTFT region 106 were formed.
Further, a gate oxide film 107 was formed by a sputtering method in an oxygen atmosphere or a method of annealing a film obtained by decomposing and depositing TEOS by a plasma CVD method at 450 to 650 ° C. In particular, when using the latter method, the temperature in this step may cause distortion or shrinkage of the substrate, which may make subsequent mask alignment difficult.Therefore, care must be taken when handling large-area substrates. Must. Although the substrate temperature can be set to 150 ° C. or lower by sputtering, it is desirable to perform annealing at about 450 ° C. in hydrogen in order to reduce dangling bonds and the like in the film and reduce the influence of fixed charges.

Thereafter, an aluminum film having a thickness of 200 nm to 5 μm is formed by an electron beam evaporation method, and this is patterned, and as shown in FIG.
08 and 109 were formed. At this time, a TFT (inverted stagger type) gate electrode 110 in the active matrix portion is also formed at the same time.

Further, as shown in FIG. 1C, the substrate was immersed in an electrolytic solution, a current was passed through the gate electrode, and anodic oxide layers 111 to 113 were formed therearound. In this case, Japanese Patent Application No. Hei 4-3022, which was an invention of the present inventors, was made.
As shown in FIGS. 0, 4-38637 and 4-54322, the anodic oxide film of the TFT in the peripheral circuit region (that is, the TFT on the left side of the figure) is thinned to improve the mobility,
Further, it is desirable to adopt a configuration in which the anodized film of the TFT in the active matrix portion (that is, the inverted staggered TFT on the right side of the figure) is made thick to prevent gate leak. In this embodiment, the thickness of the anodic oxide film is 200
２５０250 nm.

Thereafter, impurities were implanted into the island-like silicon film of each TFT in a self-aligned manner by using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) as a mask by ion doping. At this time, first, phosphorus is injected into the entire surface using phosphine (PH ₃ ) as a doping gas, and then only the island-like region 105 in the figure is covered with a photoresist, and diborane (B ₂ H ₆ ) is used as a doping gas. , Boron was implanted only in the island region 106. The dose amount is 2 to 8 × 10 ¹⁵ cm ⁻² for phosphorus and 4 to 10 × 1 for boron.
It was set to 0 ¹⁵ cm ^-2 and the boron dose was set to be higher than that of phosphorus.

Thereafter, as shown in FIG. 1D, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
ec) was applied to improve the crystallinity of the portion where the crystallinity was deteriorated by introducing the impurity region. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . At the time of this laser irradiation, if the auxiliary heating is performed at 100 to 500 ° C., the uniformity of the crystal is improved.

As a result, N-type regions 114 and 115 and P-type regions 116 and 117 were formed. The sheet resistance in these regions was 200 to 800 Ω / □. After that, a silicon oxide film having a thickness of 300 nm was formed over the entire surface as an interlayer insulator 118 by a sputtering method. This may be a silicon nitride film formed by a plasma CVD method. Although this film is merely an interlayer insulator in the peripheral circuit, it becomes a gate insulating film of the TFT in the active matrix portion.
Care must be taken in its fabrication.

Thereafter, an amorphous silicon layer 119 having a thickness of 20 to 50 nm is formed on the gate electrode 110 in the active matrix portion, and a microcrystalline silicon layer serving as a source / drain of an a-Si TFT is formed by a plasma CVD method. (Thickness 50-100 nm)
Was formed and patterned to form source / drain 120 and 121.

Thereafter, contact holes were formed in the source / drain of the TFT in the peripheral circuit portion, and aluminum wirings 122, 123, and 124 were formed. In this case, the left NTFT and PTFT form an inverter circuit. Further, the pixel electrode 125 was formed of a transparent conductive material (such as ITO) on the TFT in the active matrix portion. Finally, annealing was performed at 350 ° C. for 2 hours in hydrogen to reduce dangling bonds in the silicon film. Through the above steps, the peripheral circuit and the active matrix circuit were integrally formed. In this embodiment, an inverted-staggered TFT is used as the a-Si TFT of the active matrix. However, since the conductivity of a-Si changes by light irradiation, light is prevented from entering the channel portion. That's why. If sufficient measures against external light are taken, it goes without saying that a normal planar type TFT may be used.

FIG. 6 shows an example of the characteristics of the TFT of the peripheral drive circuit section manufactured in this embodiment. This is because a 20 nm thick silicon film is formed on a 50 nm thick silicon film formed by LPCVD.
m is formed by forming a protective layer and crystallizing it with a KrF laser in a vacuum. The energy density of the laser at this time was 250 mJ / cm ² , and 10 shots were irradiated.
Further, after removing the protective layer, a silicon oxide film having a thickness of 120 nm was formed by a sputtering method, and this was used as a gate oxide film. Then, after forming the gate electrode, an anodic oxide film having a thickness of 206 nm is formed by an anodic oxidation method, and by using this as a mask, phosphorus ions are accelerated to 65 keV and boron ions are accelerated to 80 keV, and through-implantation is performed. ,
Impurity regions are formed in a self-aligned manner, and Kr
F laser (energy density 300 mJ / cm ² , 10
Shot) was activated.

FIG. 6A shows an NTFT, and FIG. 6B shows a PTFT.
The characteristics of the FT are shown. The size of the TFT channel is 3.5 μm in length and 15 μm in width. The electric field mobility is 60 cm ² / Vs for NTFT and 30 for PTFT.
cm ² / Vs. The S value indicating the sharpness of the ON / OFF of the TFT is 0.42 V / digit for NTFT, and the PTF
0.53V / digit at T, threshold voltage of 3.9 for NTFT
V and PTFT were -5.4V. Set the drain voltage to 1
V / -1V, the ON / OFF ratio is NT
It was 8.7 digits for FT and 6.9 digits for PTFT.

Embodiment 2 An example in which an active matrix is formed on a soda glass substrate will be described. As the substrate 201, a soda glass substrate (thickness: 1.1 mm, 300 × 40
0 mm). Since soda glass contains a large amount of sodium, a thickness of 5 to 50 nm is applied to the entire surface by a plasma CVD method so that the sodium does not diffuse into the TFT.
Preferably, a silicon nitride film 202 of 5 to 20 nm is formed. As described above, the technique of coating a substrate with a film of silicon nitride or aluminum oxide and using the film as a blocking layer is disclosed in Japanese Patent Application No. 3-2387 filed by the present inventors.
10, 3-328714. Further, the film 202 may be aluminum nitride.

Next, after forming a base oxide film 203 (silicon oxide), a silicon film 204 (thickness: 30 to 150 nm, preferably 3 nm) is formed by LPCVD or plasma CVD.
0 to 50 nm), and a protective layer 20 of silicon oxide.
5 was formed. Then, as shown in FIG.
The crystallinity of the silicon film 204 was improved by irradiating a laser beam. However, at this time, the energy density of the laser beam was set to 150 to 200 mJ / cm ² , which was slightly lower than that in Example 1, and the number of shots was set to 10 times. As a result, the crystallinity of the silicon film obtained at this time was closer to amorphous than that of Example 1. Actually, the electric field mobility of the holes of the silicon film obtained in this state was 3 to 10 cm ² / Vs, which was smaller than that of Example 1.

Next, the protective layer was removed, the silicon film was patterned into island-like regions 206, and a gate oxide film 207 having a thickness of 50 to 300 nm, preferably 70 to 150 nm was formed by sputtering. Further, an aluminum gate electrode 208 was formed in the same manner as in Example 1, and the periphery was covered with an anodic oxide 209. Figure 2 shows this situation.
It is shown in (B).

Thereafter, boron as a P-type impurity is implanted into the silicon layer by ion doping in a self-aligned manner.
The source / drain 210 and 211 of FT are formed, and further, as shown in FIG. 2C, KrF laser light is applied to the source / drain 210 and 211 to reduce the crystallinity of the silicon film whose crystallinity is deteriorated due to the ion doping. Was improved. However, at this time, the energy density of the laser beam is 250 to 30.
It was set as high as 0 mJ / cm ² . Therefore, this TF
The source / drain sheet resistance of T is 400-800Ω
/ □ was equivalent to that of Example 1.

As described above, although the electric field mobility of the active layer is small, this is convenient for use as an active matrix TFT. That is, although the ON resistance is high, the OFF resistance is sufficiently higher than that, so that it is not necessary to provide an auxiliary capacitor as in the related art. In particular, mobile ions such as sodium cause a leak current in an N-channel MOS, but there is no problem since the present embodiment is a P-channel MOS.

In this embodiment, the maximum process temperature is limited to 350 ° C. for forming a silicon nitride film or a silicon oxide film. At a higher temperature, the soda glass is softened. When a process at such a remarkably low temperature is required, a defect of the gate oxide film becomes a problem. In the case of Example 1, since the heat resistance of the substrate was relatively good, the gate oxide film could be annealed at a temperature up to 450 ° C., but this is not possible with a soda glass substrate. As a result, many fixed charges are left in the gate oxide film.
The fixed charge in this case is mainly a positive charge. Therefore, in the N-channel type MOS, the leak between the source and the drain is large due to the influence of the fixed charge, and the MOS cannot be actually used. However, in the P-channel type MOS, although the fixed charge has an effect on the threshold voltage, the characteristic of low leakage which is indispensable for the operation of the active matrix is maintained. On the other hand, since the source / drain is annealed with a high energy laser, the sheet resistance is small and the signal delay is suppressed.

After that, the interlayer insulator 2 is made of polyimide.
12, and the pixel electrode 213 was formed by ITO. Then, a contact hole is formed, and T
Electrode 21 made of aluminum on the source / drain region of FT
4, 215 are formed, and one of the electrodes 215 is IT
O was also connected. Finally, in hydrogen at 300 ° C
For 2 hours to complete the hydrogenation of silicon.

Four active matrices were formed on one substrate thus manufactured, and the four active matrices were cut out to take out four active matrix panels. Since a peripheral circuit is not attached to the active matrix obtained in this embodiment, the peripheral circuit must connect a driving IC by TAB or the like. However, if the substrate is a conventional a
-Soda glass is cheaper than the non-alkali glass substrate used in the SiTFT-AMLCD, so it is sufficiently profitable in terms of cost. In particular, the panel manufactured in this example was suitable for a large screen and high definition panel. FIG.
FIG. 1 shows a schematic diagram of the obtained active matrix.
Reference numeral 952 denotes an active matrix, and 951 denotes a peripheral circuit. The peripheral circuit 951 has a driver TFT and a shift register. 953 is an active matrix pixel, 956 is an active matrix TFT,
954 is a liquid crystal layer, and 955 is an auxiliary capacitance.

For example, since the mobility of the conventional a-Si TFT is about 0.5 to 1.0 cm ² / Vs, it cannot be used for a large-scale matrix having more than 1000 rows. However, in the present embodiment, it is 3 times higher than a-Si.
Since the mobility is as large as 10 to 10 times, not only there is no problem but also it can sufficiently respond to analog gradation display. In addition, since both the gate line and the data line are made of aluminum, signal delay and attenuation can be significantly reduced, especially on a large screen having a diagonal exceeding 20 inches.

Embodiment 3 In this embodiment, in a high-contrast LCD utilizing the diode characteristics and the memory characteristics of a ferroelectric polymer, the cost can be reduced by integrally forming the peripheral circuits on a substrate. An example is shown. An LCD having such a configuration is described in, for example, Japanese Patent Application No. 61-1152.

Since this LCD can perform a semi-static operation, it can display a very high contrast even with a simple matrix using a TN liquid crystal. In addition, there are few problems in manufacturing such as the MIM type non-linear element. This operating principle is illustrated in FIG.

As shown in FIG. 4A, a general ferroelectric substance has a hysteresis in the E (electric field) -D (electric flux density) characteristic. That is, a constant polarization is always generated in the ferroelectric material until an external electric field of a certain magnitude is applied, but when an electric field of a certain magnitude or more is applied, the internal polarization is reversed. In this case, movement of electric charge, that is, electric current occurs in an electric circuit. For example, consider a circuit in which a capacitor (FE) sandwiching a ferroelectric and a capacitor (LC, capacity is C) sandwiching a material such as liquid crystal are connected in series. In practice, a ferroelectric capacitor often includes a relatively large resistance R in parallel. Therefore, an actual circuit is as shown in FIG. Where F
It should be noted that E has not only a capacitor but also a non-linear resistance component in parallel. And
When a change in current flowing into the circuit is examined by applying an alternating current to such a circuit, a non-linear characteristic having hysteresis is obtained as shown in FIG. 4B.

If the potential of the counter electrode is -V ₀ or 0 on one side and 0 or + V ₀ on the other side, the voltage applied to the cell is:
± 2V ₀ , ± V ₀ , or 0. When the voltage becomes any of ± 2V ₀ , as shown in FIG. 4 (B), during the transition, the resistance of the FE is significantly reduced, and sufficient charge is supplied to the LC. Becomes Then, regardless of the transition to either the state of ± V0 or 0, FE
Does not decrease so much, and only the leakage current from the parallel resistance R becomes a problem during this period. This leakage current causes the charge of the LC to be lost. That is, ± 2V ₀
Is a selected state, and the other states are non-selected states.

A straight line passing through the origin indicated by a chain line in FIG. 4B is a current leak due to R.
The relationship between C and C is important for use as an LCD.
Although a detailed discussion is omitted, the time constant of this pixel τ = RC
However, if the period is extremely shorter than the period of one frame, the contribution of FE is small, that is, the contrast is reduced. On the other hand, τ
Is extremely longer than the period of one frame, an afterimage occurs at the time of image rewriting, and it becomes very difficult to see. Therefore, it is better to make τ as close as possible to the period of one frame.

FIG. 5 shows an outline of the cell. Like a normal LCD, it has a structure in which a liquid crystal material 512 is sandwiched between two substrates 501 and 502. A spacer 511 is interposed to make the cell thickness uniform. Liquid crystal materials include TN liquid crystal and STN liquid crystal, non-twist mode nematic liquid crystal and ferroelectric liquid crystal using birefringence, and dispersion liquid crystal (PDLC) in which liquid crystal such as nematic and cholesteric is dispersed in a polymer. Various things can be used.

As with a general simple matrix, ITO
And the like, and the formed striped electrode 505
And 506 are arranged so as to be orthogonal to each other, except that a transparent conductive film such as an island-shaped ITO is formed on one electrode 506 with a ferroelectric polymer 507 interposed therebetween. I have. Orientation films 509 and 510 are formed to cover these electrodes. Detail is,
It is described in Japanese Patent Application No. 61-1152.

Now, in such an LCD, the driving is performed by the TAB connection of the IC as in the past, but this is limited in several points. For one thing, in an LCD of this type, the voltage applied to the liquid crystal is either 1 or 0, and moreover, in order to achieve the high contrast characteristic of this type, this voltage is almost one frame. Will be applied during this period. Therefore, if gradation display is to be performed, it is difficult to perform analog gradation display such as that performed by a TFT LCD, and it is not possible to employ a pulse modulation method or a frame modulation method that is performed by an STN LCD. As a result, it relies on area gray scale, and therefore the number of pixels is greatly increased.

As such, there is no inherent difficulty in this LCD. This is because LCDs of this kind have a simple structure, and are rather good at large-capacity matrices. However, actually, the connection terminal density is 20 pins /
mm, it is no longer possible to cope with the TAB method, and it is difficult to produce even by the COG (chip-on-glass) method. Therefore, it has been required to form a peripheral driving circuit monolithically on the same substrate.

For example, in order to achieve an area gradation of 64 gradations, one pixel requires six sub-pixels, and requires two to three times the number of rows of a normal matrix. Therefore, X
In the case of a high-definition screen such as the GA standard, if this method is adopted, the number of lines reaches 1500 to 3000 lines. Therefore, even a large screen having a diagonal size of 15 inches requires 10 to 15 lines / mm. Furthermore, as the screen becomes smaller, higher density mounting is required. In particular, when a projection type display is configured using the LCD of the present system and PDLC which is a high transmittance liquid crystal, the substrate size is 5 inches or less diagonally.

At this time, not only high-density mounting but also high-speed operation of the IC is required. In this case, the circuit on the insulating substrate has a smaller loss than the circuit on the single crystal semiconductor substrate, and can operate at high speed. However, as in Example 2 in this case, the BECAUSE the problems field mobility is less than 10 cm ² / Vs, mobility 30 cm ²
/ Vs or more, preferably 50 cm ² / Vs or more.

Therefore, a low-temperature process by laser annealing of the present invention or annealing by strong light similar to laser light is desired. Hereinafter, the peripheral circuit manufacturing process described in FIG. 3 will be described. As the substrate 301, Corning 7059 or an alkali-free glass substrate equivalent thereto was used. The size of the substrate is 300mm x 400mm
Met. A base oxide film (silicon oxide) 302 was formed thereon, a silicon layer 303 and a protective layer 304 were formed, and laser irradiation was performed under the same conditions as in Example 1 as shown in FIG.

Thereafter, the silicon layer was patterned into an island shape, an NTFT region 305 and a PTFT region 306 were formed, and a gate oxide film (silicon oxide) 307 was formed. Then, as shown in FIG. 3B, aluminum gate electrodes 308 and 309 were formed. At this time, since aluminum needs to withstand the subsequent laser irradiation, aluminum formed by electron beam evaporation having high reflectance was used. The aluminum formed by the sputtering method had a grain size of about 1 μm and had an extremely rough surface, so that it was significantly damaged by laser irradiation. The surface of the aluminum film formed by electron beam evaporation was so flat that the presence of grains could not be confirmed by an optical microscope.
As a result of observation by an electron microscope, the grain size was 200
nm or less. That is, the particle size must be smaller than the wavelength of the laser used.

Next, an N-type impurity (phosphorus) is introduced into the regions 310 and 311 and a P-type impurity (boron) is introduced into the regions 312 and 313 by ion doping, and laser annealing is performed as shown in FIG. Was. Laser irradiation conditions were the same as in Examples 1 and 2. This laser irradiation hardly damaged the aluminum gate electrode.

Finally, as shown in FIG. 3D, an interlayer insulator (silicon oxide) 314 is formed, a contact hole is formed in the interlayer insulator 314, and T
Connection between FTs was made. Thus, a peripheral circuit was formed. Although not shown in the figure, a stripe-shaped ITO film is formed thereafter to form a pixel electrode.
Divided into two pieces and the size of one piece is 150mm x 200mm
4 substrates are taken out, and two more substrates are
A ferroelectric polymer or the like was formed by the method described in 1-1152. Then, two substrates as shown in FIG. 5 were adhered to complete the LCD.

Embodiment 4 FIG. 7 shows this embodiment. In this embodiment, the laser crystallized silicon TFT of the present invention is used for the peripheral circuit of the TFT type liquid crystal display device. However, unlike the first embodiment, the TFT in the active matrix region is of a top gate type (gate is Amorphous silicon (in the opposite direction to the substrate). In this case, the active layers of both TFTs can be manufactured by the same process, but it is required that both the characteristics of laser crystallization and the characteristics as amorphous silicon are excellent.
Conditions are somewhat strict.

First, a base oxide film 702 having a thickness of 20 to 100 was formed on a Corning 7059 substrate 701 by sputtering.
200 nm was deposited. Further, a plasma CVD method using monosilane or disilane as a raw material is further performed thereon.
An amorphous silicon film was deposited to a thickness of 50 to 150 nm. At this time, the amorphous silicon film is required to function as it is as an a-Si TFT, and is also required to withstand laser irradiation. According to the knowledge of the present inventors, an amorphous silicon film having excellent characteristics can be obtained by setting the substrate temperature to 300 to 400 ° C. when forming an amorphous silicon film. On this amorphous silicon film, a protective silicon oxide film (thickness: 10 to 50 nm) 705 was formed again by the sputtering method. afterwards,
Only the peripheral circuit was irradiated with laser light by covering the active matrix region with a photoresist 706 or the like.

In this state, laser irradiation was performed as shown in FIG. The type and conditions of the laser used were the same as in Example 1. However, the energy density of the laser at this time was more preferably 200 to 250 mJ / cm ² . This is because the amorphous silicon film formed by the plasma CVD method contains an excessive amount of hydrogen, and when a strong laser beam is irradiated, hydrogen gasifies, expands, and the film is destroyed. It is. Thus, the silicon film was crystallized to form a crystallized region 704. On the other hand, since the laser light did not reach the portion covered with the photoresist, it remained amorphous silicon.

Thereafter, these Si films are patterned into an island shape, for example, as shown in FIG. 7B, the island region 707 of the peripheral circuit and the island region 70 of the active matrix region.
8 was formed. Further, a silicon oxide film was formed by sputtering to cover these island-shaped regions, and this was used as a gate insulating film 709. Then, similarly to the first embodiment, the metal gate electrodes 710, 711, 71 covered with the anodic oxide film
2 was formed.

Next, as shown in FIG. 7C, an N-type impurity is added to the regions 713 and 715, and a P-type impurity is added to the region 714.
And then irradiated with a laser beam to crystallize the region into which the impurities were implanted. The conditions were the same as in Example 1.
And the same. In this case, the areas 716 and 717
Has already been crystallized at the stage of FIG.
No. 18 does not crystallize even in this step. That is, the TFT at the right end of FIG. 7 (TFT in the active matrix area)
Is an a-Si TFT in which the source / drain is crystallized but the active layer is in an amorphous state.

Finally, a silicon oxide film (thickness of 400 to 10) was formed as an interlayer insulator by plasma CVD of TEOS.
00 nm) 719, and an ITO film 720 is formed on the active matrix region in a thickness of 100 to 300 nm.
This was formed and patterned to form a pixel electrode. Further, a contact hole was formed in the interlayer insulator, and metal wirings 721 to 724 were formed thereon. by this,
A TFT active matrix type liquid crystal display device was manufactured. In this liquid crystal display device, the active region of the thin film transistor in the active matrix circuit has lower crystallinity than the active region of the thin film transistor in the peripheral circuit. The active region of the thin film transistor in the active matrix circuit is a substantially amorphous silicon film having a resistivity in the dark of 10 ⁹ Ω · cm or more.

In the method shown in this embodiment, an a-Si TFT having a high OFF resistance is used for the TFT of the pixel as in the first embodiment. In this embodiment, it is a top gate type. In the first embodiment, the number of steps is increased because the steps of manufacturing the TFT of the peripheral circuit and the TFT of the active matrix are different except for the gate electrode manufacturing step. Since the active matrix TFTs are manufactured in parallel, the number of steps can be reduced.

However, an Si film suitable for an a-Si TFT desirably contains a large amount of hydrogen, whereas the crystallization by a laser desirably has a hydrogen content as small as possible. Since the characteristics are thus contradictory, there is a problem that a Si film must be formed so as to satisfy both conditions as much as possible. For example, even in the case of the plasma CVD method, Si produced using high energy plasma such as ECR plasma or microwave plasma
Since the film contains many crystallized clusters, it is ideal for the purpose of the present embodiment, but there is a problem that the OFF resistance is slightly low.

Embodiment 5 FIG. 8 shows this embodiment. In Examples 1 to 4, the TFT regions were separated from each other by being divided. On the other hand, in this embodiment, the TF is formed by forming a silicon layer on one surface, selectively crystallizing the silicon layer, and using a thick insulating film.
The separation between T is performed.

First, an amorphous silicon film having a thickness of 50 to 150 nm or a silicon film having substantially the same low crystallinity as that of the underlying silicon oxide film 802 was deposited on the insulating substrate 801. In this embodiment, since the amorphous silicon film is required to have sufficient laser resistance and high resistance,
The conditions for forming the amorphous silicon film were the same as in Example 4. Thereafter, a silicon oxide film having a thickness of 10 to 500 nm, preferably 10 to 50 nm is formed on the entire surface by a plasma CVD method, and a part thereof is etched,
A thick region 805 and a thin region 806 of a silicon oxide film were formed. At this time, if an equal etching method was used, the step was gentle as shown in FIG. 8A, and the disconnection of the wiring due to the step could be prevented.

In this state, boron was lightly doped, and crystallization was performed by laser irradiation. As a result, as shown in FIG. 8A, part of the amorphous silicon layer was crystallized to become a region 804, and the other region 803 remained amorphous silicon. This region 804 is substantially intrinsic or weak p-type due to boron doping.

This step may be performed by a method as shown in FIG. That is, after a silicon oxide layer is formed, a film having a thickness of 20 to 500 nm is formed thereon using a material that reflects laser light, such as aluminum, titanium, or chromium, or a material that does not transmit laser light, and is patterned. Then, using the film 819 as a mask, the silicon oxide layer is isotropically etched to form a thick region 817 and a thin region 818 in the silicon oxide layer. Thereafter, laser irradiation is performed while the mask 819 remains, and the amorphous silicon layer is selectively crystallized to form a crystallized region 816 and an amorphous silicon region 815.

Next, as shown in FIG. 8B, a gate oxide film (silicon oxide) 807 was formed, and a metal gate electrode 808 having an anodic oxide was formed. At this time, the side surface of the gate electrode was tapered because a wet etching method was used for etching the metal gate. Such a shape was effective in preventing disconnection at the intersection of wiring.

Further, as shown in FIG. 8C, an N-type region 809 and a P-type region 810 are formed by ion doping.
And activated by irradiating it with laser light.
Thereafter, as shown in FIG. 8D, an interlayer insulator 811 is deposited, and a contact hole is provided in the interlayer insulator 811 to form a metal wiring 811.
The circuit was completed by forming 12 to 814. In this embodiment, since a large amount of opaque amorphous silicon remains on the substrate, it cannot be used, for example, in an active matrix area of an LCD, but can be used in a peripheral circuit area or a driving circuit of an image sensor. In the present embodiment, in a circuit requiring a relatively thick active layer (100 nm or more), a step for separating elements is small, and therefore, disconnection of wiring and the like can be significantly reduced. The effect is particularly remarkable in a high-density integrated circuit.

Embodiment 6 FIG. 9 shows this embodiment. In this embodiment, as in the fifth embodiment, a silicon layer is formed on one surface, and the silicon layer is selectively crystallized to separate TFTs. However, in order not to use the uneven oxide film used in Example 5,
Further, disconnection of the wiring can be prevented.

First, an amorphous silicon film having a thickness of 50 to 150 nm or a silicon film having substantially the same crystallinity as that of the underlying silicon oxide film 902 (hereinafter collectively referred to as an amorphous silicon film) is formed on an insulating substrate 901. Deposited. Also in this embodiment, since the amorphous silicon film requires sufficient laser resistance and high resistance, the conditions for forming the amorphous silicon film were the same as those in the fourth embodiment. Further, a thickness of 20 to 10 is applied to the surface of the amorphous silicon film.
A 0 nm protective silicon oxide layer 905 was deposited. This silicon oxide layer 905 may be left as it is to be used as a gate insulating film of the TFT later. However, it should be noted that such a TFT has low mobility as described above. Thereafter, a film having a thickness of 20 to 500 nm was formed using a material that reflects laser light or a material that does not transmit laser light, such as aluminum, titanium, and chromium, and was patterned. Then, as shown in FIG.
Using the coating 906 as a mask, laser irradiation is performed to selectively crystallize the amorphous silicon layer, and the crystallized region 904 and the amorphous silicon region 9 are formed.
03 was formed.

Next, as shown in FIG. 9B, metal gate electrodes 907 and 908 having anodic oxide were formed on the newly formed gate insulating film. At this time, the side surface of the gate electrode was tapered because a wet etching method was used for etching the metal gate. Such a shape was effective in preventing disconnection at the intersection of wiring. Further, a photoresist 909 was applied and patterned, so that only the N-channel TFT was exposed.

Further, using a photoresist as a mask, N
A type impurity was implanted, and a laser beam was irradiated in that state to activate the region 912 into which the N-type impurity was implanted. At this time, if the photoresist does not remain in the region other than the region into which the impurities are implanted, the amorphous silicon is crystallized, and a relatively thick oxide film cannot be used particularly for isolation between elements as in this embodiment. This situation is not preferable because it causes leakage between elements.

Similarly, for a P-channel TFT,
Photoresist 910 is applied and P-channel TFT
A P-type impurity was implanted so that only the portion was exposed to form a P-type impurity region 913. Further, while leaving the photoresist, laser light irradiation was performed as shown in FIG. 9C to activate the region 913 into which the P-type impurity was implanted first. In the above steps, for example, the region 914 between the N-type impurity region 912 and the P-type impurity region 912 is not irradiated with laser light, and thus remains amorphous silicon. Therefore,
Even if a wiring is formed on an insulating film 905 (which is also a gate insulating film) existing thereon,
Even if an inversion layer is formed, the electric field mobility of the amorphous silicon is very small, and the resistance is very large, so that the leakage current is very small and does not actually cause a problem.

Thereafter, as shown in FIG. 9D, an interlayer insulator 915 is deposited, a contact hole is provided therein, and metal wirings 916 to 918 are formed.
The circuit was completed. In this embodiment, as in the case of Embodiment 5, a large amount of opaque amorphous silicon remains on the substrate.
For example, it cannot be used for an active matrix area of an LCD, but can be used for a peripheral circuit area or a driving circuit of an image sensor. In the present embodiment, unlike the fifth embodiment, there is almost no step of the gate electrode, and therefore, disconnection of the wiring and the like can be significantly reduced. The effect is particularly remarkable in a high-density integrated circuit.

FIG. 9E shows a TFT manufactured in this embodiment.
9 is another cross section of the circuit, which is a cross section taken along a dashed-dotted line AB of the N-channel TFT in FIG. As can be seen from the figure, the gate electrode 917 is flat because the crystallized impurity regions 912 and 913 ′ and the element isolation region 914 therebetween are on the same plane. In addition, the wiring 917 ′ contacting the impurity region 913 ′ and the gate electrode 907 has only a step in the contact hole portion and a step in the interlayer insulating film portion. Since there is no step of a thick insulating film for element isolation as in Example 5 or Example 5, it is advantageous in manufacturing a higher-density integrated circuit with high yield.

[Embodiment 7] An example in which an active matrix is formed on a soda glass substrate will be described. As the substrate 201, a soda glass substrate (thickness: 1.1 mm, 300 ×
400 mm). SiO ₂ film 2 on substrate 201
No. 16 was formed (FIG. 10A). Thereafter, a film 202 made of AlN, SiN or Al ₂ O _{3 is formed on} the entire surface of the substrate.
Was formed (FIG. 10A). Thereafter, the same steps as in Example 2 were performed to complete the active matrix.
That is, after forming the base oxide film 203 (silicon oxide),
Silicon film 20 by PCVD or plasma CVD
4 (thickness 30 to 150 nm, preferably 30 to 50 n
m), and a protective layer 205 of silicon oxide was further formed.

Then, as shown in FIG.
The crystallinity of the silicon film 204 was improved by irradiating a laser beam. However, at this time, the energy density of the laser beam was set to 150 to 200 mJ / cm ² , which was slightly lower than that in Example 1, and the number of shots was set to 10 times. As a result, the crystallinity of the silicon film obtained at this time was closer to amorphous than that of Example 1. Actually, the electric field mobility of the holes of the silicon film obtained in this state was 3 to 10 cm ² / Vs, which was smaller than that of Example 1.

Next, the protective layer was removed, the silicon film was patterned into island-like regions 206, and a gate oxide film 207 having a thickness of 50 to 300 nm, preferably 70 to 150 nm was formed by a sputtering method. Further, an aluminum gate electrode 208 was formed in the same manner as in Example 1, and the periphery was covered with an anodic oxide 209. Figure 1 shows this situation.
0 (B).

Thereafter, as a P-type impurity, boron is implanted into the silicon layer by ion doping in a self-aligned manner.
The source / drain 210 and 211 of FT are formed, and further, as shown in FIG. 10 (C), this is irradiated with KrF laser light, and the crystallinity of the silicon film whose crystallinity is deteriorated due to the ion doping is increased. Was improved. But,
At this time, the energy density of the laser light is 250 to 3
It was set as high as 00 mJ / cm ² . Therefore, this T
FT source / drain sheet resistance 400-800
Ω / □, which was equivalent to that of Example 1.

As described above, although the electric field mobility of the active layer is small, it is convenient for use as an active matrix TFT. That is, although the ON resistance is high, the OFF resistance is sufficiently higher than that, so that it is not necessary to provide an auxiliary capacitor as in the related art. In particular, mobile ions such as sodium cause a leak current in an N-channel MOS, but there is no problem since the present embodiment is a P-channel MOS.

In the present embodiment, the maximum process temperature is limited to 350 ° C. for forming a silicon nitride film or a silicon oxide film, and at a higher temperature, the soda glass is softened. When a process at such a remarkably low temperature is required, a defect of the gate oxide film becomes a problem. In the case of Example 1, since the heat resistance of the substrate was relatively good, the gate oxide film could be annealed at a temperature up to 450 ° C., but this is not possible with a soda glass substrate. As a result, many fixed charges are left in the gate oxide film.
The fixed charge in this case is mainly a positive charge. Therefore, in the N-channel type MOS, the leak between the source and the drain is large due to the influence of the fixed charge, and the MOS cannot be actually used. However, in the P-channel type MOS, although the fixed charge has an effect on the threshold voltage, the characteristic of low leakage which is indispensable for the operation of the active matrix is maintained. On the other hand, since the source / drain is annealed with a high energy laser, the sheet resistance is small and the signal delay is suppressed.

Thereafter, the interlayer insulator 2 is made of polyimide.
12, and the pixel electrode 213 was formed by ITO. Then, a contact hole is formed, and T
Electrode 21 made of aluminum on the source / drain region of FT
4, 215 are formed, and one of the electrodes 215 is IT
O was also connected. Finally, in hydrogen at 300 ° C
For 2 hours to complete the hydrogenation of silicon.

Four active matrices were formed on one substrate thus prepared, and the four active matrices were cut out to take out four active matrix panels. Since a peripheral circuit is not attached to the active matrix obtained in this embodiment, the peripheral circuit must connect a driving IC by TAB or the like. However, if the substrate is a conventional a
-Soda glass is cheaper than the non-alkali glass substrate used in the SiTFT-AMLCD, so it is sufficiently profitable in terms of cost. In particular, the panel manufactured in this example was suitable for a large screen and high definition panel. FIG.
FIG. 1 shows a schematic diagram of the obtained active matrix.
Reference numeral 952 denotes an active matrix, and 951 denotes a peripheral circuit. The peripheral circuit 951 has a driver TFT and a shift register. 953 is an active matrix pixel, 956 is an active matrix TFT,
954 is a liquid crystal layer, and 955 is an auxiliary capacitance.

For example, since the mobility of the conventional a-Si TFT is about 0.5 to 1.0 cm ² / Vs, it cannot be used for a large-scale matrix having more than 1000 rows. However, in the present embodiment, it is 3 times higher than a-Si.
Since the mobility is as large as 10 to 10 times, not only there is no problem but also it can sufficiently respond to analog gradation display. In addition, since both the gate line and the data line are made of aluminum, signal delay and attenuation can be significantly reduced, especially on a large screen having a diagonal exceeding 20 inches.

[0086]

According to the present invention, a TFT can be manufactured at a very low temperature and with a high yield. Then, as shown in the examples, various LCDs could be formed using the present invention. This is because in the present invention, the characteristics required by the TFT can be set freely. Although not shown in the examples, the present invention can be applied to single crystal ICs and other ICs.
It may be used to form a so-called three-dimensional IC in which a semiconductor circuit is further stacked on the substrate.

[Brief description of the drawings]

FIG. 1 shows a method for manufacturing a TFT according to the present invention.

FIG. 2 shows a method for manufacturing a TFT according to the present invention.

FIG. 3 shows a method for manufacturing a TFT according to the present invention.

FIG. 4 shows an operation principle of the LCD in the embodiment.

FIG. 5 shows a cell structure of the LCD in the embodiment.

FIG. 6 shows characteristics of a TFT in an example.

FIG. 7 shows a method for manufacturing a TFT according to the present invention.

FIG. 8 shows a method for manufacturing a TFT according to the present invention.

FIG. 9 shows a method for manufacturing a TFT according to the present invention.

FIG. 10 shows a method for manufacturing a TFT according to the present invention.

FIG. 11 shows an active matrix and peripheral circuits according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 Insulating substrate 102 Base oxide film 103 Semiconductor region 104 Protective insulating film 105 Island-like semiconductor region (for NTFT) 106 Island-like semiconductor region (for PTFT) 107 Gate insulating film 108 Gate electrode (for NTFT) 109 Gate electrode (for PTFT) 110 Gate electrode (active matrix a
−Si TFT) 111 to 113 Anodized film 114, 115 N-type impurity region 116, 117 P-type impurity region 118 Interlayer insulator 119 a-Si layer (active layer) 120, 121 N-type microcrystal region 122 to 124 Metal wiring 125 pixel electrode (ITO)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 H01L 27/08 321D 27/08 331 321B

Claims (4)

[Claims] An insulating substrate, a semiconductor film including a region to which P-type or N-type impurities are added, formed above the insulating substrate; and a gate insulating film formed in contact with the semiconductor film. A gate electrode having a tapered side surface formed in contact with the gate insulating film; an interlayer insulating film formed above the gate electrode; and a P-type or N-type formed on the interlayer insulating film and And a wiring connected to the region to which the impurity is added. 2. The semiconductor device according to claim 1, wherein the region to which the P-type or N-type impurity is added is made of crystalline silicon. 3. The semiconductor device according to claim 1, wherein said semiconductor film further includes a region made of amorphous silicon. 4. The semiconductor device according to claim 1, wherein said insulating substrate is made of non-alkali glass.