JP2001117816A - Controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control different kind of controlled systems which are optionally connected after suppressing an increase in the number of pins of an interface. SOLUTION: A decoder 11 generates and outputs various control signals needed to place a 64M DRAM in operation. A decoder 12 generates and outputs various control signals needed to place a 16M DRAM in operation. A selector 13 is provided with output terminals T0 to T23 which are less in number than all the control signals outputted by the decoders 11 and 12. The selector 13 select specific control signals out of the control signals outputted by the decoders 11 and 12 according to the states of a BANKAD terminal and a SEL64 terminal which are set from outside and outputs the control signals to specific output terminals corresponding to the control signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device such as a DRAM controller for controlling the operation of a control target by giving a control signal to a predetermined control target such as a DRAM.

[0002]

2. Description of the Related Art A DRAM controller is, for example, an ASIC.
(Application Specific Integrated Circuit).

[0003] Since DRAMs have different address matrices and capacities depending on the type, different control signals are required.

For this reason, conventionally, a DRAM to be controlled is
It is necessary to design and use a dedicated DRAM controller having an interface configuration according to the requirements.

[0005]

For this reason, conventionally, DR
The AM controller can control only one type of DRAM suitable for the interface that it has, and it is impossible to substitute another type of DRAM.

[0006] If an interface corresponding to each of a plurality of types of DRAMs is provided in parallel, it is possible to arbitrarily connect a plurality of DRAMs. However, the number of pins of the interface increases, and the size and cost are increased. Will rise.

[0007] Such a problem is not limited to the DRAM controller, but the same can be said for a control device that controls a control target by giving a control signal to the control target.

The present invention has been made in view of such circumstances, and an object of the present invention is to suppress an increase in the number of pins in an interface and to control a plurality of types of control objects arbitrarily connected. An object of the present invention is to provide a control device capable of controlling each of them.

[0009]

In order to achieve the above objects, the present invention provides, for example, 16 Mbits and 64 Mbits, respectively.
A plurality of different types of control targets such as a DRAM having an M-bit capacity can be arbitrarily connected, and a predetermined control signal is applied to the connected control targets to control the operation of the control target. In a control device such as a controller, a plurality of control signal generation means such as a decoder, for example, which is provided corresponding to each of the plurality of types of control targets and generates and outputs a control signal to be given to the corresponding control target, Having a smaller number of output terminals than the number of all control signals output by the control signal generating means, and a predetermined signal corresponding to an external instruction among the control signals output by the plurality of control signal generating means. An example in which a control signal is selected, and the selected control signal is output from an output terminal associated with each control signal in advance among the plurality of output terminals. If equipped with a selection unit, such as a selector.

[0010] By adopting such means, a plurality of control signal generating means provided corresponding to each of a plurality of types of controlled objects and generating and outputting control signals to be given to the corresponding controlled objects are respectively output. A predetermined control signal corresponding to an external instruction among the control signals to be performed is selected by the selection means. Then, the control signal selected in this manner is set in advance for each control signal among the number of output terminals smaller than the number of all control signals output by the plurality of control signal generation means, which the selection means has. Output from the associated output terminal. Therefore, while keeping the number smaller than the number of all the control signals output by the plurality of control signal generating means of the output terminal, the control signals generated by the plurality of control signal generating means from the output terminals are output from the output terminals. A required control signal is selected and output, and an arbitrary control target can be controlled by the control signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a main configuration of a DRAM controller configured by applying the control device according to the present embodiment.

[0013] In this figure, reference numeral 1 is enclosed by a broken line.
The DRAM controller according to the present embodiment is indicated with a symbol. And this DRAM controller 1
For example, it is configured on one chip using a single gate array.

The DRAM controller 1 has decoders 11, 12 and a selector 13.

The decoder 11 outputs various control signals for simultaneously controlling one or two DRAMs having a capacity of 64 Mbits (hereinafter referred to as 64M DRAMs) in 16-bit parallel data D0 to D15. And output according to the state of the CASCNT terminal. The control signals output from the decoder 11 are DA0-DA9, DA10, D
A11, LA10, LA11 address signals, RASK signal, WEX signal, 1st 64M DRAM CASHX signal, 1st 64M DRAM CASLX signal, 2nd 64M DRAM CASHX signal, 2nd 64M DRAM CASLX signal, DRAM RD signal and 245 buffer G enable signal There are 22.

The decoder 12 outputs various control signals for simultaneously controlling one to five DRAMs having a capacity of 16 Mbits (hereinafter referred to as 16M DRAMs) in 16-bit parallel data D0 to D15. and
Generate and output according to the state of CASCNT signal etc. The control signals output from the decoder 12 include the address signals DA0 to DA9, the RASK signal, the WEX signal, the CAS0HX signal, and the CAS0LX.
Signal, CAS1HX signal, CAS1LX signal, CAS2HX signal, CAS2LX signal, CAS3HX signal, CAS3LX signal, CAS4HX signal and CAS4LX
22 signals.

The selector 13 receives 22 control signals output from the decoder 11 and 22 control signals output from the decoder 12. The selector 13 is connected to a BANKAD terminal and a SEL64 terminal, the states of which are externally set. Further, the selector 13 has 23 output terminals T0 to T23. Then, the selector 13 selects a predetermined control signal from a total of 44 control signals output from the decoders 11 and 12 according to the states of the BANKAD terminal and the SEL64 terminal, and outputs the selected control signal to a predetermined output terminal.

FIG. 2 is a diagram showing a relationship between selection of a control signal in the selector 13 and an output terminal of the selected control signal. That is, the selector 13 selects and outputs a control signal according to the relationship shown in FIG.

The DRAM constructed as described above
According to the controller 1, 3 as shown in FIGS.
It is possible to control the DRAM in two forms.

(Form using only 16M DRAM)
FIG. 3 is a diagram showing an example of a mode in which only one to five 16M DRAMs are connected and these 16M DRAMs are controlled. In this figure, two 16M DRA
The state where M2 and M3 are connected is shown.

In this case, the 16M DRAMs 2, 3
16-bit parallel data D0-D15 connected to the CPU 4 that accesses the
M controller 1 and 16M DRAMs 2 and 3. Note that the level conversion circuit 5 converts the signal level of the data D0 to D15 between 5V and 3.3V.

DA0-D of each of 16M DRAMs 2 and 3
Terminals T0 to T9 of the DRAM controller 1 are connected to input terminals of the respective signals of A9.

RASK of each of 16M DRAMs 2 and 3
The signal input terminal is a terminal T1 of the DRAM controller 1.
0 is connected respectively.

The input terminals of the WEX signals of the 16M DRAMs 2 and 3 are connected to the terminal T11 of the DRAM controller 1 respectively.
Are respectively connected.

The CASHX signal and CASL of the 16M DRAM 2
Terminals T12 and T13 of the DRAM controller 1 are connected to input terminals of the X signal, respectively.

The CASHX signal and CASL of the 16M DRAM 3
Terminals T14 and T15 of the DRAM controller 1 are connected to the X signal input terminals, respectively.

Then, as described above, the DRAM controller 1
To control only 16M DRAM, BAN
The CAD terminal is fixed at the H level, and the SEL64 terminal is fixed at the L level.

Thus, in this state, the signals DA0-DA9 are output from the terminals T0-T9 of the DRAM controller 1, so that the signals DA0-DA9 are applied to the 16M DRAMs 2,3.
Are correctly input to the input terminals of each signal of DA0-DA9.

The RASK signal and the WEX signal are output from the terminals T10 and T11 of the DRAM controller 1, respectively.
3 correctly input to the RASK signal input terminal and the WEX signal input terminal.

From the terminals T12 and T13 of the DRAM controller 1, a first 16M DRAM (here, 16M DRA)
The CAS0HX signal and CAS0LX signal which are the CASHX signal and CASLX signal for M2) are output, respectively.
The S0HX signal and the CAS0LX signal are correctly input to the CASHX signal and CASLX signal input terminals of the first 16M DRAM 16M DRAM2.

From the terminals T14 and T15 of the DRAM controller 1, a second 16M DRAM (here, 16M DRA)
Since the CAS1HX signal and CAS1LX signal, which are the CASHX signal and CASLX signal for M3), are output, respectively,
The S1HX signal and the CAS1LX signal are correctly input to the CASHX signal and CASLX signal input terminals of the second 16M DRAM 16M DRAM3.

Thus, the 16M DRAMs 2 and 3
Various control signals output from the RAM controller 1 can be correctly received.
It is possible to operate under the control of.

FIG. 4 shows a case where a 64M DRAM and a 16M DRAM are mixedly used.
DRAMs are connected one by one, and this 64M DRAM
FIG. 3 is a diagram showing an example of a mode for controlling a 16M DRAM. The same parts as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this case, the 16-bit parallel data D0-D15 connected to the CPU 4 accessing the 64M DRAM 6 and 16M DRAM 3 are transferred to the DRAM controller 1, 64M DR via the level conversion circuit 5.
Connected to AM6 and 16M DRAM3.

64M DRAM 6 and 16M DRAM
3 is connected to the input terminal of each signal of DA0-DA9.
The terminals T0 to T9 of the AM controller 1 are respectively connected.

64M DRAM 6 and 16M DRAM
The terminal T10 of the DRAM controller 1 is connected to the input terminal of each RASK signal of No. 3.

64M DRAM 6 and 16M DRAM
The terminal T11 of the DRAM controller 1 is connected to the input terminal of each of the WEX signals 3.

The input terminals of the signals DA10 and DA11 of the 64M DRAM 6 are connected to the terminals T18 and T of the DRAM controller 1, respectively.
19 are connected respectively.

The CASHX signal and CASL of the 64M DRAM 6
Terminals T12 and T13 of the DRAM controller 1 are connected to input terminals of the X signal, respectively.

The terminals T22 and T23 of the DRAM controller 1 are connected to the input terminals of the DRAM ED signal and the enable signal of the 64M DRAM 6, respectively.

The CASHX signal and CASL of the 16M DRAM 3
Terminals T14 and T15 of the DRAM controller 1 are connected to the X signal input terminals, respectively.

The DRAM controller 1
To control both the 64M DRAM 6 and the 16M DRAM 3, the BANCAD terminal is fixed at the H level,
In addition, the SEL64 terminal is fixed at the H level.

In this state, the signals DA0-DA9 are output from the terminals T0-T9 of the DRAM controller 1, and the signals DA0-DA9 are output from the terminals T0-DA9 of the 64M DRAM6 and the 16M DRAM3, respectively. Is correctly input to the input terminal of each signal.

The RASK signal and the WEX signal are output from the terminals T10 and T11 of the DRAM controller 1, respectively. Input correctly to the input terminal.

From the terminals T12 and T13 of the DRAM controller 1, a first 64M DRAM (here, 64M DRA) is used.
1st 64M which is CASHX signal and CASLX signal for M6)
The DRAM CASHX signal and the 1st 64M DRAM CASLX signal are output, respectively.
The st 64M DRAM CASLX signal is correctly input to the CASHX signal and CASLX signal input terminals of the 64M DRAM 6.

From the terminals T14 and T15 of the DRAM controller 1, the CAS1HX signal and the CAS1LX signal output from the decoder 12 for the 16M DRAM 3 are supplied to the 16M DRAM CASHX.
Signal and 16M DRAM CASLX signal respectively, so this 16M DRAM CASHX signal and 16M DRAM CASLX
The signal is correctly input to the input terminals of the 16M DRAM 3 for the CASHX signal and the CASLX signal.

From the terminals T18 and T19 of the DRAM controller 1, a first 64M DRAM (here, 64M DRA)
Since the signals of DA10 and DA11, which are the eleventh and twelfth DA signals for M6), are output, the signals DA10 and DA11 are output.
11 are correctly input to the input terminals of the signals DA10 and DA11 of the 64M DRAM 6.

Further, the terminal T2 of the DRAM controller 1
Since the DRAM RD signal and the 245 buffer G enable signal are output from T23 and T23, respectively, the DRAM RD signal and the 245 buffer G enable signal are output from the 64M DRAM.
6 are correctly input to the input terminals of the DRAM RD signal and the enable signal.

Thus, 64M DRAMs 6 and 16
The MDRAM 3 can correctly receive various control signals output from the DRAM controller 1,
It is possible to operate under the control of the RAM controller 1.

(Form using only 64M DRAM)
FIG. 5 is a diagram showing an example of a form in which two 64M DRAMs are connected and the two 64M DRAMs are controlled. 3 and 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this case, the 64M DRAMs 6, 7
16-bit parallel data D0-D15 connected to the CPU 4 that accesses the
M controller 1 and 64M DRAMs 6 and 7.

DA0-D of each of 64M DRAMs 6 and 7
Terminals T0 to T9 of the DRAM controller 1 are connected to input terminals of the respective signals of A9.

RASK of each of 64M DRAMs 6 and 7
The signal input terminal is a terminal T1 of the DRAM controller 1.
0 is connected respectively.

The input terminals of the respective WEX signals of the 64M DRAMs 6 and 7 are connected to the terminal T11 of the DRAM controller 1.
Are respectively connected.

The input terminals of the signals DA10 and DA11 of the 64M DRAM 6 are connected to the terminals T18 and T of the DRAM controller 1, respectively.
19 are connected respectively.

The CASHX signal and CASL of the 64M DRAM 6
Terminals T12 and T13 of the DRAM controller 1 are connected to input terminals of the X signal, respectively.

The input terminals of the DA10 and DA11 signals of the 64M DRAM 7 are connected to terminals T20 and T20 of the DRAM controller 1, respectively.
21 are connected respectively.

The CASHX signal and CASL of the 64M DRAM 7
Terminals T14 and T15 of the DRAM controller 1 are connected to the X signal input terminals, respectively.

The terminals T22 and T23 of the DRAM controller 1 are connected to the input terminals of the DRAM ED signal and the enable signal of the 64M DRAMs 6 and 7, respectively.

The DRAM controller 1
To control the 64M DRAMs 6 and 7
A predetermined bank signal is input to the ANCAD terminal, and the SEL64 terminal is fixed at the H level.

In this state, since the signals DA0-DA9 are output from the terminals T0-T9 of the DRAM controller 1, the signals DA0-DA9 are output from the 64M DRAMs 6,7.
Are correctly input to the input terminals of each signal of DA0-DA9.

Since the RASK signal and the WEX signal are output from the terminals T10 and T11 of the DRAM controller 1, the RASK signal and the WEX signal are output from the 64M DRAM 6,
7 are correctly input to the RASK signal input terminal and the WEX signal input terminal.

From the terminals T12 and T13 of the DRAM controller 1, a first 64M DRAM (here, 64M DRA)
1st 64M which is CASHX signal and CASLX signal for M6)
The DRAM CASHX signal and the 1st 64M DRAM CASLX signal are output, respectively.
The st 64M DRAM CASLX signal is correctly input to the CASHX signal and CASLX signal input terminals of the 64M DRAM 6.

From the terminals T14 and T15 of the DRAM controller 1, a second 64M DRAM (here, 64M DRA)
2nd 64M which is CASHX signal and CASLX signal for M7)
The DRAM CASHX signal and the 2nd 64M DRAM CASLX signal are output, respectively.
The nd 64M DRAM CASLX signal is correctly input to the CASHX signal and CASLX signal input terminals of the 64M DRAM 7.

From the terminals T18 and T19 of the DRAM controller 1, a first 64M DRAM (here, 64M DRA)
Since the signals of DA10 and DA11, which are the eleventh and twelfth DA signals for M6), are output, the signals DA10 and DA11 are output.
11 are correctly input to the input terminals of the signals DA10 and DA11 of the 64M DRAM 6.

From the terminals T20 and T21 of the DRAM controller 1, a second 64M DRAM (here, 64M DRA)
Since the signals of LA10 and LA11, which are the eleventh and twelfth DA signals for M7), are output, LA10 and LA11 are output.
11 are correctly input to the input terminals of the signals DA10 and DA11 of the 64M DRAM 7.

Further, the terminal T2 of the DRAM controller 1
Since the DRAM RD signal and the 245 buffer G enable signal are output from T23 and T23, respectively, the DRAM RD signal and the 245 buffer G enable signal are output from the 64M DRAM.
It is correctly input to the input terminals of the DRAM RD signal and the enable signal of 6, 7.

Thus, the 64M DRAMs 6 and 7 have D
Various control signals output from the RAM controller 1 can be correctly received.
It is possible to operate under the control of.

As described above, according to the present embodiment, 64M
Two types of DR, DRAM and 16M DRAM
The AM can be controlled, and the DRAM can be appropriately selected and used. Therefore, versatility is significantly improved,
It becomes very convenient.

Further, according to the present embodiment, 64 generated internally by each of decoder 11 and decoder 12 is used.
22 control signals and 16M DRA for MDRAM
The 22 control signals for M are arbitrarily selected according to the connection status of the DRAM, and a common terminal is used to output control signals that need not be output simultaneously. Therefore, the number of output terminals is 23 and the decoder 11
And the total number of control signals generated by each of the decoder 11 and the decoder 12 is larger than the number of control signals individually output by the decoder 12.
The number is significantly less than four, and increases in size and cost can be suppressed.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the control device according to the present invention is applied to the DRAM controller, but the control target is not limited to the DRAM, and the present invention can be applied to a wide range of control devices for controlling any control target. It is.

In the above embodiment, the control target is 64M
Although the DRAM and the 16M DRAM are used, a DRAM having another capacity may be controlled, or a plurality of types of DRAs having the same capacity and different types may be used.
M may be the control target.

In the above embodiment, only two decoders are provided as control signal generating means.
Three or more control signal generating means may be provided.

In the above embodiment, a 64M DRAM is used.
When using, terminals T16 and T17 are not used,
If the DRAM RD signal and the 245 buffer G enable signal are output to the terminals T16 and T17, the terminals T22 and T23 can be omitted, and the number of output terminals can be controlled by the decoders 11 and 12 individually. The number can be the same as the number of signals, and the number of output terminals can be minimized.

In addition, various modifications can be made without departing from the gist of the present invention.

[0076]

According to the present invention, there is provided a control device which can arbitrarily connect a plurality of different types of controlled objects and controls the operation of the controlled objects by applying a predetermined control signal to the connected controlled objects. A plurality of control signal generating means provided corresponding to each of the plurality of types of control objects, generating and outputting control signals to be provided to the corresponding control objects, and all of the plurality of control signal generation means outputting A plurality of control terminals having a smaller number of output terminals than the number of control signals, and a predetermined control signal according to an external instruction is selected from among the control signals output by the plurality of control signal generation means, and the selected control signal is selected. Selecting means for outputting a signal from an output terminal associated with each control signal in advance among the plurality of output terminals, so that a plurality of control signal generating means of the output terminal output the signal. While controlling the number of control signals to be smaller than the number of all control signals, a required control signal among the control signals output from the plurality of control signal generation means is selected and output from these output terminals. Makes it possible to control an arbitrary control target. As a result, it is possible to provide a control device capable of controlling a plurality of types of control targets arbitrarily connected while suppressing an increase in the number of pins in an interface. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of a DRAM controller configured by applying a control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between selection of a control signal in a selector 13 in FIG. 1 and an output terminal of the selected control signal.

FIG. 3 is a diagram showing an example of a mode in which only one to five 16M DRAMs are connected and these 16M DRAMs are controlled;

FIG. 4 is a diagram showing a configuration in which a 64M DRAM and a 16M DRAM are connected one by one, and the 64M DRAM and the 16M DRA are connected.
The figure which shows an example of the form which controls M.

FIG. 5 is a diagram showing an example of a form in which two 64M DRAMs are connected and the two 64M DRAMs are controlled.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... DRAM controller 11,12 ... Decoder 13 ... Selector T0-T23 ... Terminal 2,3 ... 16M DRAM 4 ... CPU 5 ... Level conversion circuit 6,7 ... 64M DRAM

Claims (1)

[Claims] 1. A control device capable of arbitrarily connecting a plurality of different types of control targets, and controlling the operation of the control targets by applying a predetermined control signal to the connected control targets. A plurality of control signal generating means provided corresponding to each of the objects and generating and outputting a control signal to be given to the corresponding control object, the number of all the control signals output by the plurality of control signal generating means It has a small number of output terminals and selects a predetermined control signal according to an external instruction from among the control signals output by the plurality of control signal generation means, and outputs the selected control signal to the plurality of output terminals. A control unit for outputting, from among the terminals, an output terminal associated with each control signal in advance.